MiniProject#1

Due on Jan. 15, 2023

In this mini project, by using the FEOL CMOS process provided from Integrated Circuit

Processing Technologies as your starting template, please modify the template to meet the following

specifications.

Here is your working sequence:

(1) Enter the workstation through MobaXterm. (2) Creating your command (XXX.in) in Deckbuild

input deck (3) Run your Deckbuild input deck by using command “Your file’s name XXX.in”)

Use the following process steps and the extra steps given in the lecture to complete your

simulation for Miniproject#1

# Specifications:

(1) Channel length = 0.13 μm.

(2) Spacer length = 0.13 μm.

(3) Gate oxide thickness = 5±2 nm.

Required items in your report for Miniproject#1

1. Plot FEOL CMOS process .str files of the following process steps

(1) STI process.

(2) Well define and drive in.

(3) Vt adjust implant.

(4) Poly define.

(5) LDD implant.

(6) Spacer process.

(7) Source/Drain implant.

2. Upload your .in file along with your report to eeclass.

Note that the template used here is FEOL CMOS process, please follow and modify the

corresponding command of the template step by step to complete your mini project.
 MinProject#2
Due on Jan. 15, 2023

In this mini project, by using the Metal-Oxide-Semiconductor Field-Effect Transistors

(MOSFETs) provided from slide 222 to 261 as your starting template, please modify the template to

meet the following specifications.

Here is your working sequence:

(1) Enter the workstation through MobaXterm. (2) Creating your command (XXX.in) in Deckbuild

input deck (3) Run your Deckbuild input deck by using command “Your file’s name XXX.in”)

Use the following MOSFETs structure and MOSFETs design Space to design your simulation

for Mini Project#2

MOSFETs structure

MOSFETs design Space

#Specifications:
1. Channel length = 0.13 μm.
2. Gate oxide thickness = 2±1 nm.
3. Adequate threshold voltage = 0.5 ± 0.1 V.

#Output: (in A4 format)

(1) Generate the 0.13μm device mesh for N-MOSFETs and P-MOSFETs. (as Figure 1)
(2) Plot Id-Vg at Vds=0.05, 1V for N-MOSFETs and P-MOSFETs. (as Figure 2)
(3) Plot Id-Vd at Vgs=0.4, 0.6, 0.8, 1V for N-MOSFETs and P-MOSFETs. (as Figure 3)
(4) Shows the threshold voltage (Vt) and subthreshold swing (SS) of your devices at Vds= 0.05, 1 V
(as Figure4)
(5) Plot Id-Vg at Vds= 0.05 and Vgs=-3 to 3V for NMOSFETs and PMOSFETs C-V Characteristics
(as Figure 5)
(6) Please make a cutline at y=0.001 position and plot energy band-diagram at (Vd,Vg)= (0,0) and (1,1) as
Figure 6.
(7) Upload all .in file.

#Sample Plots:
 Figure 1

NMOSFETs
PMOSFETs

Figure 2

NMOSFETs
PMOSFETs

Figure 3

Figure 4

Figure 5
Figure 6