Introduction to Altera DE2-115

ITI 1100A – Winter 2017 January, 2017

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IMAGINE Lab
 Outline
• Introduction
• Altera FPGA circuit board (DE2-115)
• Quartus II 13.0 design software
• Detailed example through the software
• What we (TAs) expect from students
• Attendance
• Prelab
• Demonstration of work
• Reports

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 Altera FPGA DE2-115
•A Field Programmable Gate Array (FPGA) is a Programmable
Logic Device (PLD) with higher densities and capable of
implementing different logic functions in a short period of time.

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 Altera FGPA DE2-115

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Design, Simulation and Verification Process

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VHDL Model UP-1 Development Board
 Quartus II 13.0

Already installed in you lab PCs

Do NOT try to download and install in lab PCs

IF you want, for your laptops (optional)

• Quartus Version 13.0 web edition can be downloaded from the

Internet
• Google for Quartus 13.0 sp1, fill registration form and download with Cyclone IV
support

• Different versions (including latest) might not have device support

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 How to start Quartus (Lab PCs)

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 How to start Quartus cont…

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 Start new project from Welcome screen

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Start new project from FILE menu

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 New Project Wizard

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 New Project Wizard

It is very important to create the project in an accessible location

Never create it in the original software installation directory in C:\ drive

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 New Project Wizard

If you like to add previously designed files

to the new project

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 New Project Wizard

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 New Project Wizard

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 New Project Wizard

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 New Project Wizard

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 New Project Created

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 Step 1: Design

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VHDL Model UP-1 Development Board
 Step 1: Design

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 Step 1: Design

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 Step 1: Design

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 Step 1: Design

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 Step 1: Design

Shortcut for inputs

and outputs

Avoid overlapping
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connections
 Step 2: Compile

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VHDL Model UP-1 Development Board
 Step 2: Compile

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 Step 2: Compile

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Assigning pins:
Connecting Inputs and Outputs to switches and LEDs

Internally connected

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Assigning pins: Two Ways
Can be done in two ways
Assignment Editor Pin Planner

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Illustrated in following slides Explained in lab manual (Chapter 4)
Assigning pins: Assignment Editor

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Assigning pins: Assignment Editor

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Assigning pins: Assignment Editor

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Assigning pins: Assignment Editor

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Assigning pins: Assignment Editor

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Assigning pins: Compile To Apply Changes

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 Step 3: Simulate

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VHDL Model UP-1 Development Board
 Step 3: Simulate

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 Step 3: Simulation pane

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 Save the Simulation file

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 Step 3: Simulate

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 Step 3: Simulate

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 Step 3: Simulate

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 Step 3: Simulate

Doubling periods will

guarantee every possible
combination of inputs

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 Step 3: Simulate

Adjust end time to cover at

least one full set of input
combinations.

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 Step 3: Simulate

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 Step 3: Simulate

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 Step 3: Simulate

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 Step 3: Simulate

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 Step 3: Simulate
Simulation Input

Simulation output

Take a screenshot
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Do not put Simulation input instead.
 Step 4: Programming & Verification

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VHDL Model UP-1 Development Board
 Step 4: Programming & Verification

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 Step 4: Programming & Verification

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 Step 4: Programming & Verification

Might need to close and open this window few times

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 Step 4: Programming & Verification

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 Step 4: Programming & Verification

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 Step 4: Programming & Verification

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 Attendance and Pre-Labs
Attendance
• Students are expected to work on labs in groups of two.
• Attendance will be taken for all Labs.
• If a group member is not shown, a ZERO mark will count for him/her.
• Only medical and other emergencies will be considered for rescheduling of labs
Pre-Labs
• Pre-labs for all parts will be checked by TAs before the starting of the lab.
• One hand written or printed pre-lab is sufficient per group
• Pre-lab but marks are awarded based on how each group member answer
questions asked by TAs

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 Demonstration
Explaining Simulation and Experimental Results to TAs
• After completing design, simulation and verification steps for each part/circuit,
please call a TA to demonstrate your work
• Leaving the lab without showing your fully or partially completed work will result
in zero marks
• Group members must demonstrate correct operation of their circuits
• The TA will ask few questions to verify that the experiment was done by group
members with sound theoretical background.
• Failing to explain simulation and experimental results may result in lesser marks

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 Laboratory Report

• Take screenshots of schematic designs and simulation outputs

to include into report
• Lab report format will be available in blackboard
• Students shall submit one lab report per group on blackboard.

Total marks = Pre-lab + Simulation & demonstration + Final report

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 Thank You

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