COEN 6341 Assignment: 2

Priyesh Arvindbhai Bhalala Student ID: 40217267

1. [10pts] Compare two methods of responding to external events: polling and interrupts. Discuss the
advantages and disadvantages of each approach.

ANS.

Polling and interrupts are two common methods used in computer systems to respond to external events.

Polling is a method where the system periodically checks for the occurrence of an event by repeatedly querying the
device or system being monitored. In this method, the system continuously sends a request for information and
waits for a response.

Interrupts, on the other hand, are a method where the device or system being monitored sends a signal to the
processor to indicate the occurrence of an event. When an interrupt occurs, the processor stops its current operation
and executes a special routine known as an interrupt service routine (ISR) to handle the event.

Advantages of Polling:

• Simple to implement and easy to understand.

• Predictable response time as the system checks for events periodically.
• Can work well for low-speed devices with predictable event rates.

Disadvantages of Polling:

• High CPU utilization as the system must continuously poll for events, leading to a waste of system
resources.
• Delayed response time as the system may not detect the event immediately, leading to a slower reaction to
time-critical events.
• Can lead to inaccurate results if the polling frequency is too slow or too fast.

Advantages of Interrupts:

• Efficient use of system resources as the system only processes events as they occur, leading to lower CPU
utilization.
• Immediate response time as the processor can quickly respond to time-critical events.
• Accurate results as the system only processes events when they occur.

Disadvantages of Interrupts:

• More complex to implement and understand.

• Difficult to predict response time as interrupts may occur at any time, leading to unpredictable system
behavior.
• Can lead to priority inversion, where a higher-priority interrupt may be blocked by a lower-priority interrupt
that is currently being processed.
2. [5pts] Discuss the process for data acquisition from an input device when polling technique is used.

ANS.

When polling is used for data acquisition from an input device, the following process typically occurs:

i. The system sends a request to the input device, asking for data.
ii. The input device responds to the request by sending the requested data back to the system.
iii. The system receives the data and processes it as required.
iv. The system then repeats the process, sending another request for data to the input device at a
predetermined interval.

This process is repeated continuously, with the system polling the input device at regular intervals to check for new
data. The interval between polling requests can be adjusted depending on the specific requirements of the system,
but it should be frequent enough to ensure that the system does not miss any important data.

3. [5pts] Three devices are attached to a microprocessor: Device 1 has the highest priority and device
3 has the lowest priority. Each device’s interrupt handler takes 5-time units to execute. Show what
interrupt handler (if any) is executing at each time given the sequence of device interrupts displayed
below:

ANS.

According to the device priority given and each device’s interrupt handler takes 5 time units to execute the sequence
of executing the interrupt and time when execution of particular interrupt for the respective device is

i. Device 1 (1st priority) - 5 time units - executed

ii. Device 2 (2nd priority) – 10 time units – executed
iii. Device 3 (3rd priority) – 15 time units – executed
iv. Device 3 (3rd priority) – execution is terminated at 20 time units because device 1 interrupt occurred
v. Device 1 (1st priority) – 25 time units – executed
vi. Device 2 (2nd priority) – 30 time units – executed
vii. Device 3 (3rd priority) – 35 time units – interrupt mentioned in (iv) is executed.
viii. Device 3 (3rd priority) – 40 time units – executed.
4.
ANS.

To configure pin 3 as an output for the LED and pin 4 as an input for the switch on GPIO port B, the following
memory addresses need to be used:

To configure pin 3 as an output, we need to set the corresponding bits in the GPIOB_MODER register. Since pin 3
is associated with bits 6-7 in the register, we need to set bits 6-7 to 01 to configure the pin as a general-purpose
output. The memory address for the GPIOB_MODER register is calculated as follows:

GPIOB_MODER = GPIOB_BASE + 0x00 = 0x48000400 + 0x00 = 0x48000400

To configure pin 4 as an input, we need to set the corresponding bits in the GPIOB_MODER register. Since pin 4
is associated with bits 8-9 in the register, we need to set bits 8-9 to 00 to configure the pin as an input. The memory
address for the GPIOB_MODER register is the same as above.

To read the input provided by the switch connected to pin 4, we need to read the corresponding bit in the
GPIOB_IDR register. Since pin 4 is associated with bit 4 in the register, we need to read bit 4 to determine the state
of the switch. The memory address for the GPIOB_IDR register is calculated as follows:

GPIOB_IDR = GPIOB_BASE + 0x10 = 0x48000400 + 0x10 = 0x48000410

To write the output for the LED connected to pin 3, we need to set the corresponding bit in the GPIOB_ODR
register. Since pin 3 is associated with bit 3 in the register, we need to set bit 3 to 1 to turn on the LED. The memory
address for the GPIOB_ODR register is calculated as follows:

GPIOB_ODR = GPIOB_BASE + 0x14 = 0x48000400 + 0x14 = 0x48000414

Therefore, to configure the pins and read/write the input/output on GPIO port B for the given scenario, the memory
addresses used are GPIOB_MODER (0x48000400) for pin mode configuration, GPIOB_IDR (0x48000410) for
reading input from pin 4, and GPIOB_ODR (0x48000414) for writing output to pin 3.

5. [10pts] Assume an input device is connected to the SPI3 port on an STM32L4 microcontroller.
Discuss where the handler for dealing with interrupts generated from that device is located in
memory.

ANS.

The handler for dealing with interrupts generated from an input device connected to the SPI3 port on an STM32L4
microcontroller is located in the interrupt vector table (IVT) in memory. The IVT is a table of memory addresses
that contains the location of the interrupt service routine (ISR) for each interrupt source in the system.

When an interrupt occurs, the microcontroller reads the interrupt number from a hardware register and uses it as an
index to look up the corresponding memory address in the IVT. This memory address points to the ISR for the
interrupt source that triggered the interrupt. The microcontroller then jumps to this memory address and begins
executing the ISR.

The handler for dealing with interrupts generated from the input device connected to the SPI3 port on an STM32L4
microcontroller is typically located in the Interrupt Vector Table (IVT) in memory.

In the case of STM32L4 microcontroller, the IVT is usually located at address 0x0800 0000.

When an interrupt is generated from the input device, the microcontroller interrupts its normal program flow, looks
up the corresponding interrupt handler address in the IVT, and jumps to that location in memory to execute the
interrupt handler code.
6. [10pts] Discuss the motivation and the process for stacking and unstacking when the CPU is dealing
with an interrupt.

ANS.

The motivation for stacking and unstacking when the CPU is dealing with an interrupt is to preserve the context of
the interrupted code and ensure that the CPU can return to the correct execution point once the interrupt is complete.

When an interrupt occurs, the CPU must stop executing the current code and transfer control to the interrupt service
routine (ISR) that will handle the interrupt. However, before the ISR can execute, the CPU must save the state of
the interrupted code by storing the contents of the CPU registers onto a stack. This process is known as stacking.

The process of stacking involves pushing the contents of the CPU registers onto the stack in a specific order to
ensure that they can be restored correctly when the ISR is complete. The order in which registers are stacked may
depend on the architecture of the CPU, but typically the program counter (PC) is pushed first, followed by the status
register (SR) and other registers in a specific order.

Once the ISR has completed, the CPU must return to the interrupted code and continue execution from the point
where it was interrupted. To do this, the CPU must restore the context of the interrupted code by retrieving the
contents of the CPU registers that were stacked earlier. This process is known as unstacking.

The process of unstacking involves popping the contents of the CPU registers from the stack in reverse order to that
in which they were stacked. Once all the registers have been restored, the CPU can resume execution of the
interrupted code from the point at which it was interrupted.

7. [5pts] What is the average memory access time of a machine whose hit rate is 96%, with a cache
access time of 3ns and a main memory access time of 70ns?

ANS.

The average memory access time can be calculated using the following formula:

Average access time = Hit rate × Cache access time + Miss rate × Main memory access time

where Miss rate = 1 - Hit rate

Substituting the given values, we get:

Average access time = 0.96 × 3ns + 0.04 × 70ns

= 2.88ns + 2.8ns

= 5.68ns
8. [10pts] Explain the process for address translation when the segmented memory organization is
used.

ANS.

Segmented memory organization is a memory management technique used by operating systems to allow programs
to be divided into smaller logical units called segments. Each segment is assigned a unique identifier called a
segment number, and can have a different size, which provides flexibility in managing memory allocation.

Address translation in segmented memory organization is a process that maps logical addresses generated by a
program to physical memory addresses. It is achieved through the following steps:

i. The program generates a logical address that consists of two parts: the segment number and an offset within
the segment.
ii. The segment number is used as an index to locate the corresponding segment descriptor in a table
maintained by the operating system.
iii. The segment descriptor contains information about the segment, such as its base address in physical
memory and its length.
iv. The base address of the segment is added to the offset to generate the physical address.
v. The operating system then checks if the resulting physical address is valid (i.e., it falls within the bounds
of physical memory).
vi. If the physical address is valid, the program can access the data stored at that address. If the physical address
is not valid, the operating system raises an exception or error.

9.

ANS.

a) Direct-mapped cache memory:

Instruction Address Block Index Block Address Tag Cache Line Cache Content
MOV r0,#0 0x08000160 0 0x08000140 0x0800014 0 0x00000000
LDR r1,#10 0x08000164 1 0x08000140 0x0800014 0 0x0000000A
MOV r2,#0 0x08000168 2 0x08000140 0x0800014 0 0x00000000
ADR r3,c 0x0800016C 3 0x08000160 0x0800016 0 0x08000160
ADR r5,x 0x08000170 4 0x08000160 0x0800016 1 0x08000160
loop 0x08000174 5 0x08000160 0x0800016 1 0x08000160
CMP r0,r1 0x08000178 6 0x08000160 0x0800016 1 0x08000160
BGE loopend 0x0800017C 7 0x08000160 0x0800016 1 0x08000160
LDR r4,[r3,r0] 0x08000180 8 0x08000160 0x0800016 1 0x00000000
LDR r6,[r5,r0] 0x08000184 9 0x08000160 0x0800016 1 0x00000000
MUL r4,r4,r6 0x08000188 10 0x08000160 0x0800016 1 0x00000000
ADD r2,r2,r4 0x0800018C 11 0x08000160 0x0800016 1 0x00000000
ADD r0,r0,#1 0x08000190 12 0x08000160 0x0800016 1 0x00000001
B loop 0x08000194 13 0x08000160 0x0800016 1 0x08000160
b) A 2-way set-associative cache memory is used.

Instruction Address Cache Set Cache Line 0 Cache Line 1

MOV r0,#0 0x08000160 0 0x08000160: 0x0000
LDR r1,#10 0x08000162 1 0x08000160: 0x000A
MOV r2,#0 0x08000164 0 0x08000164: 0x0000
ADR r3,c 0x08000166 1 0x08000160: 0x08010000
ADR r5,x 0x08000168 0 0x08000168: 0x08010040
CMP r0,r1 0x0800016A 1 0x08000160: 0x000A
BGE loopend 0x0800016C 0 0x0800016C: 0xE7FE
LDR r4,[r3,r0] 0x0800016E 1 0x08010160: 0x0001
LDR r6,[r5,r0] 0x08000170 0 0x08010040: 0x0001
MUL r4,r4,r6 0x08000172 1 0x08010260: 0x0001
ADD r2,r2,r4 0x08000174 0 0x08000174: 0x0001
ADD r0,r0,#1 0x08000176 1 0x08000160: 0x0001
B loop 0x08000178 0 0x08000178: 0xEAFF