UVM Meeting 4 23-11-21

UVM – Chapter 2 content
Chapter 3: UVM reporting macros

Content:
●
UVM reporting macros
– ùvm_info
– ùvm_warning
– ùvm_error
– ùvm_fatal
●
Verbosity control
UVM – UVM reporting
UVM reporter class name is uvm_report_server. However, UVM contains a series of
wrappers for using the reporting service, report macros.
Report method Severity Verbosity Numeric value
uvm_fatal FATAL UVM_NONE(implicit) 0
uvm_error ERROR UVM_NONE(implicit) 0
uvm_warning WARNING UVM_NONE(implicit) 0
uvm_info INFO UVM_NONE 0
UVM_LOW 100
UVM_MEDIUM (default) 200
UVM_HIGH 300
UVM_FULL 400
UVM_DEBUG 500
Lab. This Lab shows how to use uvm reporting macros for displaying messages,
warnings, errors, and fatal reports.
Note that verbosity

cannot be changed
Lab. This Lab shows how to use uvm reporting macros for printing variables in the
console using $sformatf, variables can be printed in different formats, such as, binary,
decimal, and, hexadecimal.
Assignment 1. This assignment consists of displaying four variables in the console,
three 4-state and one 2-state variables in hexadecimal format using UVM reporting
macros.
Assignment 1. This assignment consists of displaying four variables in the console,
three 4-state and one 2-state variables in hexadecimal format using UVM reporting
macros.
As shown in previous table, verbosity level can be modified to every uvm object, for
this UVM provides a series of methods for setting and getting the verbosity level.
obj o;
o.set_report_verbosity_level(UVM_NONE);
int level = o.get_report_verbosity_level;
set/get verbosity
code
UVM – Chapter 4 content
Chapter 4: UVM Classes

Content:
●
Why Object-Oriented Programming?
●
UVM component
– UVM verification components
●
UVM object
– Transaction/sequence item
UVM – Why Object-Oriented Programming?
Object Oriented Programming in SystemVerilog is supported through the class data
type.
OOP yields the following features:
●
Encapsulation: to create containers of data along with their behaviors.
type.
●
●
Inheritance: ability to extend or override the containers with new data or new
behaviors.
type.
●
●
behaviors.
●
Data hiding: hide the complexity of the implementation, by creating a hierarchical
software model (different levels of abstraction).
type.
●
●
behaviors.
●
●
Generic programming: ability to reuse the same code with different applications
(parametrization).
type.
●
●
behaviors.
●
●
Generic programming: ability to reuse the same code with different applications
(parametrization).
●
Polymorphism: concept that provides to the same code to have different behaviors.
What these features means to verification?
Classes can be used to model:
●
Reusable verification environments
●
Abstract highly reusable data & methods that operate on them
Class types define a collection of data(properties) and methods, which are encapsulated
in a class
Class declaration does not

allocate any storage,
it only creates a new type.
The variables inside a class are called class properties. Class properties can be of any
type, including other class variables.
Properties of a class can be accesses using the object handler.
module tb;
class dummy; dummy d; // Class handler
// Data members // initial begin // procedural block
bit [7:0] A; // class property d = new(); // allocate memory for d object
string str; d.A = 8'h3B;
// Data members // d.str = “Hola”;
endclass end
endmodule
The functions and tasks inside a class are called class methods.
Properties of a class can be accesses using the object handler.
module tb;
class dummy;
dummy d; // Class handler
bit [7:0] A; // class property
initial begin // procedural block
function void print(string s);
d = new(); // allocate memory for d object
$display(s);
d.A = 8'h3B;
endfunction
d.print(“Hola”); // calling print method
endclass
end
endmodule
Lab: This lab presents how structures can be used with SystemVerilog.
Lab: This lab presents how classes can be used with SystemVerilog.
Assignment. This assignment consists of generating random stimulus for the input ports
of the following module using class-based coding. Use a class method to print the values
in hex. Hint: use randomize() class method.
bit A [15:0]
bit B [15:0] Z [15:0]
Z = f(A,B,En)
bit En
Assignment. This assignment consists of generating random stimulus for the input ports
of the following module using class-based coding. And print the values in hex.
Class methods can also have input arguments, just as conventional programming
functions.
this keyword
distinguishes
class member
from method
local variable
Lab: This Lab shows how class inheritance can be used to extend an existing class, by
adding new features, this feature is widely used in UVM testbench, thus, it is important
to understand its behavior and advantages.
Class inheritance
code
Class methods can be overridden in a child class. This can be only done with methods
declared as virtual in parent class.
virtual function void fnct(); virtual task tsk();
endfunction endtask
Lab: This Labs shows how methods of parent class, can be redefined within a child
class by declaring methods in parent class as virtual. Virtual methods are used to apply
polymorphism dynamically (i.e. at run-time). NOTE: Constructor function must always
be non-virtual function.
Class inheritance
code
Class inheritance
Code 2

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UVM – Chapter 2 content

Chapter 3: UVM reporting macros

Note that verbosity

Chapter 4: UVM Classes

Class declaration does not

class dummy; dummy d; // Class handler

// Data members // initial begin // procedural block

bit [7:0] A; // class property d = new(); // allocate memory for d object

string str; d.A = 8'h3B;

// Data members // d.str = “Hola”;

virtual function void fnct(); virtual task tsk();

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