Buck-Boost Converter with a Wide Voltage Conversion for the USB PD 3.

1 Standard
(Jan 2023 - Present)
 Design a nine-switch buck-boost convertor in TSMC 65-nm CMOS technology in Cadence.
 The specifications are
Supply voltage (VDD) 6 – 28V
Output voltage (VO) 5 – 48V
Output current (IO) 5A
 The power stage is constructed by discrete components including power transistors, gate drivers,
a power inductor and two flying capacitors.
 A field-programmable gate arrays (FPGA) board is used to develop the controller’s algorithms to
realize the proposed nine switching combinations.
 The selections of discrete components are focused on both the cost and volume of the circuit
board.
 A prototype of the conventional four-switch buck-boost converter controlled by the FPGA board
is built for comparison and used to prove the enhanced efficiency performance by the proposed
hybrid buck-boost structure.

Buck–Boost Converter Design (Nov 2022 – Jan 2023)

 Reproducing two circuits in papers called A Hybrid Structure Dual-Path Step-Down Converter
With 96.2% Peak Efficiency Using 250-m Large-DCR Inductor and Bidirectional Buck–Boost
Converter With Reduced Power Loss and No Right-Half-Plane Zero in MATLAB/Simulink.
 The specifications of paper 1 circuit are
Supply voltage (VDD) 4.5V
Output voltage (VO) 2.4V
Output current (IO) 1A
Working frequency 1MHz
 The specifications of paper 2 circuit are
Supply voltage (VDD) 3.7V/7.4V
Output voltage (VO) 5V
Output current (IO) 1A
Working frequency 500kHz
 Using a digital loop compensation (PID) in Simulink.
 Calculate the compensation and the transfer function in MATLAB.

Boost Converter Design with Average Current Mode Modulator Design

(Sep 2022 – Nov 2022)
 Design a ACM controlled boost converter in LTspice.
 The specifications are
Supply voltage (VDD) 3V
Output voltage (VO) 6V
Working frequency 500kHz
Output current (IO) 1A – 10A
 Design it use current mode control.
 Using PI (lag) compensators in inner current loop and outer voltage loop.
Buck Converter Design (May 2022 – Aug 2022)
 Design a synchronous switching CMOS buck converter with a feedback control in a 3.3V/5V
mixed-signal CMOS 0.6-µm technology in HSpice.
 The control method is PWM control (1MHz, IO = 100–350mA in CCM).
 The power efficiency is >85%.
 The specifications are
Supply voltage (VDD) 3.6V
Output voltage (VO) 1.8V
Temperature range (T) 27°C

Low-Power CMOS LDO Design (May 2022 – Aug 2022)

 Design a CMOS linear regulator in a 3.3V/5V mixed-signal CMOS 0.6-µm technology in
HSpice.
 The specifications are
Supply voltage (VDD) 3.4V to 4.2V (Li-ion battery without charger)
Ground voltage (IDD - IO) < 50A
Output voltage (VO) 3V
Output current (IO) 0 – 100mA
Temperature range (T) -15°C to 85°C
Steady-state line, load and temperature error Within 3V1%
PSRR < -20dB for freq  1GHz
Output noise < 10V/sqrt Hz@100Hz and < 0.5V/sqrt Hz@1MHz
No-load (IO = 0) startup (> 3V-2%) < 2ms
Load transient (TS with 1% accuracy) < 5s with less than 50mV voltage spikes (tested by
0100mA and 100mA0 steps in 10ns)
On-chip resistance < 2M for high-resistive poly < 100k for poly
On-chip capacitance < 50pF
Off-chip capacitance < 10F (using standard value)
 An embedded voltage reference.
 The bias currents and voltages were generated by circuits.