WEEK 13:: Objectives

WEEK 13: Arithmetic Logic Unit, Binary Integer Representation, Binary Integer
Arithmetic, Binary Floating-Point Representation

Objectives:
At the end of the lesson the learner will be able to:
Define ALU
Identify the different types of arithmetic operations used in ALU
Apply the binary integer representation
Describe the floating-point representation
ARITHMETIC LOGIC UNIT (ALU)
An arithmetic logic unit (ALU) is a combinational digital electronic circuit that

performs arithmetic and bitwise operations on integer binary numbers. This is in
contrast to a floating-point unit (FPU), which operates on floating point numbers. An
ALU is a fundamental building block of many types of computing circuits, including
the central processing unit (CPU) of computers, FPUs, and graphics processing
units (GPUs). A single CPU, FPU or GPU may contain multiple ALUs.
The inputs to an ALU are the data to be operated on, called operands, and a code
indicating the operation to be performed; the ALU's output is the result of the
performed operation. In many designs, the ALU also has status inputs or outputs, or
both, which convey information about a previous operation or the current operation,
respectively, between the ALU and external status registers.
It is the part of a computer that performs all arithmetic computations, such as addition
and multiplication, and all comparison operations. The ALU is one component of
the CPU(central processing unit).
1|Page COMPUTER ORGANIZATION AND ARCHITECTURE

SIGNALS
An ALU has a variety of input and output nets, which are the electrical
conductors used to convey digital signals between the ALU and external circuitry.
When an ALU is operating, external circuits apply signals to the ALU inputs and, in
response, the ALU produces and conveys signals to external circuitry via its outputs.
Data
A basic ALU has three parallel data buses consisting of two input operands (A and B)
and a result output (Y). Each data bus is a group of signals that conveys one binary
integer number. Typically, the A, B and Y bus widths (the number of signals
comprising each bus) are identical and match the native word size of the external
circuitry (e.g., the encapsulating CPU or other processor).
Opcode
The opcode input is a parallel bus that conveys to the ALU an operation selection code,
which is an enumerated value that specifies the desired arithmetic or logic operation to
be performed by the ALU. The opcode size (its bus width) determines the maximum
number of different operations the ALU can perform; for example, a four-bit opcode
can specify up to sixteen different ALU operations. Generally, an ALU opcode is not
the same as a machine language opcode, though in some cases it may be directly
encoded as a bit field within a machine language opcode.
Outputs
The status outputs are various individual signals that convey supplemental
information about the result of the current ALU operation. General-purpose ALUs
commonly have status signals such as:
 Carry-out, which conveys the carry resulting from an addition operation, the borrow
resulting from a subtraction operation, or the overflow bit resulting from a binary
shift operation.
 Zero, which indicates all bits of Y are logic zero.
 Negative, which indicates the result of an arithmetic operation is negative.

 Overflow, which indicates the result of an arithmetic operation has exceeded the
numeric range of Y.
 Parity, which indicates whether an even or odd number of bits in Y are logic one.
At the end of each ALU operation, the status output signals are usually stored in
external registers to make them available for future ALU operations (e.g., to
implement multiple-precision arithmetic) or for controlling conditional branching. The
collection of bit registers that store the status outputs are often treated as a single,
multi-bit register, which is referred to as the "status register" or "condition code
register".
Inputs
The status inputs allow additional information to be made available to the ALU when
performing an operation. Typically, this is a single "carry-in" bit that is the stored
carry-out from a previous ALU operation.
CIRCUIT OPERATION
An ALU is a combinational logic circuit, meaning that its outputs will change
asynchronously in response to input changes. In normal operation, stable signals are
applied to all of the ALU inputs and, when enough time (known as the "propagation
delay") has passed for the signals to propagate through the ALU circuitry, the result of
the ALU operation appears at the ALU outputs. The external circuitry connected to the
ALU is responsible for ensuring the stability of ALU input signals throughout the
operation, and for allowing sufficient time for the signals to propagate through the
ALU before sampling the ALU result.
In general, external circuitry controls an ALU by applying signals to its inputs.
Typically, the external circuitry employs sequential logic to control the ALU operation,

which is paced by a clock signal of a sufficiently low frequency to ensure enough time
for the ALU outputs to settle under worst-case conditions.
For example, a CPU begins an ALU addition operation by routing operands from their
sources (which are usually registers) to the ALU's operand inputs, while the control
unit simultaneously applies a value to the ALU's opcode input, configuring it to
perform addition. At the same time, the CPU also routes the ALU result output to a
destination register that will receive the sum. The ALU's input signals, which are held
stable until the next clock, are allowed to propagate through the ALU and to the
destination register while the CPU waits for the next clock. When the next clock
arrives, the destination register stores the ALU result and, since the ALU operation has
completed, the ALU inputs may be set up for the next ALU operation.
The combinational logic circuitry of the 74181 integrated circuit, which is a simple
four-bit ALU.

FUNCTIONS
A number of basic arithmetic and bitwise logic functions are commonly supported by
ALUs. Basic, general purpose ALUs typically include these operations in their
repertoires:
Arithmetic operations
 Add: A and B are summed and the sum appears at Y and carry-out.
 Add with carry: A, B and carry-in are summed and the sum appears at Y and carry-
out.
 Subtract: B is subtracted from A (or vice versa) and the difference appears at Y and
carry-out. For this function, carry-out is effectively a "borrow" indicator. This
operation may also be used to compare the magnitudes of A and B; in such cases
the Y output may be ignored by the processor, which is only interested in the status
bits (particularly zero and negative) that result from the operation.
 Subtract with borrow: B is subtracted from A (or vice versa) with borrow (carry-in)
and the difference appears at Y and carry-out (borrow out).
 Two's complement (negate): A (or B) is subtracted from zero and the difference
appears at Y.
 Increment: A (or B) is increased by one and the resulting value appears at Y.
 Decrement: A (or B) is decreased by one and the resulting value appears at Y.
 Pass through: all bits of A (or B) appear unmodified at Y. This operation is typically
used to determine the parity of the operand or whether it is zero or negative, or to
load the operand into a processor register.
Bitwise logical operations

 AND: the bitwise AND of A and B appears at Y.
 OR: the bitwise OR of A and B appears at Y.

 Exclusive-OR: the bitwise XOR of A and B appears at Y.
 Ones' complement: all bits of A (or B) are inverted and appear at Y.
Bit shift operations
Bit shift examples for an eight-bit ALU
Type Left Right
Arithmetic shift
Logical shift
Rotate
Rotate through carry
ALU shift operations cause operand A (or B) to shift left or right (depending on the
opcode) and the shifted operand appears at Y. Simple ALUs typically can shift the
operand by only one bit position, whereas more complex ALUs employ barrel
shifters that allow them to shift the operand by an arbitrary number of bits in one

operation. In all single-bit shift operations, the bit shifted out of the operand appears
on carry-out; the value of the bit shifted into the operand depends on the type of shift.
 Arithmetic shift: the operand is treated as a two's complement integer, meaning that
the most significant bit is a "sign" bit and is preserved.
 Logical shift: a logic zero is shifted into the operand. This is used to shift unsigned
integers.
 Rotate: the operand is treated as a circular buffer of bits so its least and most
significant bits are effectively adjacent.
 Rotate through carry: the carry bit and operand are collectively treated as a circular
buffer of bits.
Applications
Multiple-precision arithmetic
In integer arithmetic computations, multiple-precision arithmetic is an algorithm that
operates on integers which are larger than the ALU word size. To do this, the
algorithm treats each operand as an ordered collection of ALU-size fragments,
arranged from most-significant (MS) to least-significant (LS) or vice versa. For
example, in the case of an 8-bit ALU, the 24-bit integer 0x123456 would be treated as a
collection of three 8-bit fragments: 0x12 (MS), 0x34 , and 0x56 (LS). Since the size of a
fragment exactly matches the ALU word size, the ALU can directly operate on this
"piece" of operand.
The algorithm uses the ALU to directly operate on particular operand fragments and
thus generate a corresponding fragment (a "partial") of the multi-precision result. Each
partial, when generated, is written to an associated region of storage that has been

designated for the multiple-precision result. This process is repeated for all operand
fragments so as to generate a complete collection of partials, which is the result of the
multiple-precision operation.
In arithmetic operations (e.g., addition, subtraction), the algorithm starts by invoking
an ALU operation on the operands' LS fragments, thereby producing both a LS partial
and a carry out bit. The algorithm writes the partial to designated storage, whereas the
processor's state machine typically stores the carry out bit to an ALU status register.
The algorithm then advances to the next fragment of each operand's collection and
invokes an ALU operation on these fragments along with the stored carry bit from the
previous ALU operation, thus producing another (more significant) partial and a carry
out bit. As before, the carry bit is stored to the status register and the partial is written
to designated storage. This process repeats until all operand fragments have been
processed, resulting in a complete collection of partials in storage, which comprise the
multi-precision arithmetic result.
In multiple-precision shift operations, the order of operand fragment processing
depends on the shift direction. In left-shift operations, fragments are processed LS first
because the LS bit of each partial—which is conveyed via the stored carry bit—must be
obtained from the MS bit of the previously left-shifted, less-significant operand.
Conversely, operands are processed MS first in right-shift operations because the MS
bit of each partial must be obtained from the LS bit of the previously right-shifted,
more-significant operand.
In bitwise logical operations (e.g., logical AND, logical OR), the operand fragments
may be processed in any arbitrary order because each partial depends only on the
corresponding operand fragments (the stored carry bit from the previous ALU
operation is ignored).
Complex operations
Although an ALU can be designed to perform complex functions, the resulting higher
circuit complexity, cost, power consumption and larger size makes this impractical in
many cases. Consequently, ALUs are often limited to simple functions that can be
executed at very high speeds (i.e., very short propagation delays), and the external
processor circuitry is responsible for performing complex functions by orchestrating a
sequence of simpler ALU operations.
For example, computing the square root of a number might be implemented in various
ways, depending on ALU complexity:
 Calculation in a single clock: a very complex ALU that calculates a square root in one
operation.
 Calculation pipeline: a group of simple ALUs that calculates a square root in stages,
with intermediate results passing through ALUs arranged like a factory production
line. This circuit can accept new operands before finishing the previous ones and
produces results as fast as the very complex ALU, though the results are delayed by
the sum of the propagation delays of the ALU stages. For more information, see the
article on instruction pipelining.
 Iterative calculation: a simple ALU that calculates the square root through several
steps under the direction of a control unit.
The implementations above transition from fastest and most expensive to slowest and
least costly. The square root is calculated in all cases, but processors with simple ALUs
will take longer to perform the calculation because multiple ALU operations must be
performed.
Implementation
An ALU is usually implemented either as a stand-alone integrated circuit (IC), such as

the 74181, or as part of a more complex IC. In the latter case, an ALU is typically
instantiated by synthesizing it from a description written in VHDL, Verilog or some
other hardware description language. For example, the following VHDL code
describes a very simple 8-bit ALU:
entityaluis
port(-- the alu connections to external circuitry:
A:insigned(7downto0);-- operand A
B:insigned(7downto0);-- operand B
OP:inunsigned(2downto0);-- opcode
Y:outsigned(7downto0));-- operation result
endalu;
architecturebehavioralofaluis
begin
caseOPis-- decode the opcode and perform the operation:
when"000"=>Y<=A+B;-- add
when"001"=>Y<=A-B;-- subtract
when"010"=>Y<=A-1;-- decrement
when"011"=>Y<=A+1;-- increment
when"100"=>Y<=notA;-- 1's complement
when"101"=>Y<=AandB;-- bitwise AND
when"110"=>Y<=AorB;-- bitwise OR
when"111"=>Y<=AxorB;-- bitwise XOR
whenothers=>Y<=(others=>'X');
endcase;
endbehavioral;
BINARY INTEGER REPRESENTATION
A binary integer variable—also called a 0/1 variable—is a special case of an integer

variable that is required to be either zero or one. It's often used as a switch to model
Yes/No decisions.
10 | P a g e COMPUTER ORGANIZATION AND ARCHITECTURE

The syntax of the @BIN function is:
@BIN( variable_name);
where variable_name is the name of the variable you wish to make binary.
The @BIN function may be used in a model anywhere you would normally enter a
constraint. The @BIN function can be embedded in an @FOR statement to allow you
to easily set all, or selected, variables of an attribute to be binary integers. Some
examples of @BIN are:
Example 1: @BIN( X);
makes the scalar variable X a binary integer,
Example 2: @BIN( INCLUDE( 4));
makes the variable INCLUDE( 4) binary,
Example 3: @FOR( ITEMS: @BIN( INCLUDE));
makes all variables in the INCLUDE attribute binary.
BINARY INTEGER DECIMAL

The IEEE 754-2008 standard includes an encoding format for decimal floating point
numbers in which the significand and the exponent (and the payloads of NaNs) can be
encoded in two ways, referred to in the draft as binary encoding and decimal encoding.
Both formats break a number down into a sign bit s, an
exponent q (between qmin and qmax), and a p-digit significand c (between 0 and 10p−1).
The value encoded is (−1)s×10q×c. In both formats the range of possible values is
identical, but they differ in how the significand c is represented. In the decimal
encoding, it is encoded as a series of p decimal digits (using the densely packed
decimal (DPD) encoding). This makes conversion to decimal form efficient, but
requires a specialized decimal ALU to process. In the binary integer decimal (BID)
encoding, it is encoded as a binary number.

Format
Using the fact that 210 = 1024 is only slightly more than 103 = 1000, 3n-digit decimal
numbers can be efficiently packed into 10n binary bits. However, the IEEE formats
have significands of 3n+1 digits, which would generally require 10n+4 binary bits to
represent.
This would not be efficient, because only 10 of the 16 possible values of the additional
4 bits are needed. A more efficient encoding can be designed using the fact that the
exponent range is of the form 3×2k, so the exponent never starts with 11 . Using the
Decimal32 encoding (with a significand of 3*2+1 decimal digits) as an example
( e stands for exponent, m for mantissa, i.e. significand):
 If the significand starts with 0mmm , omitting the leading 0 bit lets the significand
fit into 23 bits:
s 00eeeeee (0)mmm mmmmmmmmmm mmmmmmmmmm

 If the significand starts with 100m , omitting the leading 100 bits lets the significand
fit into 21 bits. The exponent is shifted over 2 bits, and a 11 bit pair shows that this
form is being used:
s 1100eeeeee (100)m mmmmmmmmmm mmmmmmmmmm

 Infinity, quiet NaN and signaling NaN use encodings beginning with s 1111 :
s 11110 xxxxxxxxxxxxxxxxxxxxxxxxxx
s 111110 xxxxxxxxxxxxxxxxxxxxxxxxx
s 111111 xxxxxxxxxxxxxxxxxxxxxxxxx
The bits shown in parentheses are implicit: they are not included in the 32 bits of the
Decimal32 encoding, but are implied by the two bits after the sign bit.
The Decimal64 and Decimal128 encodings have larger exponent and significand fields,
but operate in a similar fashion.
For the Decimal128 encoding, 113 bits of significand is actually enough to encode 34
decimal digits, and the second form is never actually required.
Binary Representation of positive integers
Binary representations of positive can be understood in the same way as their decimal
counterparts. For example
8610 = 1*64 + 0*32 + 1*16 + 0*8 + 1*4 + 1*2 + 0*1

or
8610 = 1* 26 + 0* 25 + 1* 24 + 0* 23 + 1* 22 + 1* 21 + 0* 20
or
8610 = 1010110 2
The subscript 2 denotes a binary number. Each digit in a binary number is called a bit.
The number 1010110 is represented by 7 bits. Any number can be broken down this
way, by finding all of the powers of 2 that add up to the number in question (in this
case 26, 24, 22 and 21). You can see this is exactly analagous to the decimal
deconstruction of the number 125 that was done earlier. Likewise we can make a
similar set of observations:

 To multiply a number by 2 you can simply shift it to the left by one digit, and fill
in the rightmost digit with a 0. To divide a number by 2, simply shift the number
to the right by one digit.
 To see how many digits a number needs, you can simply take the logarithm
(base 2) of the number, and add 1 to it. The integer part of the result is the
number of digits. For instance,
log2(86) + 1 = 7.426.
The integer part of that is 7, so 7 digits are needed.
 With n digits, 2n unique numbers (from 0 to 2n-1) can be represented. If n=8, 256
(=28) numbers can be represented 0-255.
Hexadecimal, Octal, Bits, Bytes and Words.
It is often convenient to handle groups of bits, rather than individually. The most
common grouping is 8 bits, which forms a byte. A single byte can represent 256 (28)
numbers. Memory capacity is usually referred to in bytes. Two bytes is usually called a
word, or short word (though word-length depends on the application). A two-byte
word is also the size that is usually used to represent integers in programming
languages. A long word is usually twice as long as a word. A less common unit is the
nibble which is 4 bits, or half of a byte.
It is cumbersome for humans to deal with writing, reading and remembering

individual bits, because it takes many of them to represent even fairly small numbers.
A number of different ways have been developed to make the handling of binary data
easier for us. The most common is hexadecimal. In hexadecimal notation, 4 bits (a
nibble) are represented by a single digit. There is obviously a problem with this since 4
bits gives 16 possible combinations, and there are only 10 unique decimal digits, 0 to 9.
This is solved by using the first 6 letters (A..F) of the alphabet as numbers. The table
shows the relationship between decimal, hexadecimal and binary.
Decimal Hexadecimal Binary
0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
10 A 1010
11 B 1011
12 C 1100
13 D 1101
14 E 1110
15 F 1111

There are some significant advantages to using hexadecimal when dealing with
electronic representations of numbers (if people had 16 fingers, we wouldn't be
saddled with the awkward decimal system). Using hexadecimal makes it very easy to
convert back and forth from binary because each hexadecimal digit corresponds to
exactly 4 bits (log 2(16) = 4) and each byte is two hexadecimal digit. In contrast, a
decimal digit corresponds to log2(10) = 3.322 bits and a byte is 2.408 decimal digits.
Clearly hexadecimal is better suited to the task of representing binary numbers than is
decimal.
As an example, the number CA3 16 = 1100 1010 00112 (11002 = C16 , 10102 = A16, 00112 =
3 16). It is convenient to write the binary number with spaces after every fourth bit to
make it easier to read. Converting back and forth to decimal is more difficult, but can
be done in the same way as before.
323510 = C16*256 + A16*16 + 316*1 = C16 *162 + A16 *161 + 316 *160
or
323510 = 12*256 + 10*16 + 3*1 = 12*162 +10*161 +3*160
Octal notation is yet another compact method for writing binary numbers. There are 8
octal characters, 0...7. Obviously this can be represented by exactly 3 bits. Two octal
digits can represent numbers up to 64, and three octal digits up to 512. A byte requires
2.667 octal digits. Octal used to be quiete common, it was the primary way of doing
low level I/O on some old DEC computers. It is much less common today but is still
used occasionally (e.g., to set read, write and execute permissions on Unix systems)

In summary:
bit
a single binary digit, either zero or one.
byte
8 bits, can represent positive numbers from 0 to 255.
hexadecimal
A representation of 4 bits by a single digit 0..9,A..F. In this way a byte can be

represented by two hexadecimal digits
long word
A long word is usually twice as long as a word.
nibble
4 bits, half of a byte.
octal
A representation of 3 bits by a single digit 0..7. This is used much less commonly
than it once was (early DEC computers used octal for much of their I/O)
word
Usually 16 bits, or two bytes. But a word can be almost any size, depending on
the application being considered -- 32 and 64 bits are common sizes

Signed Binary Integers
It was noted previously that we will not be using a minus sign (-) to represent negative
numbers. We would like to represent our binary numbers with only two symbols, 0
and 1. There are a few ways to represent negative binary numbers. The simplest of
these methods is called ones complement, where the sign of a binary number is
changed by simply toggling each bit (0's become 1's and vice-versa). This has some
difficulties, among them the fact that zero can be represented in two different ways
(for an eight bit number these would be 0000 0000 and 1111 1111)., we will use a
method called two's complement notation which avoids the pitfalls of one's
complement, but which is a bit more complicated.
To represent an n bit signed binary number the leftmost bit, has a special significance.
The difference between a signed and an unsigned number is given in the table below
for an 8 bit number.
The value of bits in signed and unsigned binary numbers

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Unsigned 27 = 128 26 = 64 25 = 32 24= 16 23= 8 22 = 4 21 = 2 20 = 1
Signed -(27) = -128 26 = 64 25 = 32 24 = 16 23 = 8 22 = 4 21= 2 20 = 1
Let's look at how this changes the value of some binary numbers
Binary Unsigned Signed

0010 0011 35 35
1010 0011 163 -93
1111 1111 255 -1
1000 0000 128 -128

If Bit 7 is not set (as in the first example) the representation of signed and unsigned
numbers is the same. However, when Bit 7 is set, the number is always negative. For
this reason Bit 7 is sometimes called the sign bit. Signed numbers are added in the
same way as unsigned numbers, the only difference is in the way they are interpreted.
This is important for designers of arithmetic circuitry because it means that numbers
can be added by the same circuitry regardless of whether or not they are signed.
To form a two's complement number that is negative you simply take the
corresponding positive number, invert all the bits, and add 1. The example below
illustrated this by forming the number negative 35 as a two's complement integer:
3510 = 0010 00112

invert -> 1101 11002
add 1 -> 1101 11012
So 1101 1101 is our two's complement representation of -35. We can check this by
adding up the contributions from the individual bits
1101 11012 = -128 + 64 + 0 + 16 + 8 + 4 + 0 + 1 = -35.
The same procedure (invert and add 1) is used to convert the negative number to its
positive equivalent. If we want to know what what number is represented by 1111
1101, we apply the procedure again
? = 1111 11012
invert -> 0000 00102
add 1 -> 0000 00112
Since 0000 0011 represents the number 3, we know that 1111 1101 represents the
number -3.

Note that a number can be extended from 4 bits to 8 bits by simply repeating the
leftmost bit 4 times. Consider the following examples
4
Decimal 8 bit
bit
3 0011 0000 0011
-3 1101 1111 1101
7 0111 0000 0111
-5 1011 1111 1011
Let's carefully consider the last case which uses the number -5. As a 4 bit number this is
represented as
1011 = -8 + 2 + 1 = -5
The 8 bit number is
1111 1011 = -128 + 64 + 32 + 16 + 8 + 2 + 1 = -5.
It is clear that in the second case the sum of the contributions from the leftmost 5 bits (-
128 + 64 + 32 + 16 + 8 = -8) is the same as the contribution from the leftmost bit in the 4
bit representation (-8)
This process is refered to as sign-extension, and can be applied whenever a number is

to be represented by a larger number of bits. In the 320C50 Digital Signal Processor,
this typically occurs when moving a number from a 16 bit register to a 32 bit register.
Whether or not sign-extension is applied during such a move is determined by
the sign-extension mode bit. Note that to store a 32 bit number in 16 bits you can

simply truncate the upper 16 bits (as long as they are all the same as the left-most bit in
the resulting 16 bit number - i.e., the sign doesn't change).
Most processors even have two separate instructions for shifting numbers to the right
(which, you will recall, is equivalent to dividing the number in half). The first
instruction is something like LSR (Logical Shift Right) which simply shifts the bits to
the right and usually fills a zero in as the lefmost bit. The second instruction is
something like ASR (Arithmetic Shift Right), which shifts all of the bits to the right,
while keeping the leftmost bit unchanged. With ASR 1010 (-6) becomes 1101 (-3). Of
course, there is only one instruction for a left shift (since LSL is equivalent to ASL).
BINARY INTEGER ARITHMETIC
This document will introduce you to the methods for adding and multiplying binary
numbers. In each section, the topic is developed by first considering the binary
representation of unsigned numbers (which are the easiest to understand), followed by
signed numbers and finishing with fractions (the hardest to understand). For the most
part we will deal with
Addition

Adding unsigned numbers
Adding unsigned numbers in binary is quite easy. Recall that with 4 bit numbers we
can represent numbers from 0 to 15. Addition is done exactly like adding decimal
numbers, except that you have only two digits (0 and 1). The only number facts to
remember are that
0+0 = 0, with no carry,

1+1 = 0, and you carry a 1.
so to add the numbers 0610=01102 and 0710=01112 (answer=1310=11012) we can write out
the calculation (the results of any carry is shown along the top row, in italics).
Unsigned
Decimal
Binary
1
110 (carry)
(carry)
0110
06
+0111
+07
1101
13
The only difficulty adding unsigned numbers occurs when you add numbers that are
too large. Consider 13+5.
Unsigned
Decimal
Binary
0 (carry) 1101 (carry)

13 1101
+05 +0101
18 10010
The result is a 5 bit number. So the carry bit from adding the two most significant bits
represents a results that overflows (because the sum is too big to be represented with the
same number of bits as the two addends).
Adding signed numbers
Adding signed numbers is not significantly different from adding unsigned numbers.
Recall that signed 4 bit numbers (2's complement) can represent numbers between -8
and 7. To see how this addition works, consider three examples.
Decimal Signed Binary
1110 (carry)
-2 1110
+3 +0011
1 0001
011 (carry)
-5 1011
+3 +0011
-2 1110
1100 (carry)
-4 1100

-3 +1101
-7 1001
In this case the extra carry from the most significant bit has no meaning. With signed
numbers there are two ways to get an overflow -- if the result is greater than 7, or less
than -8. Let's consider these occurrences now.
110 (carry)
6 0110
+3 +0011
9 1001
1001 (carry)
-7 1001
-3 +1101
-10 0110
Obviously both of these results are incorrect, but in this case overflow is harder to
detect. But you can see that if two numbers with the same sign (either positive or
negative) are added and the result has the opposite sign, an overflow has occurred.
Typically DSP's, including the 320C5x, can deal somewhat with this problem by using
something called saturation arithmetic, in which results that result in overflow are
replaced by either the most positive number (in this case 7) if the overflow is in the
positive direction, or by the most negative number (-8) for overflows in the negative
direction.

Adding fractions
There is no further difficult in adding two signed fractions, only the interpretation of
the results differs. For instance consider addition of two Q3 numbers shown (compare
to the example with two 4 bit signed numbers, above).
Fractional
Decimal
Binary
1110 (carry)
-0.25 1110
+0.375 +0011
0.125 0001
Fractional
Decimal
Binary
011 (carry)
-0.625 1011
+0.375 +0011
-0.25 1110
Fractional
Decimal
Binary
1100 (carry)
-0.5 1100
-0.375 +1101
-0.875 1001
If you look carefully at these examples, you'll see that the binary representation and
calculations are the same as before, only the decimal representation has changed. This

is very useful because it means we can use the same circuitry for addition, regardless
of the interpretation of the results.
Even the generation of overflows resulting in error conditions remains unchanged

(again compare with above)
Fractional
Decimal
Binary
110 (carry)
0.75 0110
+0.375 +0011
1.125 1001
Fractional
Decimal
Binary
1001 (carry)
-0.875 1001
-0.375 +1101
-1.25 0110
Multiplication
Multiplying unsigned numbers
Multiplying unsigned numbers in binary is quite easy. Recall that with 4 bit numbers
we can represent numbers from 0 to 15. Multiplication can be performed done exactly
as with decimal numbers, except that you have only two digits (0 and 1). The only
number facts to remember are that 0*1=0, and 1*1=1 (this is the same as a logical "and").

Multiplication is different than addition in that multiplication of an n bit number by an
m bit number results in an n+m bit number. Let's take a look at an example where
n=m=4 and the result is 8 bits
Decimal Binary
1010
x0110
0000
10
1010
x6
1010
60
+0000
0111100
In this case the result was 7 bit, which can be extended to 8 bits by adding a 0 at the
left. When multiplying larger numbers, the result will be 8 bits, with the leftmost set to
1, as shown.
Decimal Binary
1101
x1110
0000
13
1101
x14
1101
182
+1101
10110110

As long as there are n+m bits for the result, there is no chance of overflow. For 2 four
bit multiplicands, the largest possible product is 15*15=225, which can be represented
in 8 bits.
Multiplying signed numbers
There are many methods to multiply 2's complement numbers. The easiest is to simply
find the magnitude of the two multiplicands, multiply these together, and then use the
original sign bits to determine the sign of the result. If the multiplicands had the same
sign, the result must be positive, if the they had different signs, the result is negative.
Multiplication by zero is a special case (the result is always zero, with no sign bit).
Multiplying fractions
As you might expect, the multiplication of fractions can be done in the same way as the
multiplication of signed numbers. The magnitudes of the two multiplicands are
multiplied, and the sign of the result is determined by the signs of the two
multiplicands.
There are a couple of complications involved in using fractions. Although it is almost

impossible to get an overflow (since the multiplicands and results usually have
magnitude less than one), it is possible to get an overflow by multiplying -1x-1 since
the result of this is +1, which cannot be represented by fixed point numbers.
The other difficulty is that multiplying two Q3 numbers, obviously results in a Q6

number, but we have 8 bits in our result (since we are multiplying two 4 bit numbers).
This means that we end up with two bits to the left of the decimal point. These are sign
extended, so that for positive numbers they are both zero, and for negative numbers
they are both one. Consider the case of multiplying -1/2 by -1/2 (using the method from
the textbook):

Fractional
Decimal
Binary
1100
x0100
0000
-0.5
0000
x0.5
+111100
-0.25
11110000
This obviously presents a difficulty if we wanted to store the number in a Q3 result,

because if we took just the 4 leftmost bits, we would end up with two sign bits. So
what we'd like to do is shift the number to the left by one and then take the 4 leftmost
bit. This leaves us with 1110 which is equal to -1/4, as expected.
On a 16 bit DSP two Q15 numbers are multiplied to get a Q30 number with two sign
bits. On the 320C50 there are two ways to accomplish this. The first is to use the p-
scaler immediately after the multiplier, or the postscaler after the accumulator. to shift
the result to the left by one
BINARY FLOATING-POINT REPRESENTATION
The two most common floating-point binary storage formats used by Intel processors
were created for Intel and later standardized by the IEEE organization:

1 bit for the sign, 8 bits for the exponent, and 23 bits for
IEEE Short Real: 32 bits
the mantissa. Also called single precision.
1 bit for the sign, 11 bits for the exponent, and 52 bits for
IEEE Long Real: 64 bits
the mantissa. Also called double precision.
Both formats use essentially the same method for storing floating-point binary
numbers, so we will use the Short Real as an example in this tutorial. The bits in an
IEEE Short Real are arranged as follows, with the most significant bit (MSB) on the left:
Fig.
1
The Sign
The sign of a binary floating-point number is represented by a single bit. A 1 bit

indicates a negative number, and a 0 bit indicates a positive number.
The Mantissa
It is useful to consider the way decimal floating-point numbers represent their

mantissa. Using -3.154 x 105 as an example, the sign is negative, the mantissa is 3.154,
and the exponent is 5. The fractional portion of the mantissa is the sum of each digit
multiplied by a power of 10:
.154 = 1/10 + 5/100 + 4/1000

A binary floating-point number is similar. For example, in the number +11.1011 x
23, the sign is positive, the mantissa is 11.1011, and the exponent is 3. The fractional
portion of the mantissa is the sum of successive powers of 2. In our example, it is
expressed as:
.1011 = 1/2 + 0/4 + 1/8 + 1/16
Or, you can calculate this value as 1011 divided by 24. In decimal terms, this is eleven
divided by sixteen, or 0.6875. Combined with the left-hand side of 11.1011, the decimal
value of the number is 3.6875. Here are additional examples:
Binary Floating-Point Base 10 Fraction Base 10 Decimal

11.11 3 3/4 3.75
0.00000000000000000000001 1/8388608 0.00000011920928955078125
The last entry in this table shows the smallest fraction that can be stored in a 23-bit
mantissa. The following table shows a few simple examples of binary floating-point
numbers alongside their equivalent decimal fractions and decimal values:
Decimal Decimal
Binary
Fraction Value
.1 1/2 .5
.01 1/4 .25
.001 1/8 .125
.0001 1/16 .0625
.00001 1/32 .03125
The Exponent

IEEE Short Real exponents are stored as 8-bit unsigned integers with a bias of 127. Let's
use the number 1.101 x 25 as an example. The exponent (5) is added to 127 and the sum
(162) is stored in binary as 10100010. Here are some examples of exponents, first shown
as decimal values, then as biased decimal, and finally as 8-bit unsigned binary:
Adjusted
Exponent (E) Binary Representation
(E + 127)
5 +162 10100010
0 +127 01111111
-10 +117 01110101
128 +255 11111111
-1 +126 01111110
Notice that the binary exponent is unsigned, so it cannot be negative. That is why the
bias of 127 is used. The largest possible exponent is 128, because when added to 127,
produces 255, the largest unsigned value represented by 8 bits. If the approximage
range is from 1.0 x 2-127 to 1.0 x 2128. Expressed with decimal exponents, this is
Normalizing the Mantissa
Before a floating-point binary number can be stored correctly, its mantissa must be
normalized. The process is basically the same as when normalizing a floating-point
decimal number. For example, decimal 1234.567 is normalized as 1.234567 x 103 by
moving the decimal point so that only one digit appears before the decimal. The
exponent expresses the number of positions the decimal point was moved left (positive
exponent) or moved right (negative exponent).

Similarly, the floating-point binary value 1101.101 is normalized as 1.101101 x 23 by

moving the decimal point 3 positions to the left, and multiplying by 23. Here are some
examples of normalizations:
Binary Value Normalized As Exponent

1101.101 1.101101 3
.00101 1.01 -3
1.0001 1.0001 0
10000011.0 1.0000011 7
You may have noticed that in a normalized mantissa, the digit 1 always appears to the
left of the decimal point. In fact, the leading 1 is omitted from the mantissa's actual
storage because it is redundant.
Putting it All Together
We have now reached the point where we can combine the sign, exponent, and
normalized mantissa into the binary IEEE short real representation. Using Figure 1 as a
reference, the value 1.101 x 20 would be stored as sign = 0 (positive), mantissa = 101,
and exponent = 01111111 (the exponent value is added to 127). The leading "1." was
dropped from the mantissa. Here are more examples:

Binary Value Biased Exponent Sign, Exponent, Mantissa

-1.11 127 1 01111111 11000000000000000000000
+1101.101 130 0 10000010 10110100000000000000000
-.00101 124 1 01111100 01000000000000000000000
+100111.0 132 0 10000100 00111000000000000000000
+.0000001101011 120 0 01111000 10101100000000000000000

REFERENCES:
https://en.wikipedia.org/wiki/Arithmetic_logic_unit
https://www.webopedia.com/TERM/A/ALU.html
https://www.lindo.com/doc/online_help/lingo15_0/binary_integer_variables.htm
https://en.wikipedia.org/wiki/Binary_integer_decimal
https://www.swarthmore.edu/NatSci/echeeve1/Ref/BinaryMath/NumSys.html#posint
https://www.swarthmore.edu/NatSci/echeeve1/Ref/BinaryMath/BinaryMath.html
http://cstl-
csm.semo.edu/xzhang/Class%20Folder/CS280/Workbook_HTML/FLOATING_tut.htm

WEEK 13:: Objectives

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

WEEK 13:: Objectives

Uploaded by

Copyright:

Available Formats

WEEK 13: Arithmetic Logic Unit, Binary Integer Representation, Binary Integer

Arithmetic, Binary Floating-Point Representation

ARITHMETIC LOGIC UNIT (ALU)

An arithmetic logic unit (ALU) is a combinational digital electronic circuit that

1|Page COMPUTER ORGANIZATION AND ARCHITECTURE

 Negative, which indicates the result of an arithmetic operation is negative.

3|Page COMPUTER ORGANIZATION AND ARCHITECTURE

4|Page COMPUTER ORGANIZATION AND ARCHITECTURE

Bitwise logical operations

5|Page COMPUTER ORGANIZATION AND ARCHITECTURE

 OR: the bitwise OR of A and B appears at Y.

Type Left Right

Rotate through carry

6|Page COMPUTER ORGANIZATION AND ARCHITECTURE

7|Page COMPUTER ORGANIZATION AND ARCHITECTURE

An ALU is usually implemented either as a stand-alone integrated circuit (IC), such as

BINARY INTEGER REPRESENTATION

A binary integer variable—also called a 0/1 variable—is a special case of an integer

10 | P a g e COMPUTER ORGANIZATION AND ARCHITECTURE

BINARY INTEGER DECIMAL

11 | P a g e COMPUTER ORGANIZATION AND ARCHITECTURE

s 00eeeeee (0)mmm mmmmmmmmmm mmmmmmmmmm

s 1100eeeeee (100)m mmmmmmmmmm mmmmmmmmmm

Binary Representation of positive integers

8610 = 1*64 + 0*32 + 1*16 + 0*8 + 1*4 + 1*2 + 0*1

13 | P a g e COMPUTER ORGANIZATION AND ARCHITECTURE

Hexadecimal, Octal, Bits, Bytes and Words.

It is cumbersome for humans to deal with writing, reading and remembering

15 | P a g e COMPUTER ORGANIZATION AND ARCHITECTURE

16 | P a g e COMPUTER ORGANIZATION AND ARCHITECTURE

a single binary digit, either zero or one.

8 bits, can represent positive numbers from 0 to 255.

A representation of 4 bits by a single digit 0..9,A..F. In this way a byte can be

A long word is usually twice as long as a word.

4 bits, half of a byte.

17 | P a g e COMPUTER ORGANIZATION AND ARCHITECTURE

The value of bits in signed and unsigned binary numbers

Binary Unsigned Signed

18 | P a g e COMPUTER ORGANIZATION AND ARCHITECTURE

3510 = 0010 00112

1101 11012 = -128 + 64 + 0 + 16 + 8 + 4 + 0 + 1 = -35.

19 | P a g e COMPUTER ORGANIZATION AND ARCHITECTURE

3 0011 0000 0011

-3 1101 1111 1101

7 0111 0000 0111

-5 1011 1111 1011

The 8 bit number is

1111 1011 = -128 + 64 + 32 + 16 + 8 + 2 + 1 = -5.

This process is refered to as sign-extension, and can be applied whenever a number is

20 | P a g e COMPUTER ORGANIZATION AND ARCHITECTURE

BINARY INTEGER ARITHMETIC

21 | P a g e COMPUTER ORGANIZATION AND ARCHITECTURE

0+0 = 0, with no carry,

0 (carry) 1101 (carry)

22 | P a g e COMPUTER ORGANIZATION AND ARCHITECTURE

Adding signed numbers

Decimal Signed Binary

Decimal Signed Binary

Decimal Signed Binary

23 | P a g e COMPUTER ORGANIZATION AND ARCHITECTURE

Decimal Signed Binary

Decimal Signed Binary

24 | P a g e COMPUTER ORGANIZATION AND ARCHITECTURE

8610 = 164 + 032 + 116 + 08 + 14 + 12 + 0*1