LAB 3

Comparator Design and Simulations

Name: Mudassir Ali
Roll No.: 21i-2425
Section: IC Design
Date: Feb 28,2022
Subject: Mixed Signal IC Design
Submitted to: Google Classroom
 Lab Tasks
1. Single Stage OPAMP Based Comparator

Figure 1: Schematic of OPAMP based comparator

Figure 2: Testbench for OPAMP based comparator

 Figure 3: Output waveforms for OPAMP based comparator

The output waveform is shown in slod red color. In the reset state the output is zero while in evaluation state when
the input exceeds the 0 volts the outputs get high, and the output gets zero when the input is below 0 volts. The
other 3 waveform shows the different phases. These phases are used for reset, evaluation phase and these phases
are also used to compensates offset.

2. Multistage Op-Amp Comparator

Figure 4: Schematic of multistage op-amp based comparator

 Figure 5: Test bench for multistage op-amp based comparator

Figure 6: Output waveforms of multi-stage op-amp based comparator

The multistage op-amp based comparator has the same functionality, but multiple stages are used to increase the
speed while achieving the same gain. The multi-stage has the benefit that it also compensates for the input offset as
well as it cancels out the charge injection issue to a large extent.
 3. Latch Based Comparator:

Figure 7: Schematic for latch-based comparator

A generalized latch-based comparator has 2 stages. The first stage is pre- amplifier and the 2 nd stage is track and
latch. The track and latch stage amplify the signal to full swing by using positive feedback.
 Figure 8: Testbench for latch-based comparator

Figure 9: output of latched based comparator

The above waveform shows that the output gets high when the input is greater than 0 during the positive clock
cycle. This kind of latched based comparator is used in place of op-amp based comparator due to a number of
reasons I.e. provides high resolution, minimizes number of gain stages due to positive feedback and it is faster than
op-amp based comparators.
4. Inverter based Comparator:

Figure 10: Schematic of inverter-based comparator

Figure 11: Testbench for inverter based comparator

 Figure 12: Output waveforms of inverter-based comparator

Inverter based comparators are also used as comparators depending upon the application. The pros of inverter-
based comparator include less silicon area and less power consumption. On the order hand this architecture has
some cons as well like low gain, Accurate sample and hold circuit is required and dynamic power losses during reset
phase.
 Assignment.
1. Simulate the latch comparator using PMOS tail.

Figure 13: Schematic for Assignment 1

The above schematic is same as the latch-based comparator but only the PMOS tail is used instead of NMOS tail.
Figure 14: Testbench for Assignment # 1
 Figure 15: Output waveform of the Assign 1

In this assignment a latch-based comparator is implemented using PMOS tail. The sizes of the transistors were
changes accordingly to achieve the desired results.
2. Design a slope detector circuit using inverter -based comparator, that offers 10mv
resolution at a clock frequency of 25 KHz.

Figure 16: Schematic for the Assignment # 2

Figure 17: Testbench for the assignment # 2

 Figure 18: output waveforms of the assignment # 2

In this assignment a slope detector is designed for 25 KHz clock frequency. It is basically a replica of inverter-based
comparator, but the Reference voltage is removed in this case. In reset state the input and outputs of 1 st inverter are
shorted, and the input and output is set the V M . Which means that the 2 nd leg of cap is set to V M . Now when in
evaluation stage an input higher than VM is applied the 2 nd leg of Cap is set to a high voltage and it changes the
output to a low voltage and the 2 nd inverter sets it output to high. Then the latch is activated to latch the output.
When in evaluation stage a lower voltage then V M is applied at input it performs vice versa. In this way the circuit
detects the slop and change the output accordingly.

Conclusion: This lab started with the designing of om-amp based comparator. Then a multistage op-
amp based comparator was designed. Later latch based and inverter-based comparators were also
designed. In the assignment part an inverter-based comparator with PMOS tail was designed. A slope
detector was also designed in the assignment part of the lab.