LAB 5

Switch Capacitors Circuits Design and

Simulations
Name: Mudassir Ali
Roll No.: 21i-2425
Section: IC Design
Date: March 25,2022
Subject: Mixed Signal IC Design
Submitted to: Google Classroom
 Lab Tasks
1. Switch Capacitor Resistor

Figure 1: Schematic of the Switch Capacitor Resistor

Figure 2:Testbench for the Switch Capacitor Resistor

 Figure 3: Results of the Switch Capacitor Resistor

The above waveform shows the results of switch capacitor resistor. The current drawn by the switch capacitor
resistor is shown in dotted red and blue during each phase of the clock. The above waveforms shows that the
resistor is drawing a current of 204.6 uA during phase 1 and -202 uA during phase 2

Figure 4: Average current drawn by the switch capacitor resistor

The above figure shows that the average current drawn by the resistor is 101.2 nA. From this result we can calculate
the value of the resistor and compare it with the calculated resistance.

V 2−V 1 3−1
Rmeasured = = =19.8 M Ω
I avg 101 nA
 T 20 u
Rcalculated = = =20 M Ω
C1 1 p
The above calculation shows that the measured and calculated switch capacitance resistances are almost same.

2. Switch Capacitor Integrator

Figure 5: Schematic of switch Capacitor Integrator

Figure 6: Testbench for switch Capacitor Integrator

 Figure 7: Results of switch Capacitor Integrator

The above waveform shows the results of switch capacitor integrator. During the positive Ph1 the input is sampled
on the capacitor which is shown as Io/12/mid waveform. Then during the positive Ph2, the mid signal is subtracted
from the previous output. In this way the circuit perform as Switch capacitor Integrator.

3. Parasitic Sensitive Switch Capacitor Integrator

Figure 8: Schematic for Parasitic Sensitive Switch Capacitor Integrator

 Figure 9: Testbench for Parasitic Sensitive Switch Capacitor Integrator

Figure 10: Results of the parasitic sensitive Intergator

In the parasitic sensitive integrator circuits 4 parasitic capacitances are added to observe the effect of parasitic on
the Integrator. It can be observed that the output waveform is slightly different from the previous one which is due
to the addition of the parasitic capacitors.
4. Parasitic Insensitive switch Capacitor Integrator

Figure 11: Schematic of Parasitic Insensitive switch Capacitor Integrator

Figure 12: Testbench for Parasitic Insensitive switch Capacitor Integrator

 Figure 13: Results of the Parasitic Insensitive switch Capacitor Integrator

From the above waveforms it can be deduced that the parasitic insensitive Integrator is basically a non-inverting
integrator.
 Assignments:
1. Simulate the non-inverting Parasitic Insensitive switch Capacitor Integrator by
adding Parasitic and verify the results.

Figure 14: Schematic for Parasitic Insensitive switch Capacitor Integrator with parasitic added

In the above schematic it can be observed that 4 parasitic capacitances are added.

Figure 15: Testbench for Parasitic Insensitive switch Capacitor Integrator with parasitic added
 Figure 16: Results of Parasitic Insensitive switch Capacitor Integrator with parasitic added

The above results are exactly same as the previous lab task in which a parasitic insensitive SC Integrator was
designed but the parasitic capacitances were not included. The results verify that this SC integrator is insensitive to
parasitic.
2. Simulate the inverting delay free Parasitic Insensitive switch Capacitor Integrator
by adding Parasitic and verify the results.
a. Without parasitic
b. With Parasitic
a. Without parasitic

Figure 17: Schematic of delay free Parasitic Insensitive switch Capacitor Integrator without parasitic

Figure 18: Testbench for delay free Parasitic Insensitive switch Capacitor Integrator without parasitic
 Figure 19: Results of delay free Parasitic Insensitive switch Capacitor Integrator without parasitic

b. With Parasitic

Figure 20: schematic of delay free Parasitic Insensitive switch Capacitor Integrator with parasitic
 Figure 21: Testbench for delay free Parasitic Insensitive switch Capacitor Integrator with parasitic

Figure 22: Results of delay free Parasitic Insensitive switch Capacitor Integrator with parasitic

The results shown in Figure 19 and Figure 22 are same. Which verifies that the inverting Delay free integrator is
insensitive to parasitic.
Conclusion: In this lab we designed and switch capacitor resistor multiple types of SC integrator circuits. We
started with parasitic sensitive SC integrator then we designed non-inverting parasitic insensitive SC integrator, and,
in the Assignment # 1, we verified that the non-inverting parasitic insensitive SC integrator is insensitive to parasitic.
In Assignment # 2 a delay free parasitic insensitive integrator is designed which is also verified that it is actually
insensitive to parasitic by adding parasitic into it.