High performance current mirror

Ernesto Juárez Campos

Facultad de Ciencias de la Electrónica, BUAP

Puebla, México
ernesto.juarezc@alumno.buap.mx

Abstract – In this report, we will design and build a current In this case it is about the design and construction
mirror, which has a reference current 𝑰𝑹𝑬𝑭 = 𝟏𝟎𝟎𝝁𝑨 and of a current mirror, for this we must use calculations for the
a dynamic of 0.3V to 1.8V. design of the MOS transistors. In the first place are the
parameters of the dimensions of these.
I. INTRODUCTION
The use of a current mirror has become a basic
component of analog circuit designs and generally more
than one current mirror is present within a circuit. In its basic
form, a current mirror circuit acts as a form of current
regulator that is capable of balancing output current values
regardless of input load or resistance levels in a specified
range of operation for the circuit.

In this report, a high-performance current mirror

will be designed and built, which will have as parameters a Figure 2. MOS transistors parameters.
reference current 𝐼𝑅𝐸𝐹 = 100𝜇𝐴 and a dynamic of 0.3V to
1.8V. later we will create the circuit symbol to add it to a
new schematic focused on simulating it. Likewise, we will First, we have the length of the channel 𝐿. In analog
create the geometric pattern and verify that both the Layout circuits, all transistors must have at least twice the minimum
and the schematic circuit match. length, this is because we seek to minimize the impact of
uncertainty in manufacturing. thus, the designated value will
II. DEVELOPMENT be 𝐿 = 360𝑛𝑚.
With the help of the software Virtuoso, we will Using the following equation, we will find the
make the schematic circuit of the current mirror, as shown value of the finger width (𝑊)
below.
1 𝑊
𝐼𝑅𝐸𝐹 = 𝐾𝑛 ( ) (𝑉𝐺𝑆 − 𝑉𝑇𝐻 )2 (1)
2 𝐿

Using the following parameters

• 𝐼𝑅𝐸𝐹 = 100𝜇𝐴
𝜇𝐴⁄
• 𝐾𝑛 = 260 𝑉2
• 𝐿 = 360𝑛𝑚
• 𝑉𝑇𝐻 = 0.5𝑉

As we require the circuit dynamics to start at 0.3V,

the difference 𝑉𝐺𝑆 − 𝑉𝑇𝐻 must be equal to 0.3𝑉, so 𝑉𝐺𝑆 =
0.8𝑉. Solving the equation for 𝑊, we have that the value is
equal to 𝑊 = 3.077𝜇𝑚. We can use this value, but for
manufacturing issues, it is necessary that the length be
Figure 1. High performance current mirror schematic circuit.
multiples of the minimum length (180𝑛𝑚), therefore we
will use the value 𝑊 = 3.06𝜇𝑚.

Now, we will create a symbol for the previously

elaborated circuit, this to add it more easily to a new
schematic to carry out the pertinent simulations.

We put the IREF and MO pins at the top, the VB

pin at the left, and the VSSA pin at the bottom.

Figure 5. Parameters of the simulation.

III. RESULTS

Figure 3. Symbol of the current mirror circuit.

Once this is done, we create a new cellview to

perform the simulation, we instantiate the previously created
symbol, and the sources required for the simulation, as
shown in the following figure.

Figure 6. Simulation results.

In the figure 6, we can see that the dynamics of the

current mirror starts at 0.3V, as required in the
specifications, in addition to being practically 100𝜇𝐴 up to
1.8V. To create the layout, we will go to the original circuit
to create the geometric pattern.

Figure 4. Circuit used for the test bench.

Now, we will carry out a simulation in DC to

observe the behavior of the current and verify that it meets
the requested specifications, for this we will use the tool
ADE L. We will sweep the voltage 𝑉𝑋 , and we will use the
values shown in figure 5. The outputs to be plotted will be
𝐼𝑅𝐸𝐹 and 𝑀𝑂 .

Figure 7. Geometric Pattern.

 V. REFERENCES
[1] V. R. Gonzales Díaz. Clase Diseño Circuitos Analógicos
Integrados. Microsoft Teams. September 13th , 2021. MP4.

[2] B. Razavi. (2008). Fundamentals of microelectronics (1st

ed.). Wiley.

Figure 8. Connections and labels.

Now, we will check that the layout matches the schematic

circuit.

Figure 9. Calibre LVS report file.

As we can see in the figure 9, the layout matches the

schematic, so we can conclude that the geometric pattern is
correct.

IV. CONCLUSIONS
In this report we were able to apply the knowledge
acquired previously, both for the realization of the schematic
circuit, and for the simulation, as well as for the realization
of the layout. in the same way, calculations were used for
the design of the MOS transistors, something that is essential
in the manufacture of analog circuits.