LDO Project

Francisco Valentino Palencia Solano-2174669

School of Electrical, Electronic and Telecommunications Engineering. Microelectronics
Industrial University of Santander UIS, Bucaramanga, Colombia
Email: francisco2174669@correo.uis.edu.co

I. I NTRODUCTION objectives the order of development was initially classified by

This project has as its main purpose to design an LDO.
that as an application to achieve a clean and stable energy
source by feeding microcontrollers of this application, factors
such as the selection of the regulation topology, the choice of
suitable components and the optimization of circuit parameters
must be taken into account. Simulations in design tools such
as Cadence Virtuoso can be useful in determining optimal
circuit operating points and improving LDO efficiency and
stability. When designing and optimizing the LDO for this
specific application, we seek to meet the voltage, current, and
efficiency requirements necessary for proper operation of the
microcontroller.
II. T HEORETICAL FRAMEWORK
Arefin, S., Islam, M. S. (2017). Design of Low Drop-
Out Regulator with MOSFET for Portable Applications. In
2017 International Conference on Electrical, Computer and
Communication Engineering (ECCE) (pp. 137-140). IEEE.
Abstract: Article presents a low voltage drop (LDO) regulator
design for portable applications using MOSFETs. The LDO
circuit is described and the design and simulation processes are
detailed. Test results show that the proposed design achieves
high energy efficiency and excellent voltage stability. This
LDO design is suitable for low-power and portable applica-
tions where a reliable and efficient power supply is required.
Kumar, R., Chaudhary, R. K. (2016). Design and simu-
lation of LDO regulator with MOSFET pass device. 2016
International Conference on Wireless Communications, Sig-
nal Processing and Networking (WiSPNET) (pp. 1982-1987).
IEEE. Abstract: Article presents the design and simulation of
a low voltage drop (LDO) regulator with a MOSFET pass-
through device. The components and circuit of the LDO, as
well as the design and simulation processes, are described.
The results show that the proposed design provides high
energy efficiency and good voltage stability over a wide range
of loads. This LDO design is suitable for low-power and
portable applications such as mobile devices and wireless
sensor systems.
III. M ETHODOLOGY
Procedure For the development of the LDO it was necessary
to start from the characterization of each of the transistors
taking into account that it is necessary to know from the
dimensions of the transistor to its points of operation for
optimal operation, taking into account the framework of the
characterizing the step transistor which is one of the most
important since this is the one that will guarantee That my
output is ideal according to what is established in the design,
on the other hand we pass to calculate the dimensions of the
current mirror based on known parameters such as voltage, it
is also important to note that the process made for the current
mirror will be reflected in the other four transistors since they
will have the same qualities. Finally, it remains to characterize
the ota from an input voltage defined by the step transistor.
Step-through transistor characterization: During the calcu-
lation of the parameters it was of vital importance to start
from the values established by the objectives of the project
where initially we have the approximate value of the output
current. The input voltage to the Pmos transistor pump and
the LDO voltage that directly establishes the voltage between
drain and dispenser, now starting from there we make in our
preset circuit the characterization of VGS, VDS and opcharac
which is the direct characterization between for a linear input
t. Taking into account figure ?? , we can directly establish the
Fig. 1. lp
relationship we want to establish with respect to the parameter
wn since we can make the graph of the current to see its
behavior according to the preset values. For the proper use of
the characteristic graph of the current we must bear in mind
that the graph is with respect to the value that we do not know
that this case is Vsg, at this point it is important to clarify the
logic of the graph, since we are operating a PMOS transistor
the is throwing us the VGS relationship and we have to keep
in mind the change of signs when returning the VSG voltage.
 Fig. 2. parame

Next to this point we look at the relationship between the

values thrown that this case was 853,117m and 930,111m.

Fig. 4. parame

this time we used the same starting parameters except for lp

that in this case was 355n to comply with the correct operation
of the step transistor.

Fig. 3. parame

In figure 4, we can see reflected the values we need to

confirm the point of operation of the transistor taking into
account that we must compare according to the equations in
such a way that this transistor is always in saturation and for
this we first verify and likewise we force that the transistor is
always on and on the other hand its saturation voltage equation
V gs ą vthp (1) Fig. 5. parame

V ds ą vdsat (2)
and likewise the generic saturation equation
V DS ą“ V GS–V T (3)
Finally when evaluating the overdrive voltage equations we
can say that the value that was chosen due to the pre-
established requirements was 839,694m, you will wonder why
it is value if you had previously given us another. Clearly
for this procedure it is necessary to maintain a range so that
the requirements are met but when testing with the value
853.717m our transistor did not meet the requirements so it
was necessary to start from a different lp to the previous one
All these calculations were necessary to establish the dimen-
sions of our step transistor, where finally the value we decided
to choose was that of the green graph that is approximately
600.35u for wp as you can see in figure 5, and the lp value is
the one established from the beginning, that is, 355n so we can
directly establish the polarization point of the step transistor.
For the current mirror:
Initially to calculate the parameters of this transistor it
is necessary to have some input parameters that directly
characterize the function of this current mirror, it is important
to mention that we know the drain and pump voltage since it is
a current follower therefore we know the parameters in terms
of voltage. Now it is important to analyze the dimensions of

Fig. 6. parame

this transistor since being a current mirror the other transistors

replicate their information in the Mtail, Mnbc, Mnb1 and
Mnb2 transistors but their dimensions can change as can be
seen in figure 6. What was initially done was to characterize
the transistor current to see your point of operation, where
we already know parameters such as Lp, Ln, Vgs and Vds.
From there we make a sweep in our simulation OpCharact to
characterize the parameters of the same, where we will finally
find the value of wn starting from a range of values of Ln
since in this case we face an NMOS transistor. Fig. 8. parame

Fig. 9. parame

that the most appropriate Wn dimension is the one belonging

Fig. 7. parame to the yellow color that has a dimension of 300.35u as can be
seen in the figure 10.
Then we go to the calculator and graph with respect to our
operating points that in this case are the opCharact that is
mainly responsible for making a neighborhood before a linear
input, while on the other hand we make a simulation in this
case vs Vds or Vgs since the transistor is in diode connection
and its source is grounded therefore
vgs “ vds (4)
and this transistor will always be saturated.
Finally, for our current mirror, as we can see in the figure 9 Fig. 10. parame
we make the characterization with respect to the current taking
into account its dimensions and that it meets the requirements Taking into account the above mentioned In this current
for the transistor to remain in saturation. On the other hand mirror, the input current (Ibias) is applied to the transistor Q1,
before the values thrown by our cadence tool we can show which establishes a mirror current through the transistors Q2,
Q3, Q4 and Q5. Transistors Q2, Q3, Q4, and Q5 have the
same geometry and are paired to have the same bias current.
Because the mirror current is divided equally between the
paired transistors, the current through Q2, Q3, Q4, and Q5 is
equal. The mirror current generated by the current mirror can
be used in an LDO to generate a constant reference current that
is compared with the load current and used to control voltage
regulation. By ensuring that the reference current is constant
and accurate, a more stable and reliable voltage regulation can
be achieved.
For the ota: Starting from the premise that we know the
dimensions and polarization of the step transistor we can know
the voltage Vsg and likewise the voltage of the gate which in
turn is the voltage of the output node of the ota as can be seen
in the figure 11, therefore, we can characterize the transistor
and likewise from there the rest.
Fig. 11. parame
Taking into account the calculations made above the Voltage
at the gate is 1.36 the voltage at the transistor drain p of the ota
is 1.36. As we can see in the figures in the characterization
Fig. 12. parame
of this transistor we find things very similar to the previous
polarization points because we know certain parameters and
it becomes a bit mechanical part of the procedure, it is very
important to round that in the differential pair the currents
Fig. 13. parame
of the mirrors are known and by entity the polarization point
taking into account that vref It is equal to 0.9 and we can also
arrive at an equation that satisfies the saturation requirements
of these transistors.
Following the previous step it was necessary to create the
schematics according to each part of the LDO, initially after
knowing the dimensions of all the transistors we start from
what we now call amplifier and inside the amplifier our great
friend the differential torque as can be seen in the figure 14.
After this you must continue to create the symbol of each part
of the circuit to optimize the use of the LDO, therefore, the
next step to follow is to create the step circuit that contains the
differential torque as an amplifier as you can see in the figure
15 and finally having all the configurations of the circuit we
proceed to characterize the LDO taking into account that it
must have a tb, which verifies its correct operation and shows
that if the established parameters were met as can be seen in
the figure 16.
Fig. 14. complete ota
Finally, to meet all the necessary requirements for the first
part of the development of the LDO it is necessary to calculate
the performance before an input of the LDO in order to
see sunfionalidad, starting from there the second phase is to
implement the Layaout of the LDO.
IV. C ONCLUSION
In conclusion, designing an LDO from scratch involves
calculating different parameter dimensions, such as the width
and length of the transistors, to achieve an optimal circuit
that meets the requirements of the application. In this project,
transistor width and length values were calculated in order
to achieve maximum load and adequate transient response,
 Fig. 15. OTA

Fig. 16. OTA

and it was found that the NMOS transistor width (wn) must
be greater than the PMOS transistor width (wp) to improve
circuit performance. In addition, the value of the dimension
parameters for the load resistors and for the compensation
capacitor was calculated so that adequate LDO stability was
achieved. The value of the compensation capacitor was sought
to be calculated to ensure an adequate closed-loop response
in the circuit. In summary, the calculation of dimension
parameters is essential for the design of an LDO that meets
application requirements such as maximum load, transient
response, stability and closed-loop response. Therefore, it is
important to take these parameters into account during the
design process to achieve a functional and reliable circuit.