Hands-On Workshop: Software-Defined Radio: ©2018 Analog Devices, Inc. All Rights Reserved

Hands-on Workshop:
Software-Defined Radio
ANALOG DEVICES
ROBIN GETZ
TRAVIS COLLINS
MATHWORKS
CURIE CHUNG
NOAM LEVINE
RICHARDSON RFPD
MARK VITELLARO
VINCE WRIGHT
©2018 Analog Devices, Inc. All rights reserved. 1

Welcome
Time Presenter Topic
8:00 – 8:30 Richardson • Check In / Coffee
• Pick up hardware and Textbook
8:30 – 9:00 Analog Devices • Debug Software Installation Issues
MathWorks • Check Connectivity to hardware
9:00 – 9:10 Richardson Introductions
9:10 – 9:45 Analog Devices • ADI Prototyping Ecosystem (RadioVerse)
• AD9361 (chip)
• Pluto SDR (system)
• Instructor lead demo of dump1090
9:45 – 10:00 MathWorks Model Based Design
10:00 – 10:45 Analog Devices IIO infrastructure and Software Tools
• capture and control radio with IIO command line tools, and the
IIO Oscilloscope
• Hands on labs
10:45 – 11:15 MathWorks MATLAB and Simulink and system objects
• Hands on labs
11:15 – 11:30 Analog Devices Data Flow and Transfers
11:30 – 12:30 Analog Devices Basic communications theory
• Hands on labs
12:00 Lunch
12:30 – 12:45 MathWorks Advanced Workflows
12:45 – 1:00 Analog Devices Moving to Custom Hardware
1:00 – 1:30 Richardson Signal Chain
1:30 - ? All Questions / Answers
©2018 Analog Devices, Inc. All rights reserved.

2
Checking out your hardware/software
Try this out now! Help us help you.
► From console/DOS window type:

▪ “iio_info –s<ret>”
Not working
▪ <ret> indicates return key
▪ iio_info (underscore), not iio-info (dash) Working
▪ Should find the PlutoSDR

▪ If this works – great
▪ If this doesn’t work – please put up your hand,
and someone will come to help
3 ©2018 Analog Devices, Inc. All rights reserved.

Checking out your hardware/software
Try this out now! Help us help you.
► From MATLAB prompt type:

▪ “findPlutoRadio()<ret>”
▪ <ret> indicates return key

Not working
▪ Should find the PlutoSDR
▪ If this works – great
▪ If this doesn’t work – please put up your hand, Working
and someone will come to help

Get the labs (if you haven’t already)
► https://wiki.analog.com/sdrseminars
▪ Get the lab zip file:

Hands-on Workshop:
Software-Defined Radio
ANALOG DEVICES
ROBIN GETZ
TRAVIS COLLINS
MATHWORKS
CURIE CHUNG
NOAM LEVINE
RICHARDSON RFPD
MARK VITELLARO
VINCE WRIGHT
©2018 Analog Devices, Inc. All rights reserved. 6

Copyright and Disclaimer
► Portions of this presentation are ©2018 Analog Devices, Inc. All rights reserved.
► Portions of this presentation are ©2018 MathWorks. All rights reserved.
► Portions of this presentation are ©2018 Richardson RFPD. All rights reserved.
These PowerPoint slides are the intellectual property of the content creator and are protected under
the copyright laws of the United States of America and other countries. All rights are reserved. All
trademarks are the property of their respective owners.
While we have made every attempt to ensure that the information contained in this presentation is
accurate and reliable, neither Analog Devices, MathWorks or Richardson RFPD is responsible for
errors or omissions, or for the results obtained from the use of this information. All information is
provided “as is” with no guarantee of completeness, accuracy, timeliness or the results obtained from
the use of this information, and without warranty of any kind, expressed or implied, including, but not
limited to warranties of performance, merchantability and fitness for a particular purpose.

7
Welcome
• AD9361 (chip)
IIO Oscilloscope
• Hands on labs
• Hands on labs
• Hands on labs
12:00 Lunch

8
Presenters: Richardson RFPD
Mark Vitellaro Vince Wright

Global Marketing Local Field Sales Engineer
Danny Molezion
RF Applications Engineer NA
9
Presenters : Analog Devices
Dr. Travis F. Collins Robin Getz

Communications Development Engineer Director of Systems Engineering
Analog Devices Analog Devices
Travis holds M.S. and Ph.D. degrees in electrical and computer engineering from Robin has spent 25 years in the semiconductor industry, and has held positions
Worcester Polytechnic Institute (WPI) in Worcester, MA. Dr. Collins’ research is ranging from applications engineer to field applications engineer to director of
focused on small cell interference modeling, phased-array localization, and high engineering. He has worked on a variety of systems in the analog, digital, RF, and
performance computing for software defined radio (SDR). He has extensive software domains, as well as with large direct customers and smaller customers.
Robin has been with Analog Devices for 19 years and is the director of
experience developing for SDR applications in many different software engineering for Analog Devices Inc. Systems Development Group, where he
environments, hardware architectures, and remains active in several opensource- works creating HDL interfaces and device drivers for ADI’s mixed-signal IC
based SDR projects. Currently, Dr. Collins works as a development engineer for products. He holds four patents and a B.Sc. (EE) from the University of
Analog `Devices, Inc. (ADI) in the Systems Development Group. At ADI, Dr. Saskatchewan.
Collins is responsible for transceiver applications and works heavily on hardware
and software integration projects. Linked In : https://www.linkedin.com/in/rgetz/
EngineerZone : travisfcollins Twitter : @robinlgetz

EngineerZone : rgetz

10
Presenters : MathWorks
Noam Levine Curie Chung

Partner Manager Principal Application Engineer
MathWorks MathWorks
Noam has worked in Technical Marketing at MathWorks for 10 years, Curie has spent 17 years working on various aspects of FPGA designs
concentrating on hardware-targeted, application-based workflows. and tools, from digital and system designs, HDL code generation and
Prior to joining MathWorks, Noam spent over 15 years in the verification tools development, to her current role in application
semiconductor industry working on digital signal processing solutions. engineering, where she works with customers to evaluate and adopt
He holds an M.S.E.E. from Northeastern University and a B.S.E.E. MathWorks products into their FPGA/ASIC design flow. Curie holds an
from Boston University. MSEE from Stanford University and a BSEE from University of
Michigan, Ann Arbor.
©2018 The MathWorks ,Inc. All rights reserved.

11
• AD9361 (chip)
Richardson RFPD Overview IIO Oscilloscope
• Hands on labs
• Hands on labs
• Hands on labs
12:00 Lunch

Richardson RFPD
Global RF, Wireless, Industrial IoT, Energy & Power Expert

• Electronic Components & Engineered Solutions
• Deep and Broad Selection of Quality Components, Modules and Kits
• Expert Team of RF Designers and Engineers

• ~245 Customer-Facing Team Members: 128 FSEs, 28 FAEs and 89 ISRs
• Value-Added Services
• Design-In Resources, System Integration, Testing and Application Engineering
• Integrated Supply Chain and Global Logistic Centers

• Reno, Nevada; Hong Kong, China; Venlo, Netherlands
• 35 Sales Offices and Locations, 6 Engineering Centers
• Richardson RFPD, Inc. - Wholly Owned Subsidiary of Arrow Electronics

• Corporate Headquarters in Geneva, IL - USA
Our Company Evolution
Acquired By Arrow Electronics

March 2011 Who we are today:
Founded in 1947
RFPD Richardson
Richardson RFPD, Inc
A Business Unit
of RELL RFPD, Inc
An Arrow Company
Throughout the Company’s evolution, the philosophy has not changed, Richardson RFPD
remains a design-led RF and Power Specialized Distributor, providing both suppliers and
customers, technology design support and market awareness
Richardson RFPD Line Card
• Leading RF & Wireless

Suppliers
• Over $100M in inventory
• Over 11,000 SKUs in stock
• Over 2,000 RF Evaluation and
Development Tools available
• www.richardsonrfpd.com
• AD9361 (chip)
Brief Intro to the Pluto SDR IIO Oscilloscope
• Hands on labs
• Hands on labs
• Hands on labs
12:00 Lunch

Communications and Radios are hard
Software Defined Radio makes it worse!
RF Hardware skills
► Designs are complex
▪ Multiple skillsets RF
▪ Multiple technologies Design
► Radio Developer needs
▪ Fast prototyping
▪ Complete reference designs
▪ antenna to MATLAB SoC
▪ Streaming Software Assembly
▪ Targeting Engineering
▪ Easy to use prototyping platforms
SDR
▪ Complete workflows – easy to use toolchains
▪ Path to production
▪ Reduced system complexity
▪ Hardware
▪ Software
▪ Mechanics DSP Digital
▪ Reduced risk Algorithms Hardware
► Ease of use sometimes beats
performance
▪ Many decisions are made by the system Communications theory
engineer in the prototyping stage
Traditional RF Evaluation Platforms
(Antenna to Bits and Back™, circa IMS 2010)
 Discrete single product evaluation boards,

 connected with SMA cables
 Power supplies
 External oscillators
 Tuning filters
 No Antenna
 6 power supplies
 4 different USB applications
 Not easy to replicate, or use as part of a

SDR prototyping solution
 Needed small form factor, open design

Enabling Technologies
Simulation and
Code Transitional
Generation Hardware
Tools
Flexible
Infrastructure

Design Flow
Research Algorithm Design Prototype Production

Development Elaboration
• Behavioral • MATLAB • MATLAB • Deployment to • Deployment to

Simulation reference • Simulink development custom
• Streaming data implementation modeling board hardware
to MATLAB • Hardware • Hardware • Design • Validation with
and IIO-Scope streaming streaming optimization complete
• Data type • HDL hardware
conversion Integration solution
• Driver
Integration
PlutoSDR aaaaa
RFSoM+FMC Carrier or Eval FMC + FPGA Carrier
PackRF or RFSoM + Custom Carrieraaaaaaaaaaaaaaaaaaaaaaaaaaaa
Custom aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

20
Design Flow
Algorithm Design
Research Prototype Production

21
Challenge
From devices/chips: ► AD936x is the SDR standard for high

performance agile transceivers
► AD937x is designed for applications that
require high performance radio transmissions
across a wideband frequency range, such as
3G/4G BTS with advanced signal processing
► ADRV900x is designed for applications that
require high performance radio transmissions
across a very wideband frequency range
including 4G/5G BTS and phased array radar
systems

Challenge
From devices/chips: To Products:

RadioVerse Evaluation and Prototyping Hardware
ADALM-PLUTO AD-FMCOMMS2 AD-FMCOMMS4 ARRADIO AD-FMCOMMS5 ADRV9371-N/PCBZ ADRV9375-N/PCBZ ADRV9008-1W/PCBZ (Rx)

• AD9363 AD-FMCOMMS3 • AD9364 • AD9361 • 2 x AD9361 ADRV9371-W/PCBZ ADRV9375-W/PCBZ ADRV9008-2W/PCBZ
• 1 x Rx, 1 x Tx • AD9361 • 1 x Rx, 1 x Tx • HSMC, not FMC • 4 x Rx, 4 x Tx • AD9371 • AD9375
• 325 MHz – 3.8GHz • 70 MHz – 6GHz • 2 x Rx, 2 x Tx • Synchronized RF (Tx/Obs)
• 2 x Rx, 2 x Tx • 2 x Rx, 2 x Tx, 2 x Obs, 1x • 2 x Rx, 2 x Tx, 2 x Obs, 1x
• 200kHz – 20 MHz • tuning range tuning range • 2.2 GHz – 2.6GHz • 70 MHz – 6GHz tuning Sniffer Sniffer ADRV9009-W/PCBZ (TDD)
channel bandwidth • 2.2 GHz – 2.6GHz • 200kHz - 56 MHz tuning range range • tuning range • tuning range • ADRV9008-1, ADRV9008-2,
• 70 MHz – 6GHz channel bandwidth • 200kHz - 56 MHz • 200kHz - 56 MHz • 1.8GHz – 2.6GHz • 1.8GHz – 2.6GHz ADRV9009
• 200kHz - 56 MHz • Shipping Now channel bandwidth channel bandwidth • 300MHz – 6GHz • 300MHz – 6GHz • 2 x Rx, 2 x Tx, 2 x Obs, 1x Sniffer
channel bandwidth • Shipping Now! • Shipping Now! • Tx synthesis bandwidth 250 • DPD actuator and • 75MHz - 6GHz tuning range
MHz adaptation engine for PA • Tx synthesis bandwidth 450 MHz
• Rx BW: 8 MHz to 100 MHz linearization • Rx BW to 200 MHz
ADRV9364-Z7020 PACKRF ADRV-DPD1 ADRV9009-ZU11EG

ADRV9361-Z7035 • ADRV9361 reference • AD9375 + 250 mW PA • 2 x ADRV9009 + Zynq
• AD9364 + Zynq 7020 design • 2 Rx, 2 Rx Uiltrascale
• AD9361 + Zynq 7035 • Battery, PoE, Screen, • LTE Band 7 • 75MHz to 6GHz tuning range
• 70 MHz – 6GHz tuning Audio, GPS, IMU • 2500 to 2570 Uplink • Rx BW 200MHz
range • 2620 to 2690 MHz • Tx synthesis bandwidth 450
• 200kHz - 56 MHz Downlink MHz
channel bandwidth • 2 PAs, 2 LNAs, duplex • Integrated LO and Phase synch
• 1GB DDR + 32MB filters between all channels and
FLASH Modules
• Ethernet + USB Phy • 4G x64 w/ECC PS; 4G (2Gb
x32 x2Banks) PL
• USB3, USB2, PCIe 3.0 x8,
QSFP+, SFP+, 1Gb Ethernet
x2, and CPRI
ADI ZIF Transceivers
Rx
USB 2.0 OTG

FPGA
ARM
PCB Component
Channel Attenuation
frequency wide
turning range (70 –
6000 MHz)
(Close to datasheet
specs)
Tx

Back to Basics : Fourier domain
► The Fourier is fundamentally a change of ► Gibbs phenomenon, which states if you add
basis. The basis into which the Fourier sine waves at specific frequency / phase /
changes your original signal is a set of sine amplitude combinations you can approximate a
waves instead. square wave,
► In order for that basis to describe all the
possible inputs it needs to be able to represent
phase as well as amplitude;
▪ the phase is represented using complex numbers.
𝐴 ∅ = 𝑅𝑒𝑎𝑙 + 𝑗 𝐼𝑚𝑎𝑔

Back to Basics : Euler’s Formula
𝒆𝒋𝒙 = cos 𝑥 + 𝒋 sin(𝒙) ; 𝒆𝒋𝝅 = −𝟏
Modulator stage
▪ Sin 0t is 90 out of phase with respect to cos 0t

▪ With perfect amplitude and phase matching the
signal content at -0 cancels
▪ More information : Chapter 2 : Signals and Systems
ADALM-PLUTO (PlutoSDR)

28
PlutoSDR: Block Diagram
16

29
Other Hardware: Block Diagram
FPGA Development System ADI FMC Card ADI RF System on Module
32
32
Ethernet Ethernet

30
Platform Options
Platform FPGA Logic Block DSP Cores Platform Device Tuning Bandwidth MSPS Tx Rx
Cells RAM Slices Range
ADI Zynq 7010 28k 2.1 Mb 80 1 x ARM A9 ADALM-PLUTO AD9363 300 – 3800 200 kHz – 61.44 1 1
ADALM-PLUTO @ 666 MHz MHz 20 MHz MSPS
Xilinx Zynq 7020 85k 4.9 Mb 220 2 x ARM A9 AD-FMCOMMS2 AD9361 2400 – 200 kHz – 61.44 2 2
ZED @ 866 MHz 2500 MHz 56 MHz MSPS
ADI Zynq 7020 85k 4.9 Mb 220 2 x ARM A9 AD-FMCOMMS3 AD9361 70 – 6000 200 kHz – 61.44 2 2
ADRV9364-Z7020 @ 866 MHz MHz 56 MHz MSPS
ADI Zynq 7035 275k 17.6 Mb 900 2 x ARM A9 AD-FMCOMMS4 AD9364 70 – 6000 200 kHz – 61.44 1 1
ADRV9361-Z7035 @ 866 MHz MHz 56 MHz MSPS
Xilinx Zynq 7045 350k 19.2 Mb 900 2 x ARM A9 ADI AD9361 70 – 6000 200 kHz – 61.44 2 2
ZC706 @ 866 MHz ADRV9361-Z7035 MHz 56 MHz MSPS
Intel Arria 10 SoC 10AS066 660k 47.7 Mb 3,376 2 x ARM A9 ADI AD9364 70 – 6000 200 kHz – 61.44 1 1
@ 1.5 GHz ADRV9364-Z7020 MHz 56 MHz MSPS
Xilinx Zynq 600k 40.8 Mb 2,520 4x ARM A53 ADRV9371- AD9371 300 - 6000 8 MHz to 122.88 2 2+
ZCU102 Ultrascale @ 1.5 GHz WPCBZ MHz 100 MHz MSPS Obs
XCZU9EG
ADRV9009- ADRV9009 75 - 6000 200 MHz 245.76 2 2
ADI Zynq 653k 52.7 Mb 2,928 4x ARM A53 W/PCBZ MHz MSPS
ADRV9009- Ultrascale @ 1.5 GHz
ZCU11EG XCZU11EG ADRV9009- 2x 75 - 6000 200 MHz 245.76 4 4
ZCU11EG ADRV9009 MHz MSPS

ADALM-PLUTO USB OTG Connectivity Options
Connect to host USB Thumb Drive USB LAN USB WiFi USB Audio
Linux Mac Windows
eLinux
32

Connecting With PlutoSDR
► Pluto enumerates four devices

▪ Mass storage
▪ Ethernet (RNDIS)
▪ Serial
▪ IIO

ADSB with dump1090
https://github.com/PlutoSDR/dump1090
► Automatic dependent surveillance—broadcast

(ADS–B) is a surveillance technology in which
an aircraft determines its position via satellite
navigation (GPS) and periodically broadcasts
it, enabling it to be tracked.
▪ https://en.wikipedia.org/wiki/Automatic_dependent_surveillance_%E2%80%93_broadcast
► dump1090 is an open source application, to

receive and display ADS-B information
► Three easy steps:

1. Transfer it to Pluto via network (scp)
2. Change it to execute (it’s Unix)
3. Run it

Questions about Pluto SDR
► Pluto is an embedded Linux device

▪ Uses Linux’s USB Gadget
▪ Mass storage
▪ Serial
▪ Ethernet (RNDIS)
▪ IIO
▪ Can be standalone
▪ ~ same performance as Rasberry Pi 1
▪ Supports USB Host
▪ Open Source Firmware, Open Source HDL, Open
Schematics
► For more information:

▪ www.analog.com/plutosdr
▪ wiki.analog.com/plutosdr http://www.iconarchive.com/show/noto-emoji-objects-icons-by-google/62807-radio-icon.html
http://www.streamlineicons.com
▪ For further information, check out the text http://pixelkit.com
▪ Chapter 5: Understanding SDR Hardware

• AD9361 (chip)
Model Based Design IIO Oscilloscope
• Hands on labs
• Hands on labs
• Hands on labs
12:00 Lunch

Design Flow
Algorithm Design

37
Design Flow (Model-Based Design)
Research
• Behavioral
Simulation
• Streaming data
to MATLAB
and IIO-Scope
©2018 MathWorks, Inc. All rights reserved.

38
Research Algorithm
Development
• Behavioral • MATLAB
Simulation reference
• Streaming data implementation
to MATLAB • Hardware
and IIO-Scope streaming

Research Algorithm Design

• Behavioral • MATLAB • MATLAB

Simulation reference • Simulink
• Streaming data implementation modeling
to MATLAB • Hardware • Hardware
and IIO-Scope streaming streaming
• Data type
conversion

40
Research Algorithm Design Prototype

• Behavioral • MATLAB • MATLAB • Deployment to

Simulation reference • Simulink development
• Streaming data implementation modeling board
to MATLAB • Hardware • Hardware • Design
and IIO-Scope streaming streaming optimization
• Data type • HDL
conversion Integration
• Driver
Integration

41


• Driver
Integration
Tx data mux
Raw data Rx & Tx DMAs
©2018 MathWorks, Inc. All rights reserved. Modem Rx & Tx DMAs

42
Design Flow


• Driver
Integration
PlutoSDR aaaaa

43
Questions about Model Based Design?
► Model Based Design is a

development methodology which
eases transitions between
development steps
► For more information:

▪ Wikipedia page
▪ https://en.wikipedia.org/wiki/Model-based_design
▪ MathWorks page
▪ https://www.mathworks.com/solutions/model-based-design.html
▪ MathWorks / ADI Webinar

▪ https://www.mathworks.com/videos/radio-deployment-on-soc-
platforms-1513346830203.html
http://www.iconarchive.com/show/noto-emoji-objects-icons-by-google/62807-radio-icon.html
http://pixelkit.com

44
• AD9361 (chip)
9:45 – 10:00
Linux’s Industrial Input/Output
MathWorks Model Based Design
(IIO) infrastructure IIO Oscilloscope
• Hands on labs
• Hands on labs
• Hands on labs
12:00 Lunch

IIO Concepts
► The Linux Industrial I/O (IIO) subsystem is

intended to provide support for devices that, in
some sense, are analog-to-digital or digital-to-
analog converters
▪ Devices that fall into this category are:
▪ ADCs
▪ DACs
▪ Accelerometers, gyros, IMUs
▪ Capacitance-to-Digital converters (CDCs)
▪ Pressure, temperature, and light sensors, etc.
▪ RF Transceivers (like the AD9361/AD9364)
▪ Can be used on ADCs ranging from a 1MSPS
SoC ADC to >5 GSPS ADCs
▪ Developed during 2009, committed Jan 2010,
moved out of staging Nov 2011, now in all
mainline Linux kernels.

Goal: How to I control the device?
LO Frequency

Pluto Gain Control
/sys/
bus/ 1dB Step Size
iio/
iio:device0/
dev name out_voltage0_hardwaregain out_voltage1_hardwaregain
DEVICE CHANNEL
AT T R I B U T E AT T R I B U T E
Shell Commands:
/sys/bus/iio/iio:device0 # cat name
ad8366-lpc
/sys/bus/iio/iio:device0 # echo 6 > out_voltage1_hardwaregain
/sys/bus/iio/iio:device0 # cat out_voltage1_hardwaregain
5.765000 dB
48
IIO – libiio
► System library #!/usr/bin/env python
import iio
► Abstracts away low level details of the IIO kernel
ctx = iio.Context()
ABI
▪ Kernel ABI is designed to be simple and efficient for dev in ctx.devices:
print dev.name
▪ libiio focuses on ease of use
► Provides high-level C, C++, C# or Python
programming interface to IIO (Language bindings)
C C++ C#
Language Bindings
High-level API
Backends
For more information:
https://github.com/analogdevicesinc/libiio
http://wiki.analog.com/resources/tools-software/linux-software/libiio_internals
http://analogdevicesinc.github.io/libiio/

49
IIO – libiio – Backends
► Support for backends

▪ Backend takes care of low-level communication
details
▪ Provide the same API for applications
▪ Transparent from the applications point of view
Backends
local NET USB PCIe Serial
IIOD Remote via iiod
IIO NET USB PCI tty
Linux Kernel

50
libIIO and applications
► Iio-utils (command line tools)

► IIO-Scope
► MATLAB and Simulink
► GNU Radio
► 3rd part apps
▪ SDR Angel
▪ GQRX
▪ SDR#
▪ …
► Language support for libIIO

▪ C/C++
▪ Python
▪ Nodejs (3rd party)
▪ C# (3rd part)

51
IIO – libiio – Command line tools
► iio_info : Information about all IIO devices, backends and context attributes
▪ iio_info -s
▪ iio_info –u ip:192.168.2.1
► iio_attr : Read and write IIO attributes

▪ iio_attr -c ad9361-phy altvoltage0 frequency 2450000000
► iio_readdev : Read samples from an IIO device

▪ iio_readdev -u usb:1.100.5 -b 100000 cf-ad9361-lpc | pv > /dev/null
► iio_writedev : Write samples to an IIO device

▪ iio_readdev -b 100000 cf-ad9361-lpc | iio_writedev -b 100000 cf-ad9361-dds-core-lpc
► iio_reg : Read or write SPI or I2C registers in an IIO device (useful to debug drivers)
▪ iio_reg adrv9009-phy 0

52
IIO-Scope
► Capture and display data

▪ Time domain
▪ Frequency domain
▪ Constellation plot
▪ Markers
▪ Math operations
► Device configuration
► Plug-in system allow to create device or
complex specialized GU
► Should support any IIO device
► Cross platform

53
IIO-Tools + IIO-Scope
Instructor-Led Demo
► Demo of iio-utils
▪ Open IIO Scope
▪ Attach USB Devices (Pluto)
▪ Capture and Display Signals
▪ Change LO

Questions about IIO-Tools + IIO-Scope?
► IIO scope is cross platform

▪ Linux, MAC, Windows
▪ i386, amd64, arm (on Zynq, or Raspberry Pi)
▪ Runs remote or local
▪ Local requires linux
▪ Lots of local devices on standard laptops
► IIO has lots of on-line documentation

▪ wiki.analog.com
http://pixelkit.com

Hands On Lab
9:55 - 10:15
► IIO command line tools

► the IIO Oscilloscope
► 20 min
► By end of lab, you will understand :

▪ how to talk to radio at low levels (command line
tools)
▪ Interact with high level visualizations
▪ Debug radio basics
http://pixelkit.com

Questions about IIO-Tools + IIO-Scope?
► Any Questions about Lab?
► IIO has lots of on-line documentation

▪ wiki.analog.com
► For further information, check out the text

http://pixelkit.com

• AD9361 (chip)
MATLAB / Simulink and System 10:00 – 10:45 Analog Devices IIO infrastructure and Software Tools
Objects IIO Oscilloscope
• Hands on labs
• Hands on labs
• Hands on labs
12:00 Lunch

Blocks and System Objects Using IIO Under the Hood
©2018 The MathWorks ,Inc. All rights reserved.

59
Blocks and System Objects Using IIO Under the Hood
Pluto SDR

60
System Objects and Block
Instructor-Led Demo
61 ©2018 The MathWorks ,Inc. All rights reserved.

Questions about System Objects and Blocks?
► System objects are designed specifically for

implementing and simulating dynamic systems
with inputs and outputs that change over time.
► Use to interact with streaming hardware
http://pixelkit.com

Hands On Lab
10:20 – 10:30
► MATLAB interacting with Pluto SDR

AND/OR
► Simulink interacting with Pluto SDR
► 10 min

▪ It’s easy to connect the Pluto SDR to MATLAB
and Simulink, and transfer data
http://pixelkit.com

Questions about System Objects and Blocks?
► Any questions about lab?
http://pixelkit.com

• AD9361 (chip)
Data Flow and Transfers IIO Oscilloscope
• Hands on labs
• Hands on labs
• Hands on labs
12:00 Lunch

Streaming: Basic Idea
► Controlling transceiver
► Getting data to and from
Pluto SDR transceiver

66
Pull/Push Sink/Source Data
► DAC (Tx) sinks data ► ADC (Rx)

▪ Call buffer_refill() often enough, or hardware send ▪ Call buffer_refill() often enough, or hardware
zeros drops data
▪ DAC is data sink ▪ ADC is a data source
▪ Up to user to ensure queue has data ▪ Up to user to ensure that queue has space
Incoming queue
…
User space Kernel space
application DMA Controller DAC application DMA Controller ADC
Outgoing queue

The Stack

68
Buffer management & burst
Low data rates, low host DSP – real time
Air interface
• Continuous time
RF
• Bandwidth
• LO
Data interface
• Discrete samples A B C D A B C D
• 12-bits, I/Q
• 520 kSPS to 61.44 MSPS
• FPGA + ARM
• Buffers
PLUTO
• Limited by DDR3 memory

• Bandwidth
• Size
A B C D A B C
Transfer (USB)
• buffers
• samples
• Limited by USB speed
• Latency dominated by operating system
A B C D A B C
Application
HOST
• Limited by PC MHz
• Limited by PC memory
• Some frameworks are not threaded

high data rates, high DSP – lost samples, first n buffers are continuous
Air interface
• Continuous time
RF
• Bandwidth
• LO
Data interface
A B C D A B C D
• Discrete samples
• 12-bits, I/Q
• FPGA + ARM
• Buffers
PLUTO

• Bandwidth
• Size
Transfer (USB) A B C D A
• buffers
• samples
Application
HOST

Pause = stale data (backpressure management)
Air interface
• Continuous time
RF
• Bandwidth
• LO
Data interface
• Discrete samples A B C D A B
• 12-bits, I/Q
• FPGA + ARM
• Buffers
PLUTO

• Bandwidth
• Size
A B
Transfer (USB)
• buffers
• samples
A B
Application
HOST

Icon made by Freepik from www.flaticon.com is licensed by CC 3.0 BY
Questions about Data Transfer?
► Although most high level design environments

(like MATLAB and Simulink) abstract / hide
these implementation details away from the
user, you still may run into issues which are
caused by these underlying system
architecture
▪ For further information, check out the text

http://pixelkit.com

Slow USB transfers are OK
Figure out Signal processing Get Signal processing embedded
Algorithm Design
Seconds
MB/s External
MByte/s of RF
MHz MSPS single Memory
(I/Q) Data in
channel (Mbytes)
Memory
56 61.44 122.88 245.76 128 0.521
18 30.72 61.44 122.88 128 1.042 512 MBytes on Pluto SDR
9 15.36 30.72 61.44 128 2.083 Linux kernel continuous memory allocator;
4.5 7.68 15.36 30.72 128 4.167 128MBytes for Tx, and 128MBytes for Rx
2.25 3.84 7.68 15.36 128 8.333
Takes about ~4 seconds to transfer 128
.200 0.520 1.04 2.08 128 61.44
Mbytes over USB 2.0

73
• AD9361 (chip)
Communications Engineering with 10:00 – 10:45 Analog Devices IIO infrastructure and Software Tools
PlutoSDR IIO Oscilloscope
• Hands on labs
• Hands on labs
• Hands on labs
12:00 Lunch

Design Flow
Algorithm Design

75
Creating Practical Communication Systems
► Textbook published by Artech House
Analytical MATLAB Hardware

Description Simulation Verification
► Topics covered:
▪ Intro to signal processing and probability
▪ Intro to hardware and controlling software
▪ Timing Recovery
▪ Frequency Recovery
▪ Frame Synchronization
▪ Channel Equalization and Coding
▪ OFDM
▪ Advanced Topics
Understanding Sources of “Offset”
Analog Domain Separate PLLs

Propagation
Light travels ~33.6 ps/cm

2 GHz = 500ps
1 cm = 24° @ 2 GHz

77
Timing Offset: Chapter 6
► Fractional and integer offsets can be

modeled as:
► Upsampling and selective

decimation compensates for this
problem

78
Carrier Offset
► Carrier offset can be modeled as:

Demonstration with Simulation and Hardware
Instructor-Led Demo
Turn into
80
Questions about signal recovery?
► Carrier Frequency Offset (CFO) and Timing

Correction are mathematically intense
▪ For further information, check out the text
▪ Chapter 6: Timing Synchronization
▪ Chapter 7: Carrier Synchronization
▪ Chapter 8: Frame Synchronization and Channel
Coding
▪ Not interchangeable without tradeoffs

▪ Mathematically designed to go in a certain order
► Questions?
http://pixelkit.com

Hands On Lab
10:45 – 11:30
► Part 1 : System objects, controlling Pluto

► Part 2 : Dealing with Buffers (overflow)
► Part 3 : Timing and carrier recovery
► 45 min

▪ How to control Pluto from MATLAB
▪ How to capture and transmit data
▪ How correct for timing and carrier impairments http://www.iconarchive.com/show/noto-emoji-objects-icons-by-google/62807-radio-icon.html
http://pixelkit.com

Questions about signal recovery?
► Questions about Lab?
► CFC : coarse frequency correction

▪ Section 7.2.1
► Matched Filter
▪ Section 6.1
► Timing Recovery
▪ Section 6.3
► Carrier Recovery
▪ Section 7.2
► Frame Sync
▪ Chapter 8
► Equalization http://www.iconarchive.com/show/noto-emoji-objects-icons-by-google/62807-radio-icon.html
▪ Chapter 9 http://pixelkit.com

• AD9361 (chip)
MathWorks Advanced Workflows IIO Oscilloscope
• Hands on labs
11:30 – 11:45 • Hands on labs
• Hands on labs
12:00 Lunch

Design Flow
Algorithm Design

85
Design Flow
Algorithm Design

86
Design Elaboration
► Move model closer to hardware implementation

▪ HDL-compatible blocks
▪ Hardware-efficient architectures
▪ Fixed-point data types
87
Design Elaboration
► Move model closer to hardware implementation

▪ HDL-compatible blocks
▪ Hardware-efficient architectures
▪ Fixed-point data types
88
Design Flow
Algorithm Design

89
Hardware / Software Codesign
Part of system runs on

Programmable Logic
Part of system runs on ARM Processing System

HDL Workflow Advisor
©2018 MathWorks. All rights reserved.

HDL Workflow Advisor

92
HDL Code Generation Report

Generated Readable and Traceable Code

Vivado Project Generation

Bitstream Generation

Software Interface Model
97 ©2018 MathWorks, Inc. All rights reserved.

Design Flow
Algorithm Design

98
Production
► Uses a combination of a custom reference design with HDL Coder

► Requires more in-depth knowledge of the hardware and FPGA vendor tools
Tx data mux
Raw data Rx & Tx DMAs
Modem Rx & Tx DMAs

99
99 ©2018 MathWorks, Inc. All rights reserved.

• AD9361 (chip)
Dealing with Custom Hardware IIO Oscilloscope
• Hands on labs
11:45 – 11:55 • Hands on labs
• Hands on labs
12:00 Lunch

Design Flow
Algorithm Design

101
Evaluating the AD9361
► Hardware
▪ AD-FMCOMMS2-EBZ (AD9361)
▪ Narrow RF Tuning Range
▪ Wide RF Tuning Range
▪ Narrow and Wide tuning range
▪ AARADIO (AD9361)
Arrow SoCKit + ARRADIO
▪ Narrow RF Tuning Range
ZC706 + FMCOMMS2

AD936X Transceiver Family
• AD936X is the SDR standard

for high performance agile
transceivers
• RF-SOM helps streamline
system integration and
development

Analog Devices RF SOM (System on Module)
ADRV9361-Z7035 RF SOM : $1095 ADRV9364-Z7020 RF SOM : $549

► Processor ► Processor
▪ Dual Core ARM Cortex A9 (800MHz each) ▪ Dual Core ARM Cortex A9 (800MHz each)
▪ L1 cache : 32 KB Instruction, 32 KB Data ▪ L1 cache : 32 KB Instruction, 32 KB Data
▪ L2 cache : 512 KB ▪ L2 cache : 512 KB
► FPGA ► FPGA
▪ Kintex-7 Fabric ▪ Artix-7 Fabric
▪ 275K Logic Cells ▪ 85K Logic Cells
▪ ~4.1M Asic gates ▪ ~1.3M Asic gates
▪ 17.6 Mb Block RAM ▪ 4.9 Mb Block RAM
▪ 900 DSP Slices ▪ 220 DSP Slices
▪ Vivado license required Xilinx 7035 ▪ Zero Cost Vivado Webpack Xilinx 7020
► 1 Gbyte DDR3L ► 1 Gbyte DDR3L

► 32 Mbyte SPI Flash ► 32 Mbyte SPI Flash
► MicroSD Card (lockable) ► MicroSD Card (lockable)
► Radio ► Radio
▪ 200kHz - 56 MHz RF bandwidth ▪ 200kHz - 56 MHz RF bandwidth
▪ 128-tap FIR Filters for equalization ▪ 128-tap FIR Filters for equalization
▪ 70 – 6000 MHz tuning range ▪ 70 – 6000 MHz tuning range
▪ 2 Rx, 2 Tx, 2 Tx Monitor ▪ 1 Rx, 1 Tx, 1 Tx Monitor
ADI AD9361 ADI AD9364
► 10/100/1000 Ethernet (MAC + Phy) ► 10/100/1000 Ethernet (MAC + Phy)
► USB 2.0 (OTG Controller + Phy) ► USB 2.0 (OTG Controller + Phy)
► Low power ► Low power
▪ sub 5W at full RF data rates ▪ sub 5W at full data rates
► Full Linux based reference design ► Full Linux based reference design
► Fully integrated and tested system ► Fully integrated and tested system
► Common 400 pin connector ► Common 400 pin connector
► Digital I/O pins : ► I/O pins :
► U.FL connectors : 10 ► U.FL connectors : 5
AD9361 based RF SOM Hardware
BOB ► RF-SOM Configurations

► AD9361-Z7035
► AD9364-Z7020
► Breakout boards
► FMC
FMC
► BOB
Same
SOM
PCIe
PackRF : field trials
► Example design which shows how to design RF PWR Switch SOM2

SOM into a custom carrier IMU
► Custom Carrier includes:
▪ OLED
▪ Nav Switch
▪ Power Button Battery
▪ Wake on RTC RF Card
▪ Power over Ethernet (PoE+)
▪ Automotive DC-DC converter
▪ 8 – 48V DC input
▪ Battery Management
▪ Hot Power swap
▪ Inertial Measurement Unit
▪ Six Degrees of Freedom
▪ GPS Chipset
▪ 1 PPS in and out
▪ Audio headset (stereo headphones, mic and button
control)

106
Exploded View
PWR Switch SOM2
IMU
Battery RF Card
Toward the analog

ADRV9009-ZU11EG
► Dual ADRV9009 + Expandable daughterboard

▪ 4T and 4R or 8T and 8R (with daughterboard)
► Xilinx Ultrascale+ ZU11EG
▪ 600K logic cells
▪ 2250 DSP slices
► 4 GB DD4 ECC for PS
► 2x 2 GB banks dedicated for PL
► SFP+, QSFP+, USB3, PCIe 3.0 x8
► Available Q1 2019

Moving to the Production Design
• RFSOM on FMC Carrier Board • RFSOM on Custom Carrier Board

Algorithm
Unchanged
Same RF-SOM
New Carrier
Board
Same
Connectivity
► Path from supported development hardware to production hardware

► Documented process from MathWorks called Board Support Packages
▪ ADI maintains examples for different board variants
► Provides same connectivity in final production hardware back to MATLAB
Example Reference Design Demonstrating Workflow
RX TX
950 MHz
Modem 1aaaaa a Modem 2
PackRF sss Aaa PackRF
TX RX
900 MHz
► Example design works through

QPSK modem development
► Example details:
▪ QPSK PHY with continuous link
▪ Simple FDD system (MAC)
▪ Built with common algorithms

PackRF : Video Transmission
Instructor-Led Demo
► PackRF transmitting video

▪ Station 1
▪ USB Host
▪ USB Web Camera
▪ RF Link
▪ Simple FDD Modem
▪ TCP/UDP link via tun/tap
▪ FFMPEG (in userspace) to transmit video
▪ Station 2
▪ RF Link
▪ FFMPEG (in userspace) to receive video
112
Questions about PackRF?
► PackRF transmitting video

▪ Station 1
▪ USB Host
▪ USB Web Camera
▪ RF Link
▪ FFMPEG (in userspace) to transmit video
▪ Station 2
▪ RF Link
▪ FFMPEG (in userspace) to receive video
► Available for sale in Jan 2019 http://pixelkit.com

Design Flow


• Driver
Integration
PlutoSDR aaaaa

114
System solutions
Ecosystems Support
Documentation
Development & Debug Toolchains
HDL Software Simulation

• IP cores • Linux drivers • Models
• FPGA designs • no-OS drivers • Algorithms
• SoC designs • Applications • Hardware in the
loop
115
Support and help
► Contact your MathWorks ► Two-day SDR Workshop

sales representative, or visit with Analog Devices and
► Support: mathworks.com/training
MathWorks
for a schedule of available
classes: ▪ Deeper exploration of
▪ DSP for FPGAs (3 days) targeting workflows
▪ http://ez.analog.com ▪ Generating HDL Code from ▪ See us after today’s event to
Simulink (2 days) learn more
▪ Embedded Linux and System
► Documentation: Integration for Zynq (2 days)
▪ Programming Xilinx Zynq ► ADALM-PLUTO
SoCs with MATLAB and ▪ $149 (USD)
Simulink (2 days)
▪ http://wiki.analog.com
▪ Make great gift for the
▪ Software-Defined Radio with
Zynq using Simulink (1 day)
holidays

• Debug Installation Issues
• Check Connectivity to hardware
• Hardware Checkout
9:15 – 9:30 Analog Devices • Pluto SDR (system)
• IIO (software)
• AD9361 (chip)
Lunch IIO Oscilloscope
• Hands on labs
• Hands on labs
10:30 – 11:30 Analog Devices basic communications theory
• Hands on labs
11:45 – 12:00 Analog Devices ADI Board Support Packages and model based design examples
12:00 - Lunch

117
• AD9361 (chip)
Signal Chains IIO Oscilloscope
• Hands on labs
12:00 – 12:30 • Hands on labs
• Hands on labs
12:00 Lunch

Addressing the Full RF Spectrum
Magnetic Satellite Communications
Resonance Wireless Cellular, WiMAX Short Haul Payload Long Haul Tracking & Scientific
Imaging Data, GSM, 2.5G, Wireless LAN, SDH/PDH Communications SDH/PDH SATCOM Jamming Imaging &
(MRI) Toll Tags 3G Access Points Radio Links & Telemetry Radio Links Terminal Systems Measurement
Unmanned Military Automotive

CATV & RFID DVB, DBS, Consumer & Air Vehicle Radar & Adaptive
Cable Telematics Satellite Test Industrial Industrial (UAV) Counter- Cruise Fiber Optic
Modem GPS Radio Equipment Imaging VSAT Data Link Measures Control Communications
VISIBLE
RADIO FREQUENCY MICROWAVE MILLIMETERWAVE LIGHT
0 6 GHz 20 GHz 110 GHz
HMC646LP2E HMC463LH250 HMC338LC3B

0.1 – 2.1 GHz 24 - 34 GHz HMC-C010
2 – 20 GHz 6 – 15 GHz
HMC580ST89E HMC556
HMC576
DC – 1 GHz 36 - 41 GHz
18 - 29 GHz Fout
HMC479MP86E HMC-SDD112 HMC-AUH312

DC - 5 GHz HMC258LM3 55 - 86 GHz DC - 65 GHz
14 - 20 GHz
HMC311SC70E HMC547LP3E HMC-AUH320

DC – 8 GHz DC - 20 GHz 71 – 86 GHz
Complete Signal Chain Solution
Bits to Antenna and Back
Complete Signal Chain Solution
Rx Path
TX Path
Rx and/or Tx
LO Path
30MHz to 6GHz Band Solution
RF Design Tools
All RF & Synthesis Tools

• VRMS/dBm/dBu/dBV calculators
• A converter between units of power measurement and signal strength.
• RF Impedance Matching Calculator
• Calculates the network to match a line to a specific complex load.
• X-Microwave Partnership
• Simplify design-to-prototyping of RF & MW signal chain
• Adviser
• ADI’s ADIsimRF design tool provides calculations for the most important parameters within the RF signal chain,
including cascaded gain, noise figure, IP3, P1dB, and total power consumption.
• ADIsimPLL™
• ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most
comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-
linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the
design process, thereby speeding the design- to-market.
123
RF Design Tools (Continued)
• ADIsimSRD Design Studio

• Analog Devices ADIsimSRD Design Studio is a very powerful tool allowing real-time simulation and optimization of
many of the parameters in a typical wireless system using the ADF7xxx family of transceivers and transmitters.
• ADIsimCLK Design and Evaluation Software
• ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and
clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking,
broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly
develop, evaluate and optimize your design.
• ADIsimFrequency Planner Tool
• For those developers dealing with integer boundary spurs from Analog’s PLL synthesizers, the best solution is
ADIsimFrequencyPlanner. The frequency planner quickly analyzes the PFD frequency for a user’s output
requirements and then optimizes the frequency of each output to identify the highest contributing integer boundary
spur performance.
• ADIsimDDS (Direct Digital Synthesis) - BETA
• ADIsimDDS uses mathematical equations to model and illustrate the overall performance of the selected device.
ADIsimDDS calculates the required FTW, given the reference clock frequency and desired output frequency. This tool
also models an estimate of the overall spectral performance and allows the user to explore the effects of external
reconstruction filters.
124
Richardson RFPD Radio
Development Tools
125
RadioVerse™: Richardson RFPD Microsite
► Wideband Transceivers
▪ Product Overview/Video
▪ Product Page – Datasheet, Design file
packages
► Evaluation Tools and Dev Kits
▪ Evaluation Boards
▪ Development Platforms
▪ Programmable SoC Boards
► Collateral
▪ Selector Guides
▪ Brochures
▪ Demo Videos
Visit: http://apps.richardsonrfpd.com/mktg/Analog_Devices_RadioVerse.html
126
System Block Diagram of the SDR Development Kit
• DE705, 5 Watt Avg RF FEM
• AD9375, Wideband Transceiver with DPD
EVAL-TPG- • EVAL-TPG-ZYNQ3, Programmable SoC

ZYNQ3
The FPGA, RF Transceiver, and RFFE are the basic building blocks of the SDR system
A Modular SDR Development Kit
ADI-DPD-DEVKIT
• Capture platform, Transceiver, and RFFE boards represent the

three system blocks of the SDR
• Intuitive software enables SDR system operation with deep
edit capability
• Documentation provides rapid development out of the box,
and also guides through the configurations
• All but a handful of typical bench accessories are included
• Technical support is available from Richardson RFPD
What you can do with the ADI-DPD-DEVKIT
1. Follow the Quick-Start Guide to easily configure the kit within hours
– Minimum performance: 5W average, 790MHz / 763MHz, 20MHz BW, Single Carrier LTE, 7.5dB PAPR,
45% PA Efficiency, 52dBc ACLR
2. Once configured, enable a wide variety of system characteristics through the intuitive software
GUIs for controlling the transceiver and RFFE
– Single and Multicarrier configuration
– Up to 20MHz instantaneous bandwidth (with DPD)
– Power adjustment (1-5W avg @ antenna)
– Band adjustment (toggle between LTE Band 14 and 28 via interchangeable duplexers
– Balance linearity vs efficiency
Other Benefits
► See the benefits of moving the digital predistortion (DPD) algorithms from the FPGA to the
transceiver
What’s Next?
► RF Front End Card

► TDD-LTE, 3.5GHz
► 24dBm average, 2 x 2 MIMO
► Compatible with AD937x and ADRV9008/9 RF
Agile
► Expected release June 2019 TxRx
We welcome your inputs. What hardware would you like to see as our next development tool?
References
Helpful websites to bookmark

► www.analog.com
► www.analog.com/RadioVerse
► www.richardsonrfpd.com
► Apps.richardsonrfod.com/mktg/Analog Devices RadioVerse.html
Local Richardson RFPD support

► Vince Wright, Field Sales Engineer, (m) 443-856-9226, vwright@richardsonrfpd.com
• AD9361 (chip)
Thanks IIO Oscilloscope
• Hands on labs
QUESTIONS • Hands on labs
• Hands on labs
12:00 Lunch

Support and help
► Contact your MathWorks ► Advanced 2 day SDR

Support: sales representative, or visit Workshop with Analog
http://ez.analog.com mathworks.com/training
▪ ADALM-PLUTO
Devices and MathWorks
for a schedule of available
https://ez.analog.com/university-
classes: ▪ Deeper exploration of
program
▪ DSP for FPGAs (3 days) targeting workflows
▪ FPGA questions
https://ez.analog.com/fpga ▪ Generating HDL Code from ▪ Contact Cindi Spears
▪ Linux drivers & IIO & MATLAB Simulink (2 days)
► ADALM-PLUTO
https://ez.analog.com/linux-device- ▪ Embedded Linux and System
drivers/linux-software-drivers
Integration for Zynq (2 days) ▪ $149 (USD)
▪ NO-OS Drivers: ▪ Programming Xilinx Zynq ▪ Make great gift for the
https://ez.analog.com/linux-device-
drivers/microcontroller-no-os-drivers SoCs with MATLAB and holidays or any occasion
Simulink (2 days)
Documentation: ▪ Software-Defined Radio with
http://wiki.analog.com/plutosdr Zynq using Simulink (1 day)
http://www.analog.com/plutosdr

Hands-On Workshop: Software-Defined Radio: ©2018 Analog Devices, Inc. All Rights Reserved

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Hands-on Workshop:

©2018 Analog Devices, Inc. All rights reserved. 1

©2018 Analog Devices, Inc. All rights reserved.

► From console/DOS window type:

▪ Should find the PlutoSDR

3 ©2018 Analog Devices, Inc. All rights reserved.

► From MATLAB prompt type:

▪ <ret> indicates return key

4 ©2018 Analog Devices, Inc. All rights reserved.

▪ Get the lab zip file:

5 ©2018 Analog Devices, Inc. All rights reserved.

©2018 Analog Devices, Inc. All rights reserved. 6

©2018 Analog Devices, Inc. All rights reserved.

©2018 Analog Devices, Inc. All rights reserved.

Mark Vitellaro Vince Wright

Dr. Travis F. Collins Robin Getz

EngineerZone : travisfcollins Twitter : @robinlgetz

©2018 Analog Devices, Inc. All rights reserved.

Noam Levine Curie Chung

©2018 The MathWorks ,Inc. All rights reserved.

12 ©2018 Analog Devices, Inc. All rights reserved.

Global RF, Wireless, Industrial IoT, Energy & Power Expert

• Expert Team of RF Designers and Engineers

• Integrated Supply Chain and Global Logistic Centers

• 35 Sales Offices and Locations, 6 Engineering Centers

• Richardson RFPD, Inc. - Wholly Owned Subsidiary of Arrow Electronics

Acquired By Arrow Electronics

• Leading RF & Wireless

16 ©2018 Analog Devices, Inc. All rights reserved.

 Discrete single product evaluation boards,

 Not easy to replicate, or use as part of a

 Needed small form factor, open design

18 ©2018 Analog Devices, Inc. All rights reserved.

©2018 Analog Devices, Inc. All rights reserved.

Research Algorithm Design Prototype Production

• Behavioral • MATLAB • MATLAB • Deployment to • Deployment to

RFSoM+FMC Carrier or Eval FMC + FPGA Carrier

PackRF or RFSoM + Custom Carrieraaaaaaaaaaaaaaaaaaaaaaaaaaaa

©2018 Analog Devices, Inc. All rights reserved.

©2018 Analog Devices, Inc. All rights reserved.

From devices/chips: ► AD936x is the SDR standard for high

22 ©2018 Analog Devices, Inc. All rights reserved.

From devices/chips: To Products:

23 ©2018 Analog Devices, Inc. All rights reserved.

ADALM-PLUTO AD-FMCOMMS2 AD-FMCOMMS4 ARRADIO AD-FMCOMMS5 ADRV9371-N/PCBZ ADRV9375-N/PCBZ ADRV9008-1W/PCBZ (Rx)

ADRV9364-Z7020 PACKRF ADRV-DPD1 ADRV9009-ZU11EG

USB 2.0 OTG

©2018 Analog Devices, Inc. All rights reserved.

26 ©2018 Analog Devices, Inc. All rights reserved.

▪ Sin 0t is 90 out of phase with respect to cos 0t

©2018 Analog Devices, Inc. All rights reserved.

©2018 Analog Devices, Inc. All rights reserved.

FPGA Development System ADI FMC Card ADI RF System on Module

©2018 Analog Devices, Inc. All rights reserved.

31 ©2018 Analog Devices, Inc. All rights reserved.

Linux Mac Windows

©2018 Analog Devices, Inc. All rights reserved.

► Pluto enumerates four devices

33 ©2018 Analog Devices, Inc. All rights reserved.

► Automatic dependent surveillance—broadcast

► dump1090 is an open source application, to

► Three easy steps:

34 ©2018 Analog Devices, Inc. All rights reserved.