Intel: USB Board

5 4 3 2
ZQ1 BLOCK DIAGRAM GPU CORE PWR

MAX8792ETD P41
D DISCHARGER
P43
CLOCK GENERATOR Fan Driver
IDT: ICS9LVS3197BKLFT
BCLK: 133MHz
PEG_CLK: 100MHz
DPLL_REF_SSCLK: 120MHz
intel (PWM Type) +1.0V/+1.8V
X'TAL
14.318MHz P3
<MCH Processor> P34 TPS54418RTE P43
CPU VGFX_AXG
DDR SYSTEM MEMORY

CPU ISL62881 P42
Dual Channel Arrandale (SG)
DDR III XDP Conn.
800/ 1066 MHz P16
SO-DIMM 0 THERMAL
SO-DIMM 1 800 MT/s 1066 MT/s PROTECTION P46
P14, 15 rPGA 989
(37.5mm X 37.5mm)
PCI-E PCIE
X16 CRT
ATI GPU LVDS C
FDI DMI P4~P7 2.5GT/s LVDS_CRT
Madison/Park LP/PRO
HDD (SATA) 1GB (16 x 64Mb x 8pcs) INT_CRT Switchable
C
P29 INT_LVDS L
FDI interface X4 DMI interface P17~P24 P25
X'TAL
ODD (SATA) SATA0 FDI DMI
27.0MHz
Graphics Interfaces
P29 INT_CRT HDMI
USB board SATA1 intel INT_LVDS
<PCH> HDMI H
INT_HDMI
Level-shift
USB Port X3 SATA PS8101 P26
USB 3 3.0 GT/s
USB 2.0 Ibex Peak_M RTC X'TAL
USB 9 32.768KHz
USB 11 P32
PCI-E
PCI-Express
USB 2.5GT/s
USB Port x 1
USB 1 PCIE-1 PCIE-6
(Debug)
P32
CLKOUT_PEG_B CLKOUT_PEG_2
B
mBGA 676
(27mm X 25mm)
Bluetooth Atheros Mini Card M
USB 4 P32
Azalia HDA Giga-LAN
WiFi 3G
P8~P13 AR8151 P27 USB 13 P28 US
SPI LPC X'TAL USB10
CCD 25MHz
USB 8 P25
Transformer SI
P27
CardReader SPI ROM
4MB x1 (Basic ME+BIOS) C
AU6437 Audio CODEC P9
EC da
USB 12 P31 RJ45
RTL ALC271X
(NPCE781/783) P27
Note: P35
HM55 does not support USB 6 & 7 P30
X'TAL
HM55 does not support SATA 2 & 3 32.768KHz
SPDIF/HP INT MIC DMIC P33

SPI ROM Touch Pad Keyboard Button on
3G@ FOR 3G SKU P30 P30 P25 P35 P32 P34 mechanical key Quan
PK@ FOR PARK GPU
MD@ FOR MADSION GPU PROJE
IV@ FOR UMA Size Document Number
SW@ FOR SWITCHABLE GRAPHIC
Block
Date: Wednesday, February 03, 2010
5 4 3 2
1
CHARGER
1 ISL88731 P44
3/5V SYS PWR

RT8206 P36
CPU CORE PWR D
3 ISL62882 P37
ARD: 1.05V
CPU VTT CFD: 1.1V
3 UP61111AQDD P38
VTT 1.05V
2 UP61111AQDD P39
DDR3 PWR
6 RT8207A P40
CRT P25
LVDS P25 C
HDMI P26
PCIE-2
CLKOUT_PEG_1
B
Mini Card
3G
USB 10 P28
USB13
SIM Card FFC

Conn P28
daughter board
USB5
uanta Computer Inc.

OJECT : ZQ1
Rev
1A
ock Diagram
010 Sheet 1 of 48
1
1 2 3 4 5 6 7
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

+3.3V VIN +1.5V +1.5V_SUS +1.8V +5V
VDDR3 +3V_D VDDC PG_GPUIO_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 +1.8V_GPU BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MOS (AO3413) MAX8792ETD TPS54418RTE RT8207A MOS (AO6402) AO3413
P20 P41 P43 P40 P43 P20 P36
A
+3_D (0.15A) +VGPU_CORE (22.5A) +1V (2A) +1.5V_GPU (7.5A) +1.8V_GPU (1.9A) +5_GPU (0.75A)
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V
VDDC PG_GPUIO_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 +1.8V_GPU BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MAX8792ETD TPS54418RTE RT8207A MOS (AO3413) MOS (AO6402) AO3413
P41 P43 P40 P20 P43 P20 P36
+VGPU_CORE (22.5A) +1V (2A) +1.5V_GPU (7.5A) +3_D (0.15A) +1.8V_GPU (1.9A) +5_GPU (0.75A)
B
Power States Thermal Follow Chart

CONTROL
POWER PLANE VOLTAGE DESCRIPTION SIGNAL ACTIVE IN
VIN +10V~+19V MAIN POWER S0~S5
+VCCRTC +3V~+3.3V RTC S0~S5 NTC

+3VPCU +3.3V 8051 POWER ALWON S0~S5 Thermal
Protection
+5VPCU +5V CHARGE POWER ALWON S0~S5
+15V +15V LARGE POWER +15V_ALWP S0~S5
+5V_S5 +5V S5D S0~S5

CPU H_ORICHOT# PM_THRMTRIP# SYS_SHDN# 3V/5 V
+3V_S5 +3.3V S5D S0~S5
CORE PWR H/W Throttling
CPU WIRE-AND SYS PWR
C
+3VSUS +3.3V SUSD S0, S3
+1.5V_SUS +1.5V SODIMM POWER SUSON S0, S3
+0.75V_DDR_VTT +0.9V SODIMM POWER MAINON S0 SML1ALERT#
+5V +5V MAIND S0 PCH FAN Driver FAN

+3V +3.3V MAIND S0
+1.8V +1.8V MAINON S0 SM-Bus
+1.5V +1.5V PCH POWER MAIND S0
+1.1V_VTT +1.05V~+1.1V CPU POWER MAINON S0 EC

CPUFAN#
+1.05V +1.05V PCH POWER MAINON S0
+VCC_CORE 0V~+1.5V CPU CORE POWER VRON S0

D
LCDVCC +3.3V LCD Power LVDS_VDDEN S0
MBAT+ +10V~+17V MAIN BATTERY

Q
P
Size Document Number
PWR Status &
Date: Monday, February 01, 20
1 2 3 4 5 6 7
8
A)
A)
B
R C
Quanta Computer Inc.

PROJECT : ZQ1
r Rev
1A
us & GPU PWR CRL & THRM
01, 2010 Sheet 2 of 48
8
5 4 3 2
CLK Gen(CLK) pi-filter

close PIN 1 close PIN 1, 17, 24 each U38 pi-filte
150mA(30mil)
+1.5V L54 595@BLM18AG601SN1D/200mA/600ohm_6 +1.5V_CLK 1 80mA(20mil)
VDD_DOT +VDDIO_CLK L58
17 VDD_SRC VDD_SRC_I/O 15
C746 C752 C758 C467 C789 24 18 BLM18AG601S
VDD_CPU VDD_CPU_I/O C790 C786 C794
D 5 VDD_27
*0.1u/10V_4 R551 *585@0_6 *10u/6.3V_8 0.1u/10V_4 29 3
VDD_REF DOT_96 CLK_BUF_DREFCLK (10)
0.1u/10V_4 0.1u/10V_4 4 0.1u/10V_4 0.1u/10V_4 10u/6.3V_8
9/22 modify DOT_96# CLK_BUF_DREFCLK# (10)
pi-filter CLK_SDATA 31
CLK_SCLK SDA R300 *SW@33_4 Place each 0.1uF cap as close a
20mil 32 SCL 27M 6 27M_CLK (18)
+3V L57 BLM18AG601SN1D/200mA/600ohm_6 +3V_CLK 7 R301 *SW@0_4 possible to each VDD IO pin. Pl
27M_SS D3D
the 10uF caps on the VDD_IO pla
C792 R554 33_4 CPU_SEL 30 10
(10) CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_PCIE_3GPLL (10)
C754 C466 C757 11
SRC_1#/SATA# CLK_BUF_PCIE_3GPLL# (10)
*0.1u/10V_4 C772 27p/50V_4 13
SRC_2 CLK_BUF_DREFSSCLK (10)
10u/6.3V_8 0.1u/10V_4 0.1u/10V_4 14
SRC_2# CLK_BUF_DREFSSCLK# (10)
1
XTAL_IN 28
B-test Y6 XTAL_IN +3V
14.318MHZ XTAL_OUT 27 16 R579 10K_4
close bead close PIN 5, 29 each XTAL_OUT *CPU_STOP#
2
C782 33p/50V_4 2 20
VSS_DOT CPU_1 TP46
8 VSS_27 CPU_1# 19 TP45
C 9 VSS_SATA CPU_0 23 CLK_BUF_BCLK (10)
12 VSS_SRC CPU_0# 22 CLK_BUF_BCLK# (10)
IDT: AL003197002 (ICS9LVS3197BKLFT) 21 VSS_CPU CK_PWRGD_R
26 25
Realtek: AL000890000 (RTM890N-632-GRT) 33
VSS_REF CKPW RGD/PD#
GND
Silego: AL000595000 (SLG8LV595VTR)
ICS9LVS3197BKLFT
+3V +3V CRB use

CPU_CLK select(CLK) SMBus(CLK)
CLK Enable(CLK)
+1.05V
R584
R563 1K_4
B
2
R555 4.7K_4
*4.7K_4 CK_PWRGD_R
3 1 CLK_SDATA
(10,16,28) ICH_SMBDATA CLK_SDATA (14,15,28)
3
Q37
CPU_SEL Q33 2N7002K
2N7002K
(37) VR_PWRGD_CK505# 2 R580
R564 100K_4
4.7K_4 +3V
1
R558
2
4.7K_4
0 1
A
(10,16,28) ICH_SMBCLK 3 1 CLK_SCLK
CLK_SCLK (14,15,28) Quanta
CPU_SEL CPU0/1=133MHz CPU0/1=100MHz Q35
(default) 2N7002K PROJECT
Clock Generator
Date: Tuesday, March 30, 2010
5 4 3 2
1
-filter
+1.05V
G601SN1D/200mA/600ohm_6
C802 D
_8 *0.1u/10V_4
se as
. Place
plane.
se +3VPCU
D_R
80
0K_4
nta Computer Inc. A
ECT : ZQ1
Rev
1A
Sheet 3 of 48
1
5 4 3 2
Arrandale_1(CPU) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JT
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) Processor Compensation Signals

U28A U28B
B26 PEG_COMP R415 49.9/F_4 R490 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3
PEG_ICOMPO A26 BCLK A16 CLK_CPU_BCLK
MISC
A24 B27 R491 20/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLK#
(8) DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK#
C23 A25 PEG_RBIAS R414 750/F_4
(8) DMI_TXN1 DMI_RX#[1] PEG_RBIAS
B22 R148 49.9/F_4 H_COMP1 G16 AR30
CLOCKS
(8) DMI_TXN2 DMI_RX#[2] PEG_RXN[0..15] (17) COMP1 BCLK_ITP BCLK_ITP_P (16
A21 K35 PEG_RXN0 AT30 BCLK_ITP_N (16
D (8) DMI_TXN3 DMI_RX#[3] PEG_RX#[0] BCLK_ITP#
J34 PEG_RXN1 R492 49.9/F_4 H_COMP0 AT26
PEG_RX#[1] PEG_RXN2 COMP0
(8) DMI_TXP0 B24 J33 E16 CLK_PCIE_3GPLL
DMI_RX[0] PEG_RX#[2] PEG_RXN3 PEG_CLK
(8) DMI_TXP1 D23 DMI_RX[1] PEG_RX#[3] G35 PEG_CLK# D16 CLK_PCIE_3GPLL
DMI
B23 G32 PEG_RXN4 AH24
(8) DMI_TXP2 DMI_RX[2] PEG_RX#[4] SKTOCC#
A22 F34 PEG_RXN5 A18 DPLL_REF_SSCLK
(8) DMI_TXP3 DMI_RX[3] PEG_RX#[5] DPLL_REF_SSCLK
F31 PEG_RXN6 A17 DPLL_REF_SSCLK
PEG_RX#[6] PEG_RXN7 H_CATERR# DPLL_REF_SSCLK#
D24 D35 AK14
(8) DMI_RXN0 DMI_TX#[0] PEG_RX#[7] Use RVS type CATERR#
THERMAL
G24 E33 PEG_RXN8
(8) DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
F23 C33 PEG_RXN9
(8) DMI_RXN2 DMI_TX#[2] PEG_RX#[9]
H23 D32 PEG_RXN10 F6 CPU_DDR
(8) DMI_RXN3 DMI_TX#[3] PEG_RX#[10] SM_DRAMRST#
B32 PEG_RXN11 AT15
PEG_RX#[11] (11) H_PECI PECI
D25 C31 PEG_RXN12 AL1 SM_RCOMP_0 R183 100/F_4
(8) DMI_RXP0 DMI_TX[0] PEG_RX#[12] SM_RCOMP[0]
F24 B28 PEG_RXN13 AM1 SM_RCOMP_1 R187 24.9/F_4
E23 B30 PEG_RXN14 AN1 SM_RCOMP_2 R192 130/F_4
G23 A31 PEG_RXN15 (37) H_PROCHOT# R493 *Short_4 H_PROCHOT#_R AN26
(8) DMI_RXP3 DMI_TX[3] PEG_RX#[15] PROCHOT#
PEG_RXP[0..15] (17) AN15 R489 *Short_4
PM_EXT_TS#[0]
DDR3
MISC
J35 PEG_RXP0 AP15 R488 10K_4
PEG_RX[0] PEG_RXP1 PM_EXT_TS#[1] R487 10K_4
H34
PEG_RX[1] PEG_RXP2 PM_THRMTRIP# R205 *Short_4 PM_THRMTRIP#_R AK15 R486 *Short_4
H33
PEG_RX[2] PEG_RXP3 THERMTRIP#
(8) FDI_TXN0 E22 F35
FDI_TX#[0] PEG_RX[3] PEG_RXP4 B-test
(8) FDI_TXN1 D21 FDI_TX#[1] PEG_RX[4] G33
D19 E34 PEG_RXP5 AT28 XDP_PRDY
(8) FDI_TXN2 FDI_TX#[2] PEG_RX[5] PRDY#
D18 F32 PEG_RXP6 B-test AP27 XDP_PREQ# XDP_PREQ
(8) FDI_TXN3 FDI_TX#[3] PEG_RX[6] PREQ#
G21 D34 PEG_RXP7
(8) FDI_TXN4 FDI_TX#[4] PEG_RX[7]
PCI EXPRESS -- GRAPHICS
E19 F33 PEG_RXP8 AN28 XDP_TCLK XDP_TCLK
(8) FDI_TXN5 FDI_TX#[5] PEG_RX[8] TCK
F21 B33 PEG_RXP9 (16) H_CPURST# AP26 AP28 XDP_TMS XDP_TMS
(8) FDI_TXN6 FDI_TX#[6] PEG_RX[9] RESET_OBS# TMS
Intel(R) FDI
PWR MANAGEMENT
G18 D31 PEG_RXP10 AT27 XDP_TRST# XDP_TRST
(8) FDI_TXN7 FDI_TX#[7] PEG_RX[10] TRST#
A32 PEG_RXP11
JTAG & BPM

PEG_RX[11] PEG_RXP12 R204 *Short_4 H_PM_SYNC_R XDP_TDI_R
PEG_RX[12] C30 (8) PM_SYNC AL15 PM_SYNC TDI AT29
D22 A28 PEG_RXP13 AR27 XDP_TDO_R
(8) FDI_TXP0 FDI_TX[0] PEG_RX[13] TDO
C21 B29 PEG_RXP14 PEG_TXN[0..15] (17) AR29 XDP_TDI_M
(8) FDI_TXP1 FDI_TX[1] PEG_RX[14] TDI_M
D20 A30 PEG_RXP15 AN14 AP29 XDP_TDO_M
(8) FDI_TXP2 FDI_TX[2] PEG_RX[15] VCCPWRGOOD_1 TDO_M
(8) FDI_TXP3 C18
FDI_TX[3] CPEG_TXN0 C595 SW@0.1u/10V_4 PEG_TXN0 H_DBR#_R R188 *Short_4
(8) FDI_TXP4 G22 L33 AN25
C FDI_TX[4] PEG_TX#[0] CPEG_TXN1 C568 SW@0.1u/10V_4 PEG_TXN1 R156 *Short_4 DBR#
(8) FDI_TXP5 E20 M35 (11,16) H_PWRGOOD AN27
FDI_TX[5] PEG_TX#[1] CPEG_TXN2 C593 SW@0.1u/10V_4 PEG_TXN2 VCCPWRGOOD_0
(8) FDI_TXP6 F20 FDI_TX[6] PEG_TX#[2] M33
G19 M30 CPEG_TXN3 C566 SW@0.1u/10V_4 PEG_TXN3 AJ22 XDP_OBS0
(8) FDI_TXP7 FDI_TX[7] PEG_TX#[3] BPM#[0]
L31 CPEG_TXN4 C591 SW@0.1u/10V_4 PEG_TXN4 AK13 AK22 XDP_OBS1
PEG_TX#[4] (16) PM_DRAM_PWRGD_R SM_DRAMPWROK BPM#[1]
F17 K32 CPEG_TXN5 C564 SW@0.1u/10V_4 PEG_TXN5 AK24 XDP_OBS2
(8) FDI_FSYNC0 FDI_FSYNC[0] PEG_TX#[5] BPM#[2]
E17 M29 CPEG_TXN6 C589 SW@0.1u/10V_4 PEG_TXN6 AJ24 XDP_OBS3
(8) FDI_FSYNC1 FDI_FSYNC[1] PEG_TX#[6] BPM#[3]
J31 CPEG_TXN7 C562 SW@0.1u/10V_4 PEG_TXN7 H_VTTPWRGD AM15 AJ25 XDP_OBS4
PEG_TX#[7] CPEG_TXN8 C587 SW@0.1u/10V_4 PEG_TXN8 VTTPWRGOOD BPM#[4] XDP_OBS5
(8) FDI_INT C17 FDI_INT PEG_TX#[8] K29 BPM#[5] AH22
H30 CPEG_TXN9 C560 SW@0.1u/10V_4 PEG_TXN9 AK23 XDP_OBS6
PEG_TX#[9] CPEG_TXN10 C585 SW@0.1u/10V_4 PEG_TXN10 BPM#[6] XDP_OBS7
(8) FDI_LSYNC0 F18 H29 (16) H_PWRGD_XDP AM26 AH23
FDI_LSYNC[0] PEG_TX#[10] CPEG_TXN11 C558 SW@0.1u/10V_4 PEG_TXN11 TAPPWRGOOD BPM#[7]
(8) FDI_LSYNC1 D17 FDI_LSYNC[1] PEG_TX#[11] F29
E28 CPEG_TXN12 C583 SW@0.1u/10V_4 PEG_TXN12
PEG_TX#[12] CPEG_TXN13 C556 SW@0.1u/10V_4 PEG_TXN13 R177 1.5K/F_4 CPU_PLTRST#
D29 (10,11,27,28,31,35) PLTRST# AL14
PEG_TX#[13] CPEG_TXN14 C581 SW@0.1u/10V_4 PEG_TXN14 RSTIN#
D27 PEG_TXP[0..15] (17)
PEG_TX#[14] CPEG_TXN15 C554 SW@0.1u/10V_4 PEG_TXN15 R176
C26
PEG_TX#[15] 750/F_4
L34 CPEG_TXP0 C594 SW@0.1u/10V_4 PEG_TXP0 Clarksfield/Auburndale
PEG_TX[0] CPEG_TXP1 C567 SW@0.1u/10V_4 PEG_TXP1
PEG_TX[1] M34 SI 2/5 Modified
M32 CPEG_TXP2 C592 SW@0.1u/10V_4 PEG_TXP2
PEG_TX[3] L30
M31 CPEG_TXP4 C590 SW@0.1u/10V_4 PEG_TXP4 STD
K31
PEG_TX[6] M28
H31 CPEG_TXP7 C561 SW@0.1u/10V_4 PEG_TXP7 FOX DGG
K28
PEG_TX[9] G30
G29 CPEG_TXP10 C584 SW@0.1u/10V_4 PEG_TXP10 LTS DGG
F28
E27
PEG_TX[13] D28 SUY
C27 CPEG_TXP14 C580 SW@0.1u/10V_4 PEG_TXP14
C25
PEG_TX[15]
MLX
B
Clarksfield/Auburndale Standard: rpga
Reverse: PZ989
Thermaltrip protect(CPU) VTT PWR_Good(CPU) Processor pull-up(CPU) JTAG MAPPING(CP

XDP_TDI_R
R168
+1.1V_VTT XDP_TDO_M
+1.1V_VTT R175
H_CATERR# R162 49.9/F_4
H_PROCHOT#_R R494 68_4 R174
H_CPURST# R160 *68_4
3
XDP_TMS R165 *51_4 *0_4

XDP_TDI_R R167 *51_4
+3V XDP_PREQ# R166 *51_4 XDP_TDI_M
2 Q13 XDP_TCLK R181 *51_4 R171
(8,37) DELAY_VR_PWRGOOD
XDP_TRST# R164 51/F_4 XDP_TDO_R
FDV301N R178
C348
1
0.1u/10V_4 4/9 REV:B MODIFY BY DG1.52

Scan Chain STUFF
5
R209 (Default) NO ST
1K_4 2 R195 +1.5V_CPUVDDQ
(35) MPWROK
4 H_VTTPWRGD
1 CPU Only STUFF
2K/F_4 If S3 leakage circuit is realized, the NO ST
U17 R169
PU and PD resistors must be un-staff.
3
2
A R196 1.1K/F_4
Q14 TC7SH08FU 1K_4 GMCH Only STUFF
(11) PM_THRMTRIP#
PM_THRMTRIP# 1 3 MMBT3904 SYS_SHDN# (36,46)
PM_DRAM_PWRGD_R NO ST
R170 Use a voltage divider with VDDQ
pull-up 56ohm close to PCH 3K/F_4 (1.5V) rail (ON in S3) and
resistor combination of 4.75K (to
VDDQ)/12K(to GND) to generate the
required voltage.
Note: CRB uses a 3.3V (always ON)
rail with 2K and 1K combination.
Size Document Numb
AUBURND
Date: Tuesday, March 3
5 4 3 2
1
,JTAG)
_BCLK (11)
_BCLK# (11)
_P (16)
_N (16) D
_3GPLL (10)
_3GPLL# (10)
F_SSCLK (10)
F_SSCLK# (10)
U_DDR3_DRAMRST# (16)
100/F_4
24.9/F_4
130/F_4
hort_4 PM_EXTTS#0 (14)

10K_4
10K_4 +1.1V_VTT
hort_4 PM_EXTTS#1 (15)
P_PRDY# (16)
P_PREQ# (16)
P_TCLK (16)
P_TMS (16)
P_TRST# (16)
C3C
hort_4 XDP_DBRST# (8,16) C
XDP_OBS[0:7] (16)
STD
DGG^9000024
DGG^9000022
B
rpga989-aca-zif-069-k01-socket
PZ98927-364R-01F-SOCKET
G(CPU)
XDP_TDI (16)
68 *0_4
XDP_TDO (16)
75 *0_4
71 *0_4
78 *0_4
STUFF -> R469, R491, R507

NO STUFF -> R489, R490
STUFF -> R490, R491

NO STUFF -> R469, R489, R507
A
STUFF -> R489, R507
NO STUFF -> R491, R490, R469

PROJECT : ZQ1
nt Number Rev
1A
URNDA 1/4
March 30, 2010 Sheet 4 of 48
1
5 4 3 2 1
Arrandale_2(CPU)
AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3) U28D
U28C
(15) M_B_DQ[63:0] SB_CK[0] W8 M_B_CLK0 (15)

W9 M_B_CLK0# (15)
M_B_DQ0 SB_CK#[0]
B5 M3 M_B_CKE0 (15)
M_B_DQ1 SB_DQ[0] SB_CKE[0]
A5
M_B_DQ2 SB_DQ[1]
AA6 M_A_CLK0 (14) C3
SA_CK[0] M_B_DQ3 SB_DQ[2]
AA7 M_A_CLK0# (14) B3 V7 M_B_CLK1 (15)
SA_CK#[0] M_B_DQ4 SB_DQ[3] SB_CK[1]
(14) M_A_DQ[63:0] SA_CKE[0] P7 M_A_CKE0 (14) E4 SB_DQ[4] SB_CK#[1] V6 M_B_CLK1# (15)
D M_A_DQ0 A10 M_B_DQ5 A6 M2
SA_DQ[0] SB_DQ[5] SB_CKE[1] M_B_CKE1 (15)
M_A_DQ1 C10 M_B_DQ6 A4
M_A_DQ2 SA_DQ[1] M_B_DQ7 SB_DQ[6]
C7 SA_DQ[2] C4 SB_DQ[7]
M_A_DQ3 A7 Y6 M_A_CLK1 (14) M_B_DQ8 D1
M_A_DQ4 SA_DQ[3] SA_CK[1] M_B_DQ9 SB_DQ[8]
B10 SA_DQ[4] SA_CK#[1] Y5 M_A_CLK1# (14) D2 SB_DQ[9]
M_A_DQ5 D10 P6 M_A_CKE1 (14) M_B_DQ10 F2 AB8 M_B_CS#0 (15)
M_A_DQ6 SA_DQ[5] SA_CKE[1] M_B_DQ11 SB_DQ[10] SB_CS#[0]
E10 SA_DQ[6] F1 SB_DQ[11] SB_CS#[1] AD6 M_B_CS#1 (15)
M_A_DQ7 A8 M_B_DQ12 C2
D8 F5
F10 AE2 M_A_CS#0 (14) F3
M_A_DQ10 SA_DQ[9] SA_CS#[0] M_B_DQ15 SB_DQ[14]
E6 AE8 M_A_CS#1 (14) G4 AC7 M_B_ODT0 (15)
M_A_DQ11 SA_DQ[10] SA_CS#[1] M_B_DQ16 SB_DQ[15] SB_ODT[0]
F7 H6 AD1 M_B_ODT1 (15)
M_A_DQ12 SA_DQ[11] M_B_DQ17 SB_DQ[16] SB_ODT[1]
E9 SA_DQ[12] G2 SB_DQ[17]
M_A_DQ13 B7 M_B_DQ18 J6
E7 SA_DQ[14] SA_ODT[0] AD8 M_A_ODT0 (14) J3 SB_DQ[19]
M_A_DQ15 C6 AF9 M_A_ODT1 (14) M_B_DQ20 G1 M_B_DM[7:0] (1
M_A_DQ16 SA_DQ[15] SA_ODT[1] M_B_DQ21 SB_DQ[20] M_B_DM0
H10 SA_DQ[16] G5 SB_DQ[21] SB_DM[0] D4
M_A_DQ17 G8 M_B_DQ22 J2 E1 M_B_DM1
M_A_DQ18 SA_DQ[17] M_B_DQ23 SB_DQ[22] SB_DM[1] M_B_DM2
K7 SA_DQ[18] J1 SB_DQ[23] SB_DM[2] H3
M_A_DQ19 J8 M_B_DQ24 J5 K1 M_B_DM3
G7 K2 AH1
G10 M_A_DM[7:0] (14) L3 AL2
M_A_DQ22 SA_DQ[21] M_A_DM0 M_B_DQ27 SB_DQ[26] SB_DM[5] M_B_DM6
J7 B9 M1 AR4
M_A_DQ23 SA_DQ[22] SA_DM[0] M_A_DM1 M_B_DQ28 SB_DQ[27] SB_DM[6] M_B_DM7
J10 D7 K5 AT8
M_A_DQ24 SA_DQ[23] SA_DM[1] M_A_DM2 M_B_DQ29 SB_DQ[28] SB_DM[7]
L7 SA_DQ[24] SA_DM[2] H7 K4 SB_DQ[29]
M_A_DQ25 M6 M7 M_A_DM3 M_B_DQ30 M4
M_A_DQ26 SA_DQ[25] SA_DM[3] M_A_DM4 M_B_DQ31 SB_DQ[30]
M8 SA_DQ[26] SA_DM[4] AG6 N5 SB_DQ[31]
M_A_DQ27 L9 AM7 M_A_DM5 M_B_DQ32 AF3
M_A_DQ28 SA_DQ[27] SA_DM[5] M_A_DM6 M_B_DQ33 SB_DQ[32]
L6 SA_DQ[28] SA_DM[6] AN10 AG1 SB_DQ[33] M_B_DQS#[7:0]
M_A_DQ29 K8 AN13 M_A_DM7 M_B_DQ34 AJ3 D5 M_B_DQS#0
M_A_DQ30 SA_DQ[29] SA_DM[7] M_B_DQ35 SB_DQ[34] SB_DQS#[0] M_B_DQS#1
N8 SA_DQ[30] AK1 SB_DQ[35] SB_DQS#[1] F4
M_A_DQ31 P9 M_B_DQ36 AG4 J4 M_B_DQS#2
C M_A_DQ32 SA_DQ[31] M_B_DQ37 SB_DQ[36] SB_DQS#[2] M_B_DQS#3
AH5 AG3 L4
M_A_DQ33 SA_DQ[32] M_B_DQ38 SB_DQ[37] SB_DQS#[3] M_B_DQS#4
AF5 M_A_DQS#[7:0] (14) AJ4 AH2
SA_DQ[33] SB_DQ[38] SB_DQS#[4]
DDR SYSTEM MEMORY - B

M_A_DQ34 AK6 C9 M_A_DQS#0 M_B_DQ39 AH4 AL4 M_B_DQS#5
SA_DQ[34] SA_DQS#[0] SB_DQ[39] SB_DQS#[5]
DDR SYSTEM MEMORY A
M_A_DQ35 AK7 F8 M_A_DQS#1 M_B_DQ40 AK3 AR5 M_B_DQS#6

M_A_DQ36 SA_DQ[35] SA_DQS#[1] M_A_DQS#2 M_B_DQ41 SB_DQ[40] SB_DQS#[6] M_B_DQS#7
AF6 J9 AK4 AR8
M_A_DQ37 SA_DQ[36] SA_DQS#[2] M_A_DQS#3 M_B_DQ42 SB_DQ[41] SB_DQS#[7]
AG5 SA_DQ[37] SA_DQS#[3] N9 AM6 SB_DQ[42]
M_A_DQ38 AJ7 AH7 M_A_DQS#4 M_B_DQ43 AN2
M_A_DQ39 SA_DQ[38] SA_DQS#[4] M_A_DQS#5 M_B_DQ44 SB_DQ[43]
AJ6 SA_DQ[39] SA_DQS#[5] AK9 AK5 SB_DQ[44]
M_A_DQ40 AJ10 AP11 M_A_DQS#6 M_B_DQ45 AK2
M_A_DQ41 SA_DQ[40] SA_DQS#[6] M_A_DQS#7 M_B_DQ46 SB_DQ[45]
AJ9 SA_DQ[41] SA_DQS#[7] AT13 AM4 SB_DQ[46]
M_A_DQ42 AL10 M_B_DQ47 AM3
SA_DQ[42] SB_DQ[47] M_B_DQS[7:0] (1
M_A_DQ43 AK12 M_B_DQ48 AP3 C5 M_B_DQS0
M_A_DQ44 SA_DQ[43] M_B_DQ49 SB_DQ[48] SB_DQS[0] M_B_DQS1
AK8 AN5 E3
M_A_DQ45 SA_DQ[44] M_B_DQ50 SB_DQ[49] SB_DQS[1] M_B_DQS2
AL7 M_A_DQS[7:0] (14) AT4 H4
M_A_DQ46 SA_DQ[45] M_A_DQS0 M_B_DQ51 SB_DQ[50] SB_DQS[2] M_B_DQS3
AK11 C8 AN6 M5
M_A_DQ47 SA_DQ[46] SA_DQS[0] M_A_DQS1 M_B_DQ52 SB_DQ[51] SB_DQS[3] M_B_DQS4
AL8 F9 AN4 AG2
AN8 H9 AN3 AL5
AM10 SA_DQ[49] SA_DQS[3] M9 AT5 SB_DQ[54] SB_DQS[6] AP5
M_A_DQ50 AR11 AH8 M_A_DQS4 M_B_DQ55 AT6 AR7 M_B_DQS7
M_A_DQ51 SA_DQ[50] SA_DQS[4] M_A_DQS5 M_B_DQ56 SB_DQ[55] SB_DQS[7]
AL11 AK10 AN7
M_A_DQ52 SA_DQ[51] SA_DQS[5] M_A_DQS6 M_B_DQ57 SB_DQ[56]
AM9 SA_DQ[52] SA_DQS[6] AN11 AP6 SB_DQ[57]
M_A_DQ53 AN9 AR13 M_A_DQS7 M_B_DQ58 AP8
M_A_DQ54 SA_DQ[53] SA_DQS[7] M_B_DQ59 SB_DQ[58]
AT11 AT9
AP12 AT7
AM12 AP9
AN12 M_A_A[15:0] (14) AR10 M_B_A[15:0] (1
M_A_DQ58 SA_DQ[57] M_A_A0 M_B_DQ63 SB_DQ[62] M_B_A0
AM13 Y3 AT10 U5
M_A_DQ59 SA_DQ[58] SA_MA[0] M_A_A1 SB_DQ[63] SB_MA[0] M_B_A1
AT14 W1 V2
M_A_DQ60 SA_DQ[59] SA_MA[1] M_A_A2 SB_MA[1] M_B_A2
AT12 AA8 T5
AL13 AA3 V3
AR14 V1 R1
AP14 AA9 (15) M_B_BS#0 AB1 T8
B SA_DQ[63] SA_MA[5] M_A_A6 SB_BS[0] SB_MA[5] M_B_A6
SA_MA[6] V8 (15) M_B_BS#1 W5 SB_BS[1] SB_MA[6] R2
T1 M_A_A7 (15) M_B_BS#2 R7 R6 M_B_A7
SA_MA[7] M_A_A8 SB_BS[2] SB_MA[7] M_B_A8
SA_MA[8] Y9 SB_MA[8] R4
(14) M_A_BS#0 AC3 U6 M_A_A9 R5 M_B_A9
SA_BS[0] SA_MA[9] M_A_A10 SB_MA[9] M_B_A10
(14) M_A_BS#1 AB2 AD4 (15) M_B_CAS# AC5 AB5
SA_BS[1] SA_MA[10] M_A_A11 SB_CAS# SB_MA[10] M_B_A11
(14) M_A_BS#2 U7 T2 (15) M_B_RAS# Y7 P3
SA_BS[2] SA_MA[11] M_A_A12 SB_RAS# SB_MA[11] M_B_A12
U3 (15) M_B_WE# AC6 R3
SA_MA[12] M_A_A13 SB_WE# SB_MA[12] M_B_A13
AG8 AF7
SA_MA[13] M_A_A14 SB_MA[13] M_B_A14
T3 P5
SA_MA[14] M_A_A15 SB_MA[14] M_B_A15
(14) M_A_CAS# AE1 V9 N1
SA_CAS# SA_MA[15] SB_MA[15]
(14) M_A_RAS# AB3
SA_RAS#
(14) M_A_WE# AE9
SA_WE#
Clarksfield/Auburndale Clarksfield/Auburndale
Channel A DQ[15,32,48,54], DM[5] Channel B DQ[16,18,36,42,56,57,60,61,62]

Requires minimum 12mils spacing Requires minimum 12mils spacing
with all other signals, including data signals. with all other signals, including data signals.
Quanta Computer In
PROJECT : ZQ1
AUBURNDA 2/4
Date: Tuesday, March 30, 2010 Sheet 5 of 48
5 4 3 2 1
D
7:0] (15)
[7:0] (15)
7:0] (15)
:0] (15)
r Inc.
Rev
1A
48
5 4 3 2
Arrandale_3(CPU)
CPU Core Power U28F
VTT Rail Values are

AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)
+VCC_CORE Auburndal VTT=1.05V
ARD:48A
18A U28G
AG35 AH14 +1.1V_VTT
VCC1 VTT0_1
AG34 AH12
AG33
VCC2 VTT0_2
AH11 +VGFX_AXG
22A AT21
+ C322 + C281 + C262 + C304 VCC3 VTT0_3 C307 C298 C629 + C248 VAXG1
AG32 VCC4 VTT0_4 AH10 AT19 VAXG2 VAXG_SENSE AR22 VCC_AXG_S
D 22u/6.3V_8 22u/6.3V_8
SENSE
LINES
AG31 J14 AT18 AT22 VSS_AXG_S
*330u/2V_7343 330u/2V_7343 *330u/2V_7343 330u/2V_7343 VCC5 VTT0_5 22u/6.3V_8 330u/2V_7343 + + VAXG3 VSSAXG_SENSE
AG30 VCC6 VTT0_6 J13 AT16 VAXG4
AG29 H14 C682 C681 AR21
VCC7 VTT0_7 330u/2V_7343 330u/2V_7343 VAXG5
AG28 H12 AR19
VCC8 VTT0_8 VAXG6
AG27 VCC9 VTT0_9 G14 AR18 VAXG7
AG26 G13 AR16 AM22 GFX_VID0
VCC10 VTT0_10 VAXG8 GFX_VID[0]
AF35 VCC11 VTT0_11 G12 AP21 VAXG9 GFX_VID[1] AP22 GFX_VID1
GRAPHICS VIDs
AF34 G11 AP19 AN22 GFX_VID2
AF33 F14 AP18 AP23 GFX_VID3
C645 C656 C306 C633 C638 C318 C630 C631 VCC13 VTT0_13 C627 C648 C640 C662 VAXG11 GFX_VID[3]
AF32 F13 AP16 AM23 GFX_VID4
22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 VCC14 VTT0_14 10u/6.3V_8 10u/6.3V_8 VAXG12 GFX_VID[4]
AF31 F12 AN21 AP24 GFX_VID5
GRAPHICS
22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 AF30 F11 10u/6.3V_8 10u/6.3V_8 AN19 AN24 GFX_VID6
VCC16 VTT0_16 C357 C351 C328 VAXG14 GFX_VID[6]
AF29 VCC17 VTT0_17 E14 AN18 VAXG15
AF28 E12 *22u/6.3V_8 22u/6.3V_8 AN16
VCC18 VTT0_18 22u/6.3V_8 VAXG16
AF27 D14 AM21 AR25 GFX_ON (4
VCC19 VTT0_19 VAXG17 GFX_VR_EN
AF26 D13 AM19 AT25 GFX_DPRSL
VCC20 VTT0_20 VAXG18 GFX_DPRSLPVR
AD35 D12 AM18 AM24
1.1V RAIL POWER

VCC21 VTT0_21 VAXG19 GFX_IMON GFX_IMON
AD34 VCC22 VTT0_22 D11 AM16 VAXG20
AD33 C14 C651 C623 C249 AL21
C632 C320 C657 C317 C265 C319 C658 C659 VCC23 VTT0_23 10u/6.3V_8 10u/6.3V_8 VAXG21
AD32 C13 AL19
22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 VCC24 VTT0_24 10u/6.3V_8 VAXG22
AD31 C12 AL18
22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 VCC25 VTT0_25 VAXG23
AD30 C11 AL16
VCC26 VTT0_26 VAXG24
AD29 VCC27 VTT0_27 B14 AK21 VAXG25 VDDQ1 AJ1
AD28 B12 C679 C353 C352 AK19 AF1
VCC28 VTT0_28 VAXG26 VDDQ2
- 1.5V RAILS
AD27 A14 *10u/6.3V_8 10u/6.3V_8 AK18 AE7
VCC29 VTT0_29 10u/6.3V_8 VAXG27 VDDQ3 C331 C3
AD26 A13 AK16 AE4
VCC30 VTT0_30 VAXG28 VDDQ4 1u/6.3V_4 1u
AC35 VCC31 VTT0_31 A12 AJ21 VAXG29 VDDQ5 AC1
AC34 A11 AJ19 AB7
AC33 AJ18 AB4
VCC33 +1.1V_VTT VAXG31 VDDQ7
AC32 AJ16 Y1
C650 C315 C299 C646 C647 C272 C634 C642 VCC34 VAXG32 VDDQ8
AC31 AH21 W7
VCC35 VAXG33 VDDQ9
POWER
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 AC30 AF10 AH19 W4
C 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 VCC36 VTT0_33 VAXG34 VDDQ10
AC29 VCC37 VTT0_34 AE10 AH18 VAXG35 VDDQ11 U1
AC28 AC10 AH16 T7
CPU CORE SUPPLY

AC27 AB10 C313 C325 T4
VCC39 VTT0_36 22u/6.3V_8 VDDQ13 C312 C2
AC26 Y10 P1
VCC40 VTT0_37 22u/6.3V_8 VDDQ14 22u/6.3V_8 22
AA35 W10 N7
VCC41 VTT0_38 VDDQ15
AA34 VCC42 VTT0_39 U10 VDDQ16 N4
DDR3
AA33 T10 L1
VCC43 VTT0_40 VDDQ17
AA32 VCC44 VTT0_41 J12 +1.1V_VTT J24 VTT1_45 VDDQ18 H1
FDI
C661 C277 C288 C273 C295 C327 C280 C641 AA31 J11 J23
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 VCC45 VTT0_42 R149 *SHORT_4 VTT1_46
AA30 VCC46 VTT0_43 J16 +VTT_43 H25 VTT1_47
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 AA29 J15 +VTT_44 R146 *SHORT_4 C267 C626
VCC47 VTT0_44 22u/6.3V_8 22u/6.3V_8
AA28
AA27
VCC48
VCC49
(15mils) VTT0_59
P10
AA26 N10
VCC50 C266 VTT0_60
Y35 L10
VCC51 1u/6.3V_4 VTT0_61 C275
Y34 K10
VCC52 VTT0_62 10u/6.3V_6
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30 VCC56
1.1V
Y29 J22
VCC57 VTT1_63
Y28 +1.1V_VTT K26 J20
VCC58 VTT1_48 VTT1_64
Y27 J27 J18
PEG & DMI

Y26 J26 H21 C624
VCC60 H_PSI# C635 C291 C279 C268 VTT1_50 VTT1_66 22u/6.3V_8
V35 AN33 H_PSI# (37) J25 H20
VCC61 PSI# 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 22u/6.3V_8 VTT1_51 VTT1_67
V34 H27 H19
POWER

V33 G28
VCC63 H_VID0 VTT1_53
V32 VCC64 VID[0] AK35 H_VID0 (37) G27 VTT1_54
V31 AK33 H_VID1 H_VID1 (37) G26
VCC65 VID[1] H_VID2 VTT1_55
V30 AK34 H_VID2 (37) F26
VCC66 VID[2] H_VID3 VTT1_56
V29 VCC67 VID[3] AL35 H_VID3 (37) E26 VTT1_57 VCCPLL1 L26
CPU VIDS
1.8V
V28 AL33 H_VID4 H_VID4 (37) E25 L27
B VCC68 VID[4] H_VID5 VTT1_58 VCCPLL2
V27 VCC69 VID[5] AM33 H_VID5 (37) VCCPLL3 M26
V26 AM35 H_VID6 H_VID6 (37) C270
VCC70 VID[6] H_DPRSLPVR 1u/6.3V_4
U35 VCC71 PROC_DPRSLPVR AM34 H_DPRSLPVR (37)
U34
VCC72
U33
VCC73
U32
VCC74 H_VTTVID1
U31 G15 TP2
VCC75 VTT_SELECT
U30
VCC76 Clarksfield/Auburndale
U29
VCC77 H_VTTVID1=Low, 1.1V
U28
U27
VCC78 H_VTTVID1=High, 1.05V
VCC79
U26
VCC80
R35
VCC81
R34
VCC82 +1.1V_VTT
R33 VCC83
R32 AN35 I_MON (37)
VCC84 ISENSE
R31
VCC85
R30
VCC86 R484 100_4
R29 VCC87 +VCC_CORE
R28 AJ34
SENSE LINES
VCC88 VCC_SENSE VCCSENSE (37)

R27 AJ35 VSSSENSE (37) R191 R186 R194 R198 R201 R207 R203 R501 R500
VCC89 VSS_SENSE R485 100_4 1K_4 1K_4 1K_4 *1K_4 *1K_4 1K_4 *1K_4 1K_4 *1K_4
R26
VCC90
P35
VCC91 VTT_SENSE H_VID0
P34 B15 TP39
VCC92 VTT_SENSE VSS_SENSE_VTT H_VID1
P33 A15 TP37
VCC93 VSS_SENSE_VTT H_VID2
P32
VCC94 H_VID3
P31
VCC95 H_VID4
P30 VCC96
P29 H_VID5
VCC97 H_VID6
P28 VCC98
P27 H_DPRSLPVR
VCC99 H_PSI#
P26
A VCC100
R190 R185 R193 R197 R200 R206 R202 R499 R498

*1K_4 *1K_4 *1K_4 1K_4 1K_4 *1K_4 1K_4 *1K_4 1K_4
Clarksfield/Auburndale
Note: HFM_VID : Max 1.4V
For Validating IMVP VR R6451 should be STUFF
and R2N1 NO_STUFF LFM_VID : Min 0.65V
AUBURNDALE/CLARKSFIELD PROCESSOR (POWER) Size Document Number
AUBURND
5 4 3 2
1
R)
_AXG_SENSE (43)
D
_AXG_SENSE (43)
_VID0 (43)
_VID1 (43)
_VID2 (43)
_VID3 (43)
_VID4 (43)
_VID5 (43)
_VID6 (43)
_ON (43)
_DPRSLPVR (43)
MON (43)
ARD:3A
+1.5V_CPUVDDQ
C329 C321 C301 C296

_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
+
C283 C260
V_8 22u/6.3V_8 330u/2V_7343
+1.1V_VTT
C264
6 10u/6.3V_6
C625
V_8 22u/6.3V_8
0.6A
+1.8V
B
C271 C258 C257 C253
_4 1u/6.3V_4 2.2u/6.3V_6 4.7u/10V_6 22u/6.3V_8

PROJECT : ZQ1
Number Rev
1A
RNDA 3/4 (PWR)
1
5 4 3 2
Arrandale_4(CPU) AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED,

U28H U28I U28E
AT20 AE34 AJ13

VSS1 VSS81 RSVD32
AT17 AE33 AJ12
VSS2 VSS82 RSVD33
AR31 AE32 K27
VSS3 VSS83 VSS161
AR28 AE31 K9 AP25
VSS4 VSS84 VSS162 RSVD1
AR26 AE30 K6 AL25 AH25
VSS5 VSS85 VSS163 RSVD2 RSVD34
AR24 AE29 K3 AL24 AK26
AR23 AE28 J32 AL22
AR20 AE27 J30 AJ33 AL26
AR17 AE26 J21 AG9 AR2
D VSS9 VSS89 VSS167 RSVD6 RSVD_NCTF_37
AR15 AE6 J19 M27
AR12 AD10 H35 L28 AJ26
AR9 AC8 H32 (14) VREF_DQ_DIMM0 J17 AJ27
VSS12 VSS92 VSS170 SA_DIMM_VREF RSVD39
AR6 AC4 H28 (15) VREF_DQ_DIMM1 H17
VSS13 VSS93 VSS171 SB_DIMM_VREF
AR3 AC2 H26 G25
AP20 AB35 H24 G17
AP17 AB34 H22 E31 AP1
VSS16 VSS96 VSS174 RSVD13 RSVD_NCTF_40
AP13 AB33 H18 E30 AT2
VSS17 VSS97 VSS175 RSVD14 RSVD_NCTF_41
AP10 AB32 H15
VSS18 VSS98 VSS176
AP7 AB31 H13 AT3
VSS19 VSS99 VSS177 RSVD_NCTF_42
AP4 AB30 H11 AR1
AP2 AB29 H8
VSS21 VSS101 VSS179
AN34 AB28 H5
VSS22 VSS102 VSS180
AN31 AB27 H2
VSS23 VSS103 VSS181
AN23 AB26 G34 AL28
VSS24 VSS104 VSS182 CFG0 RSVD45
AN20 AB6 G31 AM30 AL29
VSS25 VSS105 VSS183 CFG[0] RSVD46
AN17 AA10 G20 AM28 AP30
AM29 Y8 G9 AP31 AP32
VSS27 VSS107 VSS185 CFG3 CFG[2] RSVD48
AM27 Y4 G6 AL32 AL27
AM25 Y2 G3 AL30 AT31
AM20 W35 F30 AM31 AT32
AM17 W34 F27 AN29 AP33
AM14 W33 F25 AM32 AR33
AM11 W32 F22 AK32 AT33
VSS33 VSS113 VSS191 CFG[8] RSVD_NCTF_54
AM8 W31 F19 AK31 AT34
RESERVED
AM5 W30 F16 AK28 AP35
AM2 W29 E35 AJ28 AR35
AL34 W28 E32 AN30 AR32
C AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
E29
E24
VSS195
VSS196
VSS197
VSS AN32
AJ32
CFG[12]
CFG[13]
CFG[14]
RSVD58
AL20 W6 E21 AJ29 E15

VSS40 VSS120 VSS198 CFG[15] RSVD_TP_59
AL17 V10 E18 AJ30 F15
VSS41 VSS121 VSS199 CFG[16] RSVD_TP_60
AL12 U8 E13 AK30 A2
VSS42 VSS122 VSS200 CFG[17] KEY
AL9 U4 E11 H16 D15
VSS43 VSS123 VSS201 RSVD_TP_86 RSVD62
AL6 U2 E8 C15
AL3 T35 E5 AJ15 TP4
AK29 T34 E2 AT35 AH15 TP3
VSS46 VSS126 VSS204 VSS_NCTF1 RSVD65
AK27 T33 D33 AT1
VSS47 VSS127 VSS205 VSS_NCTF2
AK25 T32 D30 AR34 TP42 B19
AK20 T31 D26 B34 TP41 A19
AK17 T30 D9 B2 TP1
NCTF
VSS50 VSS130 VSS208 VSS_NCTF5
AJ31 T29 D6 B1 TP40 A20
AJ23 T28 D3 A35 TP38 B20
AJ20 T27 C34 AA5
VSS53 VSS133 VSS211 RSVD_TP_66
AJ17 T26 C32 U9 AA4
VSS54 VSS134 VSS212 RSVD19 RSVD_TP_67
AJ14 T6 C29 T9 R8
AJ11 R10 C28 AD3
AJ8 P8 C24 AC9 AD2
AJ5 P4 C22 AB9 AA2
AJ2 P2 C20 AA1
AH35 N35 C19 R9
AH34 N34 C16 AG7
AH33 N33 B31 C1 AE3
VSS62 VSS142 VSS220 RSVD_NCTF_23 RSVD_TP_75
AH32 N32 B25 A3
AH31 N31 B21
VSS64 VSS144 VSS222
AH30 N30 B18 V4
B AH29 N29 B17 V5
AH28 N28 B13 N2
AH27 N27 B11 J29 AD5
AH26 N26 B8 J28 AD7
AH20 N6 B6 W3
AH17 M10 B4 A34 W2
AH13 L35 A29 A33 N3
AH9 L32 A27 AE5
AH6 L29 A23 C35 AD9
AH3 L8 A9 B35
AG10 L5
VSS76 VSS156
AF8 L2 AP34 TP43
VSS77 VSS157 VSS
AF4 K34
VSS78 VSS158 AP34 can be NC on CRB; EDS/
AF2 K33
VSS79 VSS159
AE35 K30
VSS80 VSS160
Clarksfield/Auburndale
Clarksfield/Auburndale Clarksfield/Auburndale
Processor Strapping The CFG signals have a default value of '1' if not terminated on the board.
1 0 CFG4 R157 *3.01K/F_4

CFG4 Enabled; An external Display port CFG0 R495 *3.01K/F_4
A (Display Port Disabled; No Physical Display Port device is connected to the Embedded
Presence) attached to Embedded Diplay Port Display port Use RVS type CFG3 R496 3.01K/F_4
CFG0 CFG[ 1:0 ] - PCI_Epress Configuration Select CFG7 R497 *3.01K/F_4

* 11= 1 x 16 PEG
(PCI-Epress Single PEG Bifurcation enabled
Configuration Select)
* 10= 2 x 8 PEG
The Clarkfield processor's PCI Express interface may not meet Qu
PCI Express 2.0 jitter specifications. Intel recommends
CFG3 placing a 3.01K +/- 5% pull down resistor to VSS on CFG[7] pin PRO
(PCI-Epress Static Normal Operation Lane Numbers Reversed for both rPGA and BGA components. This pull down resistor Size Document Number
Lane Reversal) should be removed when this issue is fixed.(ES1 only) AUBURNDA 4/4
5 4 3 2
1
, CFG)
; EDS/DG suggestion to GND

PROJECT : ZQ1
Rev
1A
4/4
10 Sheet 7 of 48
1
5 4 3 2
PCH1(CLG) IBEX PEAK-M (DMI,FDI,GPIO)

IBEX PEAK-M (LVDS,DDI)
U35C
FDI_RXN0 BA18 FDI_TXN0 (4)
BC24 BH17 U35D
(4) DMI_RXN0 DMI0RXN FDI_RXN1 FDI_TXN1 (4)
(4) DMI_RXN1 BJ22 BD16 FDI_TXN2 (4) (25) INT_LVDS_BLON T48 BJ46
DMI1RXN FDI_RXN2 L_BKLTEN SDVO_TVCLKINN
D (4) DMI_RXN2 AW20 BJ16 FDI_TXN3 (4) (25) INT_LVDS_DIGON T47 BG46
DMI2RXN FDI_RXN3 L_VDD_EN SDVO_TVCLKINP
(4) DMI_RXN3 BJ20 BA16 FDI_TXN4 (4)
DMI3RXN FDI_RXN4
BE14 FDI_TXN5 (4) (25) INT_LVDS_BRIGHT Y48 BJ48
FDI_RXN5 L_BKLTCTL SDVO_STALLN
(4) DMI_RXP0 BD24 BA14 FDI_TXN6 (4) BG48
DMI0RXP FDI_RXN6 SDVO_STALLP
(4) DMI_RXP1 BG22 BC12 FDI_TXN7 (4) (25) INT_LVDS_EDIDCLK AB48
DMI1RXP FDI_RXN7 L_DDC_CLK
(4) DMI_RXP2 BA20 (25) INT_LVDS_EDIDDATA Y45 BF45
DMI2RXP L_DDC_DATA SDVO_INTN
(4) DMI_RXP3 BG20 DMI3RXP FDI_RXP0 BB18 FDI_TXP0 (4) SDVO_INTP BH45
BF17 +3V R259 10K_4 AB46
FDI_RXP1 FDI_TXP1 (4) L_CTRL_CLK
BE22 BC16 R256 10K_4 V48
(4) DMI_TXN0 DMI0TXN FDI_RXP2 FDI_TXP2 (4) L_CTRL_DATA
(4) DMI_TXN1 BF21 BG16 FDI_TXP3 (4)
DMI1TXN FDI_RXP3 R272 2.37K/F_4
(4) DMI_TXN2 BD20 DMI2TXN FDI_RXP4 AW16 FDI_TXP4 (4) AP39 LVD_IBG SDVO_CTRLCLK T51
(4) DMI_TXN3 BE18 BD14 FDI_TXP5 (4) AP41 T53
DMI3TXN FDI_RXP5 LVD_VBG SDVO_CTRLDATA
FDI_RXP6 BB14 FDI_TXP6 (4)
(4) DMI_TXP0 BD22 BD12 FDI_TXP7 (4) AT43
DMI0TXP FDI_RXP7 LVD_VREFH
(4) DMI_TXP1 BH21 AT42 BG44
DMI1TXP LVD_VREFL DDPB_AUXN
(4) DMI_TXP2 BC20 DMI2TXP DDPB_AUXP BJ44
(4) DMI_TXP3 BD18 BJ14 FDI_INT (4) AU38
DMI3TXP FDI_INT DDPB_HPD
LVDS
(25) INT_TXLCLKOUT- INT_TXLCLKOUT- AV53
DMI
FDI
INT_TXLCLKOUT+ LVDSA_CLK# INT_HDMITX2N_R C409
FDI_FSYNC0 BF13 FDI_FSYNC0 (4) (25) INT_TXLCLKOUT+ AV51 LVDSA_CLK DDPB_0N BD42
BH25 BC42 INT_HDMITX2P_R C413
DMI_ZCOMP INT_TXLOUT0- DDPB_0P INT_HDMITX1N_R C417
BH13 FDI_FSYNC1 (4) (25) INT_TXLOUT0- BB47 BJ42
R548 49.9/F_4 DMI_COMP FDI_FSYNC1 INT_TXLOUT1- LVDSA_DATA#0 DDPB_1N INT_HDMITX1P_R C423
BF25 BA52 BG42
Digital Display Interface

+1.05V DMI_IRCOMP (25) INT_TXLOUT1- LVDSA_DATA#1 DDPB_1P
BJ12 INT_TXLOUT2- AY48 BB40 INT_HDMITX0N_R C426
FDI_LSYNC0 FDI_LSYNC0 (4) (25) INT_TXLOUT2- LVDSA_DATA#2 DDPB_2N
AV47 BA40 INT_HDMITX0P_R C431
LVDSA_DATA#3 DDPB_2P INT_HDMICLK-_R C404
BG14 FDI_LSYNC1 (4) AW38
FDI_LSYNC1 INT_TXLOUT0+ DDPB_3N INT_HDMICLK+_R C405
(25) INT_TXLOUT0+ BB48 BA38
INT_TXLOUT1+ LVDSA_DATA0 DDPB_3P
(25) INT_TXLOUT1+ BA50
INT_TXLOUT2+ LVDSA_DATA1
C (25) INT_TXLOUT2+ AY49
LVDSA_DATA2
AV48 Y49
B-test LVDSA_DATA3 DDPC_CTRLCLK
AB49
DDPC_CTRLDATA
INT_TXUCLKOUT- AP48
T56 LVDSB_CLK#
R351 *Short_4 XDP_DBRST#_R T6 J12 PCIE_WAKE# T59 INT_TXUCLKOUT+ AP47 BE44
(4,16) XDP_DBRST# SYS_RESET# WAKE# PCIE_WAKE# (27) LVDSB_CLK DDPC_AUXN
BD44
INT_TXUOUT0- DDPC_AUXP
T53 AY53 AV40
SYS_PWROK R354 *Short_4 SYS_PWROK_R CLKRUN# INT_TXUOUT1- LVDSB_DATA#0 DDPC_HPD
M6 Y1 CLKRUN# (35) T58 AT49
SYS_PWROK CLKRUN# / GPIO32 INT_TXUOUT2- LVDSB_DATA#1
T101 AU52 BE40
LVDSB_DATA#2 DDPC_0N
AT53 BD40
LVDSB_DATA#3 DDPC_0P
System Power Management
R353 *Short_4 PCHPWROK B17 BF41

PWROK INT_TXUOUT0+ DDPC_1N
T54 AY51 LVDSB_DATA0 DDPC_1P BH41
INT_TXUOUT1+ AT48 BD38
T57 LVDSB_DATA1 DDPC_2N
R355 *Short_4 MEPWROK K5 P8 SUS_STAT#
TP35 T104
INT_TXUOUT2+ AU50 BC38
MEPWROK SUS_STAT# / GPIO61 LVDSB_DATA2 DDPC_2P
AT51 BB36
LVDSB_DATA3 DDPC_3N
BA36
RSV_ICH_LAN_RST# A10 C3C DDPC_3P
F3 ICH_SUSCLK (35)
LAN_RST# SUSCLK / GPIO62
INT_CRT_BLU AA52 U50
(25) INT_CRT_BLU CRT_BLUE DDPD_CTRLCLK
D9 E4 SLP_S5#_R TP36 INT_CRT_GRN AB53 U52
(16) PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 (25) INT_CRT_GRN CRT_GREEN DDPD_CTRLDATA
INT_CRT_RED AD53
(25) INT_CRT_RED CRT_RED
ICH_RSMRST# C16 H7 BC46
(35) ICH_RSMRST# RSMRST# SLP_S4# SUSC# (35) DDPD_AUXN
(25) INT_CRT_DDCCLK V51 BD46
CRT_DDC_CLK DDPD_AUXP
(25) INT_CRT_DDCDAT V53 AT38
SUS_PWR_ACK_R C-test CRT_DDC_DATA DDPD_HPD
M1 SUS_PWR_DN_ACK / GPIO30 SLP_S3# P12 SUSB# (35)
B
B-test BJ40
DDPD_0N
(25) INT_HSYNC Y53 BG40
R622 *Short_4 SLP_M# R339 *0_4 CRT_HSYNC DDPD_0P
(35) DNBSWON# P5 PWRBTN# SLP_M# K8 (25) INT_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38 R
(16) PM_PWRBTN#_R BG38
DDPD_1P
CRT
BF37 R241
R356 *0_4 ACIN_R DAC_IREF DDPD_2N
(35) PCH_ACIN P7 N2 TP50 AD48 BH37
ACPRESENT / GPIO31 TP23 DAC_IREF DDPD_2P R240
AB51 BE36
CRT_IRTN DDPD_3N
DDPD_3P BD36
PM_BATLOW# A6 BJ10 R248 R243
BATLOW# / GPIO72 PMSYNCH PM_SYNC (4)
1K/F_4 IbexPeak-M_R1P0
PM_RI# F14 F6 PM_SLP_LAN#

RI# SLP_LAN# / GPIO29
IbexPeak-M_R1P0
PCH Pull-high/low(CLG) System PWR_OK(CLG)

+3V_S5
+3V
PM_RI# R305 10K_4

CLKRUN# R605 8.2K_4 +3V_S5
PM_BATLOW# R615 8.2K_4 DELAY_VR_PWRGOOD need PU 2K to +3V.
XDP_DBRST#_R R350 1K_4 C797 *0.1u/10V_4
A
PCIE_WAKE# R304 10K_4 10/5 modify PU at power side
5
ICH_RSMRST# R303 10K_4 PM_SLP_LAN# R326 *10K_4 1
SYS_PWROK DELAY_VR_PWRGOOD (4,37)
4
RSV_ICH_LAN_RST# R594 10K_4 SUS_PWR_ACK_R R592 10K_4 2
U39
PWROK_EC (35)
Q
3
SYS_PWROK R352 10K_4 ACIN_R R357 10K_4 R593 100K_4
TC7SH08FU
P
IBEX PEAK-M
5 4 3 2
1
SDVO_CTRLCLK (26)
SDVO_CTRLDAT (26)
INT_HDMI_HPD (26)
09 0.1u/10V_4
INT_HDMITX2N (26)
13 0.1u/10V_4
INT_HDMITX2P (26)
17 0.1u/10V_4
INT_HDMITX1N (26)
23 0.1u/10V_4
INT_HDMITX1P (26)
26 0.1u/10V_4
INT_HDMITX0N (26)
31 0.1u/10V_4
INT_HDMITX0P (26)
04 0.1u/10V_4
INT_HDMICLK- (26)
05 0.1u/10V_4
INT_HDMICLK+ (26)
C
R place close to PCH

R241 150/F_4 INT_CRT_BLU
R240 150/F_4 INT_CRT_GRN
R243 150/F_4 INT_CRT_RED

PROJECT : ZQ1
r Rev
1A
K-M 1/6
0, 2010 Sheet 8 of 48
1
5 4 3 2
RTC Circuitry(RTC) PCH2(CLG)

C465 15p/50V_4
IBEX PEAK-M (HDA,JTAG,SATA)
+VCCRTC
1
D18
Y1
+3VPCU U35A
20mils R531 20K/F_4 RTC_RST# 32.768KHz R311
VCCRTC_1 10M_4
4
1
20MIL J1 RTC_X1 B13 D33
RTCX1 FWH0 / LAD0 LPC_LAD0 (28,35)
BAT54C C727 C463 15p/50V_4 RTC_X2 D13 B33
RTCX2 FWH1 / LAD1 LPC_LAD1 (28,35)
1u/6.3V_4 C32
FWH2 / LAD2 LPC_LAD2 (28,35)
30mils *SHORT_ PAD A32 LPC_LAD3 (28,35)
2
RTC_RST# FWH3 / LAD3
C14
RTCRST#
C34 LPC_LFRAME# (28,35)
SRTC_RST# FWH4 / LFRAME#
D17
D
R527 20K/F_4 SRTC_RST# SRTCRST# PCH_DRQ#0
A34 TP44
RTC
LPC
R570 1M_4 SM_INTRUDER# LDRQ0# PCH_DRQ#1
+VCCRTC A16 F34 TP10
INTRUDER# LDRQ1# / GPIO23
1
R533 J2 R342 10K_4 +3V
1K_4 C723 C720 PCH_INVRMEN A14 AB9
INTVRMEN SERIRQ IRQ_SERIRQ (35)
1u/6.3V_4 1u/6.3V_4
*SHORT_ PAD
2
HDA_SYNC (PCH strap pin) ACZ_BIT_CLK A30
HDA_BCLK
AK7 SATA_RX0- (29)
ACZ_SYNC SATA0RXN
20MIL Internal weak pull-down D29
HDA_SYNC SATA0RXP
AK6 SATA_RX0+ (29)
VCCVRM=>+1.8V (default) AK11 SATA_TXN0_C C425 0.01u/16V_4
SATA_TX0- (29) SATA
VCCRTC_2 SATA0TXN
1 3 RTC_N01 R545 20K_6
+5V_S5 external pull-up (30) SPKR P1 AK9 SATA_TXP0_C C432 0.01u/16V_4
SATA_TX0+ (29)
SPKR SATA0TXP
Q34 R541 VCCVRM=>+1.5V ACZ_RST# CAP. Close connect side
C30
HDA_RST#
20MIL SATA1RXN
AH6 SATA_RX1- (29)
1
MMBT3904 68.1K/F_4 AH5

SATA1RXP SATA_RX1+ (29)
CN22
(30) PCH_AZ_CODEC_SDIN0 G30 AH9 SATA_TXN1_C C284 0.01u/16V_4
SATA_TX1- (29) SATA
2
RTC_N03 HDA_SDIN0 SATA1TXN

RTC_ML2032 AH8 SATA_TXP1_C C290 0.01u/16V_4
SATA_TX1+ (29)
SATA1TXP
TP13 F30
HDA_SDIN1
AF11
R537 SATA2RXN
TP12 E32 AF9
IHDA
HDA_SDIN2 SATA2RXP
AF7
2
150K/F_6 SATA2TXN
TP11 F32
HDA_SDIN3 SATA2TXP
AF6 Note:
AH3 SATA port2/3 may not be available on all PCH sku
ACZ_SDOUT SATA3RXN
B29
HDA_SDO SATA3RXP
AH1 (HM55 support 4port only)
AF3
SATA3TXN
AF1
HDA_DOCK_EN# SATA3TXP
H32
SATA
HDA_DOCK_EN# / GPIO33
AD9 SATA_RX4N_C TP30
PCH_GPIO13 SATA4RXN
+3V_S5 R289 *10K_4 J30 AD8 SATA_RX4P_C TP27
HDA_DOCK_RST# / GPIO13 SATA4RXP
(26) HDMI_HPD_PCH# AD6 SATA_TXN4_C TP32
SATA4TXN
B-test AD5 SATA_TXP4_C
HDA Bus(CLG) PCH_JTAG_TCK
SATA4TXP TP33
TP52 M3 AD3
JTAG_TCK SATA5RXN
AD1
PCH_JTAG_TMS SATA5RXP
TP51 K3 AB3
R538 33_4 ACZ_SYNC JTAG_TMS SATA5TXN
C
(30) PCH_AZ_CODEC_SYNC AB1
PCH_JTAG_TDI SATA5TXP
TP48 K1
JTAG_TDI
JTAG
R534 33_4 ACZ_RST# PCH_JTAG_TDO J2 AF16
(30) PCH_AZ_CODEC_RST# TP49 JTAG_TDO SATAICOMPO
PCH_JTAG_RST# J4 AF15 SATA_COMP R302 37.4/F_4 +1.05V
TP47 TRST# SATAICOMPI
R542 33_4 ACZ_SDOUT
(30) PCH_AZ_CODEC_SDOUT
SPI_CLK_R BA2
SPI_CLK
R536 33_4 ACZ_BIT_CLK SPI_CS0#_R AV3
(30) PCH_AZ_CODEC_BITCLK SPI_CS0#
+3VPCU R589 *10K_4 SPI_CS1# AY3 T3

SPI_CS1# SATALED# SATA_ACT# (33)
C740
*27p/50V_4
PCH_ODD_EN (29)
SPI_SI_R AY1 Y9 R344 10K_4
SPI_MOSI SATA0GP / GPIO21 D3D
SPI
SPI_SO_R AV1 V1 R624 10K_4 +3V
SPI_MISO SATA1GP / GPIO19
Place all series terms close to PCH except for SDIN input PCH Strap Table IbexPeak-M_R1P0
lines,which should be close to source.Placement of
R should equal distance to the T split trace point. Pin Name Strap description Sampled Configuration ZQ1 note
Basically, keep the same distance from T for all series
termination resistors. 0 = Default (weak pull-down 20K)
SPKR No reboot mode setting PWROK +3V R601 *10K_4 SPKR
1 = Setting to No-Reboot mode
1 = Default (weak pull-up 20K)
INIT3_3V Reserved PWROK Should not be pull-down
0 = "top-block swap" mode
GNT3# / GPIO55 Top-Block Swap Override PWROK R517 *10K_4
1 = Default (weak pull-up 20K) PCI_GNT3# (10)
INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up +VCCRTC R567 330K_4 PCH_INVRMEN
GNT1# / GPIO51 Boot BIOS Selection 1 [bit-1] PWROK GNT1# GNT0# Boot Location Default weak pull-up on GNT0/1#
[Need external pull-down for LPC BIOS]
1 1 SPI +3V
R249 1K_4 C-test
R245 1K_4
1 0 PCI
GNT0# Boot BIOS Selection 0 [bit-0] PWROK R255 *1K_4
PCI_GNT0# (10)
R254 *1K_4
PCI_GNT1# (10)
0 0 LPC
Should not be pull-down
GNT2# / GPIO53 ESI strap (Server only) PWROK (weak pull-up 20K) USE GPIO PIN
NV_ALE Intel Anti-Theft HDD protection PWROK 0 = Disable (Internal pull-down 32ohm) +1.8V R590 *1K_4 NV_ALE
NV_ALE (10)
NV_CLE DMI Termination voltage PWROK weak pull-down 32ohm +1.8V R591 *1K_4 NV_CLE
NV_CLE (10)
HDA_DOCK_EN#/GPIO33 Flash Descriptor Security PWROK 0 = Override R277 *1K_4

+3V R273 *10K_4 HDA_DOCK_EN#
1 = Default (weak pull-up 20K)
SPI_MOSI iTPM function Disable MEPWROK 0 = Default (weak pull-down 20K) +3V R627 *1K_4 SPI_SI_R
PCH SPI(CLG) 1 = Enable

Should not be pull-up
A
C-test
HDA_SDO Reserved RSMRST# (weak pull-down 20K)
+3V Should not be pull-down +3V_S5 R340 10K_4
RSV_GPIO8 (11)
U40 GPIO8 Reserved RSMRST#
SPI_CS0#_R 1 8 (weak pull-up 20K)
SPI_CLK_R CE# VDD
6
SPI_SI_R SCK
5
SI GPIO27 On-die PLL Voltage Regulator RSMRST# 0 = Disable
SPI_SO_R R609 *Short_4 SPI_SO 2 7 R608 3.3K/F_4
SO HOLD# 1 = Enable (weak pull-up 20K)
B-test
C803
3
WP# VSS
4
C796
HDA_SYNC
*22p/50V_4 W25Q32BVSSIG 0.1u/10V_4
On-die PLL PWR supply select RSMRST# 0 = 1.8V supply (weak pull-down 20K) use defaul (0 = 1.8V supply) Qua
1 = 1.5V supply
GPIO15 Reserved RSMRST# 0 = TLS no Confidentiality
PRO
+3V R611 3.3K/F_4 +3V_S5 R349 1K_4 Size Document Number
(weak pull-down 20K) CR_WAKE# (11)
IBEX PEAK-M 2/6
1 = TLS Confidentiality
5 4 3 2
1
8,35)
D
SATA HDD
SATA ODD

PROJECT : ZQ1
Rev
1A
M 2/6
10 Sheet 9 of 48
1
5 4 3 2
PCH3(CLG)
IBEX PEAK-M (PCI,USB,NVRAM) IBEX PEAK-M (PCI-E,SMBUS,CLK)
8/13 Swap Lan and WLAN/ Lan chagne to port 1
U35B
U35E
H40 AY9 BG30 B9 RSV_SMBALERT#
AD0 NV_CE#0 (27) PCIE_RX1- PERN1 SMBALERT# / GPIO11
N34 BD1 (27) PCIE_RX1+ BJ30
AD1 NV_CE#1 C741 0.1u/10V_4 PCIE_TXN1_C PERP1 ICH_SMBCLK
C44
AD2 NV_CE#2
AP15 LAN (27) PCIE_TX1- BF29
PETN1 SMBCLK
H14 ICH
A38 BD8 C737 0.1u/10V_4 PCIE_TXP1_C BH29
AD3 NV_CE#3 (27) PCIE_TX1+ PETP1
C36 C8 ICH_SMBDATA
AD4 SMBDATA ICH
J34 AV9 (28) PCIE_RX2- AW30
AD5 NV_DQS0 PERN2
A40 BG8 (28) PCIE_RX2+ BA30
AD6 NV_DQS1 C438 0.1u/10V_4 PCIE_TXN2_C PERP2 RSV_SML0ALERT#
D
D45
AD7 Mini 3G (28) PCIE_TX2- BC30
PETN2 SML0ALERT# / GPIO60
J14
E36 AP7 C435 0.1u/10V_4 PCIE_TXP2_C BD30
AD8 NV_DQ0 / NV_IO0 (28) PCIE_TX2+ PETP2
H48 AP6 C6 SMB_CLK_ME0
AD9 NV_DQ1 / NV_IO1 SML0CLK SM
E40 AT6 T72 AU30
SMBus
AD10 NV_DQ2 / NV_IO2 T71 PERN3 SMB_DATA_ME0
C40 AT9 AT30 G8 SM
AD11 NV_DQ3 / NV_IO3 T65 PERP3 SML0DATA
M48 BB1 AU32
AD12 NV_DQ4 / NV_IO4 T70 PETN3
M45 AV6 AV32
AD13 NV_DQ5 / NV_IO5 PETP3 RSV_SML1ALERT# R330 *0
F53 BB3 M14
AD14 NV_DQ6 / NV_IO6 T66 SML1ALERT# / GPIO74
M40 BA4 BA32
AD15 NV_DQ7 / NV_IO7 T67 PERN4 SMB_CLK_ME1
NVRAM
M43 BE4 BB32 E10
AD16 NV_DQ8 / NV_IO8 T68 PERP4 SML1CLK / GPIO58
J36
K48
AD17 NV_DQ9 / NV_IO9
BB6
BD6 T69
BD32
BE32
PETN4
G12 SMB_DATA_ME1 For E
AD18 NV_DQ10 / NV_IO10 PETP4 SML1DATA / GPIO75
F40 BB7
PCI-E*
AD19 NV_DQ11 / NV_IO11 B-test T114
C42 BC8 BF33
AD20 NV_DQ12 / NV_IO12 PERN5
K46 BJ8 BH33 T13 CL_CLK1 CL_
AD21 NV_DQ13 / NV_IO13 PERP5 CL_CLK1
Controller
M51 BJ6 BG32
AD22 NV_DQ14 / NV_IO14 PETN5
J52 BG6 BJ32 T11 CL_DATA1 CL_
AD23 NV_DQ15 / NV_IO15 PETP5 CL_DATA1
K51
Link
AD24 NV_ALE CL_RST1#
L34 BD3 NV_ALE (9) (28) PCIE_RX6- BA34 T9 CL_
AD25 NV_ALE NV_CLE PERN6 CL_RST1#
F42 AY6 NV_CLE (9) (28) PCIE_RX6+ AW34
AD26 NV_CLE C420 0.1u/10V_4 PCIE_TXN6_C PERP6
J40
AD27 MiniWLAN (28) PCIE_TX6- BC34
PETN6
G46 C424 0.1u/10V_4 PCIE_TXP6_C BD34
AD28 (28) PCIE_TX6+ PETP6
F44 AU2 H1 PEG_CLKREQ#_R R599 *SW
AD29 NV_RCOMP PEG_A_CLKRQ# / GPIO47
M47 AT34
AD30 PERN7
PCI
H36 AV7 AU34 P
AD31 NV_RB# PERP7
AU36 AD43 CLK
PETN7 CLKOUT_PEG_A_N
J50 AY8 AV36 AD45 CLK
C/BE0# NV_WR#0_RE# PETP7 CLKOUT_PEG_A_P
G42
C/BE1# NV_WR#1_RE#
AY5 Note:
H47 BG34 AN4 CLK
C/BE2# PCIE port7/8 may not be available on all PCH sku PERN8 CLKOUT_DMI_N
PEG
G34 AV11 BJ34 AN2 CLK
C/BE3# NV_WE#_CK0 PERP8 CLKOUT_DMI_P
NV_WE#_CK1
BF5 (HM55 support 6port only) BG36
PETN8
PCI_PIRQA# G38 Port1 and port9 can be used on debug mode BJ36
PCI_PIRQB# PIRQA# PETP8
H51 AT1 DPL
PCI_PIRQC# PIRQB# USBP0- CLKOUT_DP_N / CLKOUT_BCLK1_N
B37 H18 TP24 AT3 DPL
PCI_PIRQD# PIRQC# USBP0N USBP0+ 1/21 ramp remove CLK TP CLKOUT_DP_P / CLKOUT_BCLK1_P
A44 J18 TP26 AK48
PIRQD# USBP0P C3C CLKOUT_PCIE0N
A18 USBP1- (32) AK47
USBP1N CLKOUT_PCIE0P
From CLK BUFFER

PCI_REQ0# F51 C18 MB USB AW24
C REQ0# USBP1P USBP1+ (32) CLKIN_DMI_N CLK
PCI_REQ1# A46 N20 USBP2- TP21 CLK_PCIE_REQ0# P9 BA24
REQ1# / GPIO50 USBP2N PCIECLKRQ0# / GPIO73 CLKIN_DMI_P CLK
dGPU_SELECT# B45 P20 USBP2+ TP14
(25) dGPU_SELECT# REQ2# / GPIO52 USBP2P
PCI_REQ3# M53 J20
REQ3# / GPIO54 USBP3N USBP3- (32)
L20 USB/B-USB1-3 R237 *0_4 CLK_PCH_SRC1N AM43 AP3
USBP3P USBP3+ (32) (28) CLK_PCH_SRC1# CLKOUT_PCIE1N CLKIN_BCLK_N CLK
PCI_GNT0# F48 F20 EHCI1 Mini 3G R236 *0_4 CLK_PCH_SRC1P AM45 AP1
(9) PCI_GNT0# GNT0# USBP4N USBP4- (32) (28) CLK_PCH_SRC1 CLKOUT_PCIE1P CLKIN_BCLK_P CLK
PCI_GNT1# K45 G20 BLUETOOTH B-test
(9) PCI_GNT1# GNT1# / GPIO51 USBP4P USBP4+ (32)
F36 A20 (28) CLKREQ_3G# R348 *0_4 CLK_PCIE_REQ1# U4
(25) PWM_SELECT# GNT2# / GPIO53 USBP5N USBP5- (28) PCIECLKRQ1# / GPIO18
PCI_GNT3# H53 C20 Reserved SIM USB F18
(9) PCI_GNT3# GNT3# / GPIO55 USBP5P USBP5+ (28) CLKIN_DOT_96N CLK
M22 USBP6- TP17 E18
USBP6N CLKIN_DOT_96P CLK
PCI_PIRQE# B41 N22 USBP6+ TP16 USB port6/7 may not be available on all PCH sku R235 *Short_4 CLK_PCH_SRC2N AM47
PIRQE# / GPIO2 USBP6P (28) CLK_PCH_SRC2# CLKOUT_PCIE2N
PCI_PIRQF# K53 B21 USBP7- TP15 (HM55 support 12port only) MiniWLAN R234 *Short_4 CLK_PCH_SRC2P AM48
PIRQF# / GPIO3 USBP7N (28) CLK_PCH_SRC2 CLKOUT_PCIE2P
PCI_PIRQG# A36 D21 USBP7+ TP18 AH13
PIRQG# / GPIO4 USBP7P CLKIN_SATA_N / CKSSCD_N CLK
PCI_PIRQH# A48 H22 (28) CLKREQ_WLAN# R620 *Short_4 CLK_PCIE_REQ2# N4 AH12
PIRQH# / GPIO5 USBP8N USBP8- (25) PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P CLK
USBP8P
J22 USBP8+ (25) Camera
USB
PCI_RST# K6 E22 B-test

(28) PCI_RST# PCIRST# USBP9N USBP9- (32)
USBP9P
F22 USBP9+ (32) USB/B-USB1-2 AH42
CLKOUT_PCIE3N REFCLK14IN
P41 CLK
PCI_SERR# E44 A22 1/21 ramp remove CLK TP AH41
SERR# USBP10N USBP10- (28) CLKOUT_PCIE3P
PCI_PERR# E50 C22 Mini Card (3G)
PERR# USBP10P USBP10+ (28)
G24 EHCI2 CLK_PCIE_REQ3# A8 J42 CLK_PCI_FB
USBP11N USBP11- (32) PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK
USBP11P
H24 USBP11+ (32) USB/B-USB1-1 High = JV41/JM41
PCI_IRDY# A42 L24 BOARD_ID0
IRDY# USBP12N USBP12- (31)
PCI_PAR H44 M24 Card Reader Low = JM51 AM51 AH51 XTAL25_IN
TP9 PAR USBP12P USBP12+ (31) CLKOUT_PCIE4N XTAL25_IN
PCI_DEVSEL# F46 A24 AM53 AH53 XTAL25_OUT
DEVSEL# USBP13N USBP13- (28) CLKOUT_PCIE4P XTAL25_OUT
PCI_FRAME# C46 C24 Mini Card (WLAN) High = Disable
FRAME# USBP13P USBP13+ (28)
RSV_GPIO8 CLK_PCIE_REQ4# M9 AF38 XCLK_RCOMP R260 90.9
PCI_PLOCK# PCIECLKRQ4# / GPIO26 XCLK_RCOMP
D49
PLOCK#
Low = Enable
B25 USB_BIAS
PCI_STOP# USBRBIAS# R293 BOARD_ID1
D41 AJ50 T45
PCI_TRDY# STOP# 22.6/F_4 CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
C48 D25 AJ52
TRDY# USBRBIAS C3C CLKOUT_PCIE5P
TP31 ICH_PME# M7 C-test CLK_PCIE_REQ5# H6 P43 BOARD_ID2
Clock Flex
PME# USB_OC0#_R R290 *Short_4 B-test PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65
N16 USB_OC0# (32)
PCI_PLTRST# OC0# / GPIO59 USB_OC1#_R R316 *Short_4
D5 J16 USB_OC1# (32)
PLTRST# OC1# / GPIO40 USB_OC2# R515 *Short_4 CLK_PCH_SRC6N BOARD_ID3
F16 (27) CLK_PCIE_LOM# AK53 T42
R520 22_4 CLK_LPC_DEBUG_C OC2# / GPIO41 USB_OC3# R516 *Short_4 CLK_PCH_SRC6P CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
(28) CLK_LPC_DEBUG N52
CLKOUT_PCI0 OC3# / GPIO42
L16 LAN (27) CLK_PCIE_LOM AK51
CLKOUT_PEG_B_P
T103 CLK_PCI_PCCARD P53 E14 USB_OC4# R285 *Short_4
B CLKOUT_PCI1 OC4# / GPIO43 USB_OC4_5# (32)
R250 22_4 CLK_PCI_775_C P46 G16 USB_OC5# R291 *Short_4 (27) CLK_PCIE_LAN_REQ# CLK_PCIE_LAN_REQ# P13 N50
(35) CLK_PCI_775 CLKOUT_PCI2 OC5# / GPIO9 PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67 dGPU
CLK_PCI_FB R251 22_4 CLK_PCI_FB_C P51 F12 USB_OC6#
CLKOUT_PCI3 OC6# / GPIO10 USB_OC7#
P48 T15
CLKOUT_PCI4 OC7# / GPIO14 IbexPeak-M_R1P0 R519 SW@10K_4 +3V
IbexPeak-M_R1P0
May be remove is
PEG_A_CLKRQ# PD for FreeRun, due GPU not support.
PLTRST#(CLG) PCI/USBOC# Pull-up(CLG) CLK_REQ/Strap Pin(CLG) A16 swap override Strap/Top-Block SMBus/Pull-up(CLG)
B-test
Swap Override jumper
+3V_S5 +3V
+3V_S5 Low = A16 swap
RP2 R595 10K_4 CLK_PCIE_REQ0# override/Top-Block C3C
USB_OC7# 6 5 R596 10K_4 CLK_PCIE_REQ3# PCI_GNT3# R629 10K_4 BOARD_ID1 R630 *10K_4
USB_OC6# USB_OC0# R598 10K_4 CLK_PCIE_REQ4#
Swap Override enabled
7 4
USB_OC5# 8 3 USB_OC1# R329 10K_4 CLK_PCIE_REQ5# High = Default R631 *10K_4 BOARD_ID2 R632 10K_4 C3B
Add Buffers as needed for USB_OC4# 9 2 USB_OC2# R619 10K_4 CLK_PCIE_LAN_REQ#
(35) 2ND_MBCLK
+3V_S5 10 1 USB_OC3# R633 *10K_4 BOARD_ID3 R634 10K_4 D3D
Loading and fanout concerns. +3V_S5
Boot BIOS Strap
8.2K_10P8R +3V
GNT0# GNT1# Boot BIOS Location
C470
+3V R603 10K_4 CLK_PCIE_REQ1# 0 0 LPC High = JV41_CP(ZQ1)
0.1u/10V_4 RP4 R621 10K_4 CLK_PCIE_REQ2# BOARD_ID1
PCI_REQ0# 6 5 0 1 Reserved (NAND) Low = JM41_CP(ZQ1B)
5
PCI_PIRQB# 7 4 PCI_PIRQH#
PCI_PLTRST# 2 PCI_REQ3# 8 3 PCI_TRDY# 1 0 PCI High = 80port output to LPC
4 PCI_PIRQD# 9 2 PCI_FRAME# BOARD_ID2
PLTRST# (4,11,27,28,31,35)
1 +3V 10 1 PCI_REQ1# R247 10K_4 dGPU_SELECT# 1 1 SPI Low = 80port output to PCI
A R262 8.2K_4 PCI_PIRQE#
(35) 2ND_MBDATA
U18 R331 8.2K_10P8R R518 8.2K_4 PCI_PIRQF# High = Reserved
3
TC7SH08FU R263 8.2K_4 PCI_PIRQG# BOARD_ID3

100K_4 Danbury Technology Enabled Low = Reserved (Default)
+3V
RP1 High = Enable
PCI_PLOCK# 6 5 NV_ALE +3V_S5
PCI_SERR# 7 4 PCI_PERR# Low = Disable
PCI_DEVSEL# 8 3 PCI_PIRQC# +3V_S5 R613 10K_4 RSV_SMBALERT#
PCI_STOP# 9 2 PCI_IRDY# R359 10K_4 RSV_SML0ALERT#
+3V 10 1 PCI_PIRQA# R617 IV@10K_4 PEG_CLKREQ#_R R320 10K_4 RSV_SML1ALERT#
DMI Termination Voltage R306 2.2K_4 ICH_SMBCLK
8.2K_10P8R R618 SW@10K_4 R318 2.2K_4 ICH_SMBDATA
Set to Vcc when LOW
NV_CLE R614 2.2K_4 SMB_CLK_ME0 Size Document Num
Set to Vcc/2 when HIGH R360 2.2K_4 SMB_DATA_ME0
IBEX PE
Date: Tuesday, Marc
5 4 3 2
1
ICH_SMBCLK (3,16,28)
ICH_SMBDATA (3,16,28)
SMB_CLK_ME0 (27) For LAN

SMB_DATA_ME0 (27)
*0_4
SML1ALERT# (11,34,35)
For EC
CL_CLK1 (28)
CL_DATA1 (28)
CL_RST1# (28)
*SW@0_4
PEG_CLKREQ# (18)
PEG_A_CLKRQ# PD for FreeRun, due GPU not support.
CLK_PCIE_VGA# (17)
CLK_PCIE_VGA (17)
CLK_PCIE_3GPLL# (4)
CLK_PCIE_3GPLL (4)
DPLL_REF_SSCLK# (4)
DPLL_REF_SSCLK (4)
CLK_BUF_PCIE_3GPLL# (3) C
CLK_BUF_PCIE_3GPLL (3)
CLK_BUF_BCLK# (3)
CLK_BUF_BCLK (3)
CLK_BUF_DREFCLK# (3)
CLK_BUF_DREFCLK (3)
CLK_BUF_DREFSSCLK# (3)
CLK_BUF_DREFSSCLK (3)
CLK_ICH_14M (3)
C3B C695 10P/50V_4
2
R512 Y4
25MHz
1
1M_4
90.9/F_4 +1.05V C696 10P/50V_4
B-test
No stuff XTAL25_IN and XTAL25_OUT circuitry

until integrated CG becomes PCH POR.
INTEL FAE: If having UMA digital display
(eDP/DP/DVI/HDMI), then 25MHz is required.
B
dGPU_EDIDSEL# (25)
4 +3V
move is OK
B-test
+3V_S5
R332
2
Q18 2N7002K 2.2K_4
1 3 SMB_CLK_ME1
B-test
+3V_S5
R328
2
Q19 2N7002K 2.2K_4
SMB_DATA_ME1 A
1 3

PROJECT : ZQ1
ment Number Rev
1A
X PEAK-M 3/6
ay, March 30, 2010 Sheet 10 of 48
1
5 4 3 2
GPU RST#(CLG)
PCH4(CLG) IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)
U35F
C3C
BMBUSY# Y3 AH45 +3V
BMBUSY# / GPIO0 CLKOUT_PCIE6N
CLKOUT_PCIE6P AH46
SIO_EXT_SMI# C38 1/21 ramp remove CLK TP C469 *SW
(35) SIO_EXT_SMI# TACH1 / GPIO1
(35) SIO_EXT_SCI# SIO_EXT_SCI# D37 TACH2 / GPIO6
5
CLKOUT_PCIE7N AF48 1
MISC
BOARD_ID0 J32 AF47 (17) GPU_RST# 4
TACH3 / GPIO7 CLKOUT_PCIE7P dGPU_
2
D RSV_GPIO8 F10 U19
(9) RSV_GPIO8
3
GPIO8 SW@TC7SH08FU
TP29 LAN_DISABLE# K9 U2
LAN_PHY_PWR_CTRL / GPIO12 A20GATE SIO_A20GATE (35)
(9) CR_WAKE# CR_WAKE# T7 GPIO15

dGPU_HOLD_RST# AA2 AM3
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# (4)
(20) dGPU_PWROK F38 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_CPU_BCLK (4)
GPIO22 Y7 BG10 PCH_PECI_R R556 *Short_4
SCLOCK / GPIO22 PECI H_PECI (4)
GPIO
H10 T1 B-test
TP28 GPIO24 RCIN# SIO_RCIN# (35)
GPIO24 NC for Intel suggestion at 6/1
TP25 GPIO27 AB12 BE10
GPIO27 PROCPWRGD H_PWRGOOD (4,16)
CPU
TP_PCH_GPIO28 V13 BD10 PCH_THRMTRIP#_R R313 56/F_4
GPIO28 THRMTRIP# PM_THRMTRIP# (4)
STP_PCI# M11 R321 56/F_4 +1.1V_VTT
STP_PCI# / GPIO34
(20,41) dGPU_VRON V6 SATACLKREQ# / GPIO35

dGPU_PWR_EN# should be stable (36) dGPU_PWR_EN# dGPU_PWR_EN# AB7 BA22 TP1_PCH TP23
SATA2GP / GPIO36 TP1
before dGPU_VRON enable
dGPU_PRSNT# TP2_PCH TP19
AB13 SATA3GP / GPIO37 TP2 AW22
GPIO Pull-up/Pull-down(C
GPIO38 V3 BB22
SLOAD / GPIO38 TP3
SAVE_LED# P3 AY45
SDATAOUT0 / GPIO39 TP4
C GPIO45 H3 AY46
PCIECLKRQ6# / GPIO45 TP5
(16) RST_GATE# F1 AV43 TP_PCH_GPIO28 R347

PCIECLKRQ7# / GPIO46 TP6 GPIO45 R616
B-test SV_SET_UP AB6 AV45 RST_GATE# R597
SDATAOUT1 / GPIO48 TP7
(10,34,35) SML1ALERT# R607 *Short_4 SATA5GP AA4 AF13 LAN_DISABLE# R307

SATA5GP / GPIO49 TP8
EC suggestion use GPIO49 for FAN control GPIO57 F8 M18
GPIO57 TP9
N18 SIO_EXT_SMI# R244
TP10 SIO_EXT_SCI# R270
A4 VSS_NCTF_1 TP11 AJ24
A49 dGPU_PWR_EN# R335
NCTF
VSS_NCTF_2 RSVD
SATA5GP / GPIO49 / TEMP_ALERT# is used to A5 VSS_NCTF_3 TP12 AK41
alert for EC when CPU or Graph/Memory A50 VSS_NCTF_4
A52 VSS_NCTF_5 TP13 AK42
controllers' temperature go out of limit. A53 VSS_NCTF_6
So connecting GPIO49 to EC and avoid this B2 VSS_NCTF_7 TP14 M32
B4 SIO_RCIN# R602
pin to be used for other purpose B52
VSS_NCTF_8
N32 SIO_A20GATE R623
VSS_NCTF_9 TP15 dGPU_HOLD_RST# R626
B53 VSS_NCTF_10
BE1 M30 SATA5GP R606
VSS_NCTF_11 TP16 GPIO22 R336
BE53 VSS_NCTF_12
BF1 VSS_NCTF_13 TP17 N30
BF53 SAVE_LED# R600
VSS_NCTF_14 STP_PCI# R358
BH1 VSS_NCTF_15 TP18 H12
BH2 VSS_NCTF_16
BH52 AA23 GPIO38 R625
VSS_NCTF_17 TP19
BH53 VSS_NCTF_18
BJ1 AB45 BMBUSY# R604
B VSS_NCTF_19 NC_1
BJ2 VSS_NCTF_20
BJ4 AB38 SV_SET_UP R343
VSS_NCTF_21 NC_2
BJ49 VSS_NCTF_22
BJ5 VSS_NCTF_23 NC_3 AB42
BJ50 VSS_NCTF_24
SV_SET_UP 1-X High
BJ52 VSS_NCTF_25 NC_4 AB41
BJ53 VSS_NCTF_26
D1 VSS_NCTF_27 NC_5 T39
D2 GPIO57 stuff PD and not stuf
VSS_NCTF_28
D53 VSS_NCTF_29
E1 P6 TP_INT3_3V GPIO57
VSS_NCTF_30 INIT3_3V# TP34
E53 VSS_NCTF_31
TP24 C10
IbexPeak-M_R1P0 +3V
R283 10K_4 BOA
R334 IV@10K_4 dGP
H
BOARD_ID0
L
H
A RSV_GPIO8
L
Quan
PROJE
IBEX PEAK-M 4/6
5 4 3 2
1
*SW@0.1u/10V_4
PLTRST# (4,10,27,28,31,35)
dGPU_HOLD_RST#
D
R341
SW@100K_4
wn(CLG)
+3V_S5
R347 10K_4
R616 10K_4
R597 10K_4
R307 10K_4
+3V
R244 10K_4
R270 10K_4
R335 10K_4
remove GPIO7 PU at 6/1
+3V
R602 10K_4
R623 10K_4
R626 *10K_4
R606 10K_4
R336 10K_4
R600 10K_4
R358 10K_4
R625 10K_4
R604 8.2K_4
B
R343 10K_4
igh = Strong (Default)
stuff PU for Intel suggestion at 6/1
R324 10K_4
B-test
BOARD_ID0 R279 *10K_4
dGPU_PRSNT# R333 SW@10K_4
High = JV41/JM41
Low = JM51
High = Disable
A
Low = Enable
uanta Computer Inc.

OJECT : ZQ1
Rev
1A
6
Sheet 11 of 48
1
5 4 3 2
C3C
PCH5(CLG) U35G POWER VCCADAC= 69mA(15mils)
+1.05V R529 *Short_8 +1.05V_VCCCORE_ICH AB24 AE50 +VCCA_DAC_1_2 L23 +3V
R526 *Short_8 VCCCORE[1] VCCADAC[1] PBY160808T-181Y-N/2A/180ohm_6
AB26
VCCCORE[2]
AB28 AE52
C434 1u/6.3V_4 VCCCORE[3] VCCADAC[2] C394 C390 C393
VCCCORE(+1.05V) = 1.432A(80mils) AD26
VCCCORE[4]
CRT
AD28 AF53
C721 10u/6.3V_6 AF26
VCCCORE[5]
VCCCORE[6]
VSSA_DAC[1] 0.01u/16V_4 22u/6.3V_8 0.1u/10V_4 U35J POWER
VCC CORE
AF28
VCCCORE[7] VSSA_DAC[2]
AF51 VCCACLK= 52mA(15mils)
AF30 C-test
+1.05V L48 *10uH/100mA_8 +V1.1LAN_VCCA_CLK AP51 V24 VCCIO
VCCCORE[8] C704 *10u/6.3V_6 VCCACLK[1] VCCIO[5]
AF31 VCCALVDS= 1mA V26
IBEX PEAK-M (POWER) AH26
AH28
VCCCORE[9]
VCCCORE[10]
VCCALVDS R230 *Short_4 +3V C705 *1u/6.3V_4 AP53
VCCACLK[2]
VCCIO[6]
VCCIO[7]
Y24
Y26
C441 1u/6.3V
VCCCORE[11] C3C VCCIO[8]
AH30
VCCCORE[12]
VCCLAN = 320mA(30mils)
AH31 AH38 C397 +1.05V R286 *0_6 +1.05V_VCCAUX AF23 V28 +3V_S5_VCC
D VCCCORE[13] VCCALVDS 0.1u/10V_4 VCCLAN[1] VCCSUS3_3[1]
AJ30 U28
VCCCORE[14] VCCSUS3_3[2] C437
AJ31 VCCCORE[15] VSSA_LVDS AH39 AF24 VCCLAN[2] VCCSUS3_3[3] U26
C445 U24
For power saving, VCCSUS3_3[4] 0.022u_4
VCCTX_LVDS= 59mA(15mils) VCCSUS3_3[5]
P28
AP43 VCCTX_LVDS L25 0.1uH/250mA_8 +1.8V connect to GND 0_4 TP_PCH_VCCDSW Y20 P26
C3C VCCTX_LVDS[1] DCPSUSBYP VCCSUS3_3[6]
AP45 N28
VCCTX_LVDS[2] C406 C403 C402 C448 VCCSUS3_3[7]
AT46 N26
LVDS
R292 *Short_6 +1.05V_PCH_VCCDPLL_EXP VCCTX_LVDS[3] C3C VCCSUS3_3[8]
+1.05V AK24 AT45 AD38 M28
VCCIO[24] VCCTX_LVDS[4] 0.01u/16V_4 0.1u/10V_4 10u/6.3V_6 0.1u/10V_4 VCCME[1] VCCSUS3_3[9]
M26
VCCSUS3_3[10]
AD39 L28
USB
L55 *1uH/25mA_6 +V1.1LAN_VCCAPLL_EXP 10/5 modify VCCME[2] VCCSUS3_3[11]
40mA(15mils) +1.05V BJ24
VCCAPLLEXP VCCSUS3_3[12]
L26
AB34 AD41 J28
C756 *10u/6.3V_6 VCC3_3[2] VCCME[3] VCCSUS3_3[13]
VCCSUS3_3[14] J26
AN20
VCCIO[25] VCC3_3[3]
AB35 VCC3_3 = 357mA(30mils) AF43
VCCME[4] VCCSUS3_3[15]
H28
AN22 H26
HVCMOS
VCCIO[26] +3V_VCC_GIO R271 VCCSUS3_3[16]
AN23
VCCIO[27] VCC3_3[4]
AD35 +3V VCCME(+1.05V) = 1.849A(100mils) AF41
VCCME[5] VCCSUS3_3[17]
G28
AN24 PBY160808T-121Y-N/2.5A/120ohm_6 G26
VCCIO[28] C416 R246 *Short_8 +1.05V_VCCEPW VCCSUS3_3[18]
VCCIO = 3.062A(150mils) AN26 VCCIO[29] +1.05V AF42 VCCME[6] VCCSUS3_3[19] F28
AN28 B-test F26
R539 *Short_8 VCCIO VCCIO[30] 0.1u/10V_4 R238 *Short_8 C396 22u/6.3V_8 VCCSUS3_3[20]
+1.05V BJ26 V39 E28
VCCIO[31] VCCME[7] VCCSUS3_3[21]
Clock and Miscellaneous

R540 *Short_8 BJ28 E26
VCCIO[32] C3C C401 22u/6.3V_8 VCCSUS3_3[22]
AT26 V41 C28
C3C VCCIO[33] VCCME[8] VCCSUS3_3[23]
AT28 VCCIO[34] VCCSUS3_3[24] C26
AU26 C408 1u/6.3V_4 V42 B27
C442 1u/6.3V_4 VCCIO[35] VCCME[9] VCCSUS3_3[25]
AU28 VCCIO[36]
VCCVRM= 196mA(15mils) VCCSUS3_3[26] A28
AV26 C421 1u/6.3V_4 Y39 A26
C430 1u/6.3V_4 VCCIO[37] +VCCVRM R294 *Short_6 VCCME[10] VCCSUS3_3[27]
AV28 VCCIO[38] VCCVRM[2] AT24 +V1.5S_1.8S
AW26 Y41 U23
C429 1u/6.3V_4 VCCIO[39] C3C VCCME[11] VCCSUS3_3[28]
AW28
VCCIO[40]
DMI
BA26 AT16 +VCCDM R322 *Short_4 +1.1V_VTT VCCDMI= 61mA(15mils) Y42 V23 VCCIO
C443 1u/6.3V_4 VCCIO[41] VCCDMI[1] VCCME[12] VCCIO[56]
BA28
VCCIO[42] R323 *0_4
BB26 VCCIO[43] VCCDMI[2] AU16 +1.05V V5REF_SUS F24
C C427 10u/6.3V_6 BB28 VCCIO[44] +VCCRTCEXT C418
BC26 V9
VCCIO[45] DCPRTC
PCI E*
BC28 C457 C464 0.1u/10V_4 1u/10V_6
VCCIO[46] 1u/6.3V_4
BD26
VCCIO[47]
BD28 K49
VCCIO[48] V5REF
BE26 AM16 AU24
PCI/GPIO/LPC
VCCIO[49] VCCPNAND[1] +V1.5S_1.8S VCCVRM[3]
BE28
VCCIO[50] VCCPNAND[2]
AK16 VCCPNAND= 156mA(15mils)
BG26 AK20 J38 C398
VCCIO[51] VCCPNAND[3] VCCPNAND R325 *Short_8 VCC3_3[8] 1u/10V_6
BG28 AK19 +1.8V BB51
VCCIO[52] VCCPNAND[4] +V1.1LAN_VCCA_A_DPL VCCADPLLA[1]
BH27 VCCIO[53] VCCPNAND[5] AK15 68mA(15mils) BB53 VCCADPLLA[2] VCC3_3[9] L38
AK13 C458 C3C
VCCPNAND[6] +3V_VCCPPCI
AN30 AM12 M36
VCCIO[54] VCCPNAND[7] VCC3_3[10]
NAND / SPI
VRM enable by strap pin GPIO27 AN31 AM13 0.1u/10V_4 69mA(15mils) +V1.1LAN_VCCA_B_DPL BD51
VCCIO[55] VCCPNAND[8] VCCADPLLB[1]
AM15 BD53 N36
which supply clean 1.05V for VCCPNAND[9] VCCADPLLB[2] VCC3_3[11]
[VCCACLK,VCCAPLLEXP,VCCFDIPLL,VCCSATAPLL] +3V AN35 VCCIO AH23 P36 C419
VCC3_3[1] VCCIO[21] VCC3_3[12] 0.1u/10V_4
AJ35
VCCIO[22]
AH35 U35
C415 1u/6.3V_4 VCCIO[23] VCC3_3[13]
37mA(15mils) +V1.5S_1.8S AT22
VCCVRM[1]
VCCME3_3= 85mA(15mils) C428 1u/6.3V_4 AF34
L56 *1uH/25mA_6 +V1.1LAN_VCCAPLL_FDI C452 1u/6.3V_4 VCCIO[2]
+1.05V BJ18 AM8 AD13
VCCFDIPLL VCCME3_3[1] +3V_VCCME_SPI R314 *Short_6 VCC3_3[14]
AM9 +3V AH34
VCCME3_3[2] VCCIO[3]
FDI
VCCIO AM23 AP11 C414

C763 VCCIO[1] VCCME3_3[3] C461 C3C 0.1u/10V_4
AP9 AF32
*10u/6.3V_6 VCCME3_3[4] VCCIO[4]
AK3
0.1u/10V_4 C460 0.1u/10V_4 +VCCSST VCCSATAPLL[1] +V1.1LA
V12 DCPSST VCCSATAPLL[2] AK1
IbexPeak-M_R1P0 C799 C8
*1u/6.3V_4 *10
+V1.1LAN_INT_VCCSUS Y22
C447 0.1u/10V_4 DCPSUS
VCCIO[9] AH22
B
P18 AT20 +V1.5S_1.
VCCSUS3_3[29] VCCVRM[4]
VCCSUS3_3 = 163mA(20mils)
+3V_S5 R338 *Short_6 +3V_S5_VCCPSUS U19
SATA
VCCSUS3_3[30]
PCI/GPIO/LPC
VCCVRM=196mA(15mils) HDA_SYNC (PCH strap pin) VCCIO[10]
AH19
C3C C453 0.1u/10V_4 U20
R309 *Short_6 VCCSUS3_3[31]
+1.8V +V1.5S_1.8S Internal weak pull-down VCCIO[11]
AD20
VCCVRM=>+1.8V (default) U22
C3C VCCSUS3_3[32]
external pull-up AF22
C446 C450 VCCIO[12]
*0.1u/10V_4 *0.1u/10V_4 VCCVRM=>+1.5V VCC3_3 = 0.357A(30mils) AD19
R337 *Short_6 +3V_VCCPCORE VCCIO[13]
+3V V15 AF20
VCC3_3[5] VCCIO[14]
AF19
C3C C454 VCCIO[15]
V16 AH20
VCC3_3[6] VCCIO[16]
0.1u/10V_4 Y16 AB19
VCC3_3[7] VCCIO[17]
AB20
VCCIO[18]
AB22
VCCIO[19]
V_CPU_IO >1mA(15mils) VCCIO[20] AD22
+1.1V_VTT R578 *Short_6 +VTT_VCCPCPU AT18
L46 10uH/100mA_8 +V1.1LAN_VCCA_A_DPL V_CPU_IO[1] +1.05V_VCCEPW
AA34
CPU
+1.05V VCCME[13]
C3C C785 4.7u/10V_8 Y34
+ C703 C451 0.1u/10V_4 VCCME[14]
AU18 Y35
C693 C455 0.1u/10V_4 V_CPU_IO[2] VCCME[15]
AA35
220u/2.5V_3528 *1u/6.3V_4 VCCME[16]
VCCRTC= 2mA(15mils)
RTC
+VCCRTC A12 L30 +V3.3A_1.5A_HDA_IO
VCCRTC VCCSUSHDA
HDA
L49 10uH/100mA_8 +V1.1LAN_VCCA_B_DPL
C775 C784
+ C715 IbexPeak-M_R1P0 C433
C717 0.1u/10V_4 0.1u/10V_4 1u/6.3V_4
220u/2.5V_3528 *1u/6.3V_4
A
10/5 modify

IBEX PEAK
5 4 3 2
1
CCIO
1u/6.3V_4
VCCSUS3_3 = 0.163A(20mils)
_S5_VCCPUSB R288 *Short_6 +3V_S5
D
37 C436 C440 C3C
022u_4 0.1u/10V_4 0.1u/10V_4
V5REF_SUS< 1mA
R264 100/F_4 +5V_S5
C
18 D5 RB500V-40 +3V_S5
/10V_6
V5REF< 1mA
R239 100/F_4 +5V
D3 RB500V-40 +3V
98
/10V_6
C3C
CI R269 *Short_6 +3V
VCC3_3 = 0.357A(30mils)
19
1u/10V_4
+3V
14
1u/10V_4 31mA(15mils)
+V1.1LAN_VCCAPLL L59 *10uH/100mA_8 +1.05V
C801
*10u/6.3V_6
VCCIO
1.5S_1.8S C449
1u/6.3V_4
VCCME = 1.849A(100mils)
CCEPW
C3C B-test
A_IO R252 *Short_4 +3V_S5
VCCSUSHDA= 6mA(15mils)
3V_4

PROJECT : ZQ1
Number Rev
1A
PEAK-M 5/6
1
5 4 3 2 1
PCH6(CLG)
U35I
AY7 H49
IBEX PEAK-M (GND) B11
B15
VSS[159]
VSS[160]
VSS[259]
VSS[260]
H5
J24
VSS[161] VSS[261]
D B19 VSS[162] VSS[262] K11 D
B23 VSS[163] VSS[263] K43
B31 VSS[164] VSS[264] K47
B35 VSS[165] VSS[265] K7
B39 VSS[166] VSS[266] L14
B43 VSS[167] VSS[267] L18
B47 VSS[168] VSS[268] L2
B7 L22
VSS[169] VSS[269]
BG12 VSS[170] VSS[270] L32
BB12 L36
U35H VSS[171] VSS[271]
BB16 L40
VSS[172] VSS[272]
AB16 BB20 L52
VSS[0] VSS[173] VSS[273]
BB24 M12
VSS[174] VSS[274]
AA19 AK30 BB30 M16
VSS[1] VSS[80] VSS[175] VSS[275]
AA20 VSS[2] VSS[81] AK31 BB34 VSS[176] VSS[276] M20
AA22 VSS[3] VSS[82] AK32 BB38 VSS[177] VSS[277] N38
AM19 VSS[4] VSS[83] AK34 BB42 VSS[178] VSS[278] M34
AA28 VSS[7] VSS[86] AK43 BC10 VSS[181] VSS[281] M46
AB11 VSS[11] VSS[90] AK8 BC22 VSS[185] VSS[285] N24
AB15 AL2 BC32 P11
VSS[12] VSS[91] VSS[186] VSS[286]
AB23 AL52 BC36 AD15
VSS[13] VSS[92] VSS[187] VSS[287]
AB30 AM11 BC40 P22
VSS[14] VSS[93] VSS[188] VSS[288]
AB31 BB44 BC44 P30
VSS[15] VSS[94] VSS[189] VSS[289]
AB32 AD24 BC52 P32
VSS[16] VSS[95] VSS[190] VSS[290]
AB39 AM20 BH9 P34
VSS[17] VSS[96] VSS[191] VSS[291]
AB43 VSS[18] VSS[97] AM22 BD48 VSS[192] VSS[292] P42
C C
AB8 VSS[21] VSS[100] AM28 BE12 VSS[195] VSS[295] R2
AC2 VSS[22] VSS[101] BA42 BE16 VSS[196] VSS[296] R52
AC52 VSS[23] VSS[102] AM30 BE20 VSS[197] VSS[297] T12
AD11 VSS[24] VSS[103] AM31 BE24 VSS[198] VSS[298] T41
AD23 AM35 BE38 T5
VSS[27] VSS[106] VSS[201] VSS[301]
AD30 AM38 BE42 T8
VSS[28] VSS[107] VSS[202] VSS[302]
AD31 AM39 BE46 U30
VSS[29] VSS[108] VSS[203] VSS[303]
AD32 AM42 BE48 U31
VSS[30] VSS[109] VSS[204] VSS[304]
AD34 AU20 BE50 U32
VSS[31] VSS[110] VSS[205] VSS[305]
AU22 AM46 BE6 U34
VSS[32] VSS[111] VSS[206] VSS[306]
AD42 VSS[33] VSS[112] AV22 BE8 VSS[207] VSS[307] P38
AD46 VSS[34] VSS[113] AM49 BF3 VSS[208] VSS[308] V11
AD49 VSS[35] VSS[114] AM7 BF49 VSS[209] VSS[309] P16
AD7 VSS[36] VSS[115] AA50 BF51 VSS[210] VSS[310] V19
AE2 VSS[37] VSS[116] BB10 BG18 VSS[211] VSS[311] V20
AE4 VSS[38] VSS[117] AN32 BG24 VSS[212] VSS[312] V22
AF12 VSS[39] VSS[118] AN50 BG4 VSS[213] VSS[313] V30
Y13 VSS[40] VSS[119] AN52 BG50 VSS[214] VSS[314] V31
AH49 AP12 BH11 V32
VSS[41] VSS[120] VSS[215] VSS[315]
AU4 AP42 BH15 V34
VSS[42] VSS[121] VSS[216] VSS[316]
AF35 AP46 BH19 V35
VSS[43] VSS[122] VSS[217] VSS[317]
AP13 AP49 BH23 V38
VSS[44] VSS[123] VSS[218] VSS[318]
AN34 AP5 BH31 V43
VSS[45] VSS[124] VSS[219] VSS[319]
AF45 AP8 BH35 V45
VSS[46] VSS[125] VSS[220] VSS[320]
AF46 AR2 BH39 V46
VSS[47] VSS[126] VSS[221] VSS[321]
AF49 AR52 BH43 V47
VSS[48] VSS[127] VSS[222] VSS[322]
AF5 AT11 BH47 V49
VSS[49] VSS[128] VSS[223] VSS[323]
AF8 BA12 BH7 V5
B VSS[50] VSS[129] VSS[224] VSS[324] B
AG2 AH48 C12 V7
VSS[51] VSS[130] VSS[225] VSS[325]
AG52 VSS[52] VSS[131] AT32 C50 VSS[226] VSS[326] V8
AH11 VSS[53] VSS[132] AT36 D51 VSS[227] VSS[327] W2
AH15 VSS[54] VSS[133] AT41 E12 VSS[228] VSS[328] W52
AH16 AT47 E16 Y11
VSS[55] VSS[134] VSS[229] VSS[329]
AH24 VSS[56] VSS[135] AT7 E20 VSS[230] VSS[330] Y12
AH32 AV12 E24 Y15
VSS[57] VSS[136] VSS[231] VSS[331]
AV18 AV16 E30 Y19
VSS[58] VSS[137] VSS[232] VSS[332]
AH43 AV20 E34 Y23
VSS[59] VSS[138] VSS[233] VSS[333]
AH47 AV24 E38 Y28
VSS[60] VSS[139] VSS[234] VSS[334]
AH7 AV30 E42 Y30
VSS[61] VSS[140] VSS[235] VSS[335]
AJ19 AV34 E46 Y31
VSS[62] VSS[141] VSS[236] VSS[336]
AJ2 AV38 E48 Y32
VSS[63] VSS[142] VSS[237] VSS[337]
AJ20 AV42 E6 Y38
VSS[64] VSS[143] VSS[238] VSS[338]
AJ22 AV46 E8 Y43
VSS[65] VSS[144] VSS[239] VSS[339]
AJ23 AV49 F49 Y46
VSS[66] VSS[145] VSS[240] VSS[340]
AJ26 AV5 F5 P49
VSS[67] VSS[146] VSS[241] VSS[341]
AJ28 VSS[68] VSS[147] AV8 G10 VSS[242] VSS[342] Y5
AJ32 VSS[69] VSS[148] AW14 G14 VSS[243] VSS[343] Y6
AJ34 AW18 G18 Y8
VSS[70] VSS[149] VSS[244] VSS[344]
AT5 VSS[71] VSS[150] AW2 G2 VSS[245] VSS[345] P24
AJ4 BF9 G22 T43
VSS[72] VSS[151] VSS[246] VSS[346]
AK12 AW32 G32 AD51
VSS[73] VSS[152] VSS[247] VSS[347]
AM41 AW36 G36 AT8
VSS[74] VSS[153] VSS[248] VSS[348]
AN19 AW40 G40 AD47
VSS[75] VSS[154] VSS[249] VSS[349]
AK26 AW52 G44 Y47
VSS[76] VSS[155] VSS[250] VSS[350]
AK22 AY11 G52 AT12
VSS[77] VSS[156] VSS[251] VSS[351]
AK23 AY43 AF39 AM6
VSS[78] VSS[157] VSS[252] VSS[352]
AK28 AY47 H16 AT13
VSS[79] VSS[158] VSS[253] VSS[353]
H20 AM5
IbexPeak-M_R1P0 VSS[254] VSS[354]
H30 AK45
VSS[255] VSS[355]
A H34 AK39 A
VSS[256] VSS[356]
H38 VSS[257] VSS[366] AV14
H42 VSS[258]
IbexPeak-M_R1P0
PROJECT : ZQ1
Size Document Number Rev
1A
IBEX PEAK-M 6/6
5 4 3 2 1
D
v
A
5 4 3 2
DDR_STD(DDR) +1.5V_SUS
JDIM2B
JDIM2A M_A_DQ[63:0] (5)
(5) M_A_A[15:0] 75 VDD1 VSS16 44
M_A_A0 M_A_DQ0
M_A_A1
98
97
A0 DQ0 5
7 M_A_DQ1
2.48A 76
81
VDD2 VSS17 48
49
M_A_A2 A1 DQ1 M_A_DQ2 VDD3 VSS18
96 A2 DQ2 15 82 VDD4 VSS19 54
M_A_A3 95 17 M_A_DQ3 87 55
92 A4 DQ4 4 88 VDD6 VSS21 60
M_A_A5 91 6 M_A_DQ5 93 61
90 A6 DQ6 16 94 VDD8 VSS23 65
M_A_A7 86 18 M_A_DQ7 99 66
D 89 A8 DQ8 21 100 VDD10 VSS25 71
M_A_A9 85 23 M_A_DQ9 105 72
PC2100 DDR3 SDRAM SO-DIMM

107 A10/AP DQ10 33 106 VDD12 VSS27 127
M_A_A11 84 35 M_A_DQ11 111 128
83 A12/BC# DQ12 22 112 VDD14 VSS29 133
M_A_A13 119 24 M_A_DQ13 117 134
80 A14 DQ14 34 118 VDD16 VSS31 138
M_A_A15 78 36 M_A_DQ15 123 139
A15 DQ15 M_A_DQ16 VDD17 VSS32
39 124 144

DQ16 M_A_DQ17 VDD18 VSS33
(5) M_A_BS#0 109 BA0 DQ17 41 VSS34 145
108 51 M_A_DQ18 199 150
(5) M_A_BS#1 BA1 DQ18 +3V VDDSPD VSS35
79 53 M_A_DQ19 151
(5) M_A_BS#2 BA2 DQ19 VSS36
114 40 M_A_DQ20 77 155
(5) M_A_CS#0 S0# DQ20 NC1 VSS37
121 42 M_A_DQ21 122 156
(5) M_A_CS#1 S1# DQ21 M_A_DQ22 NC2 VSS38
101 50 R219 *10K_4 125 161
(5) M_A_CLK0 CK0 DQ22 +3V NCTEST VSS39
103 52 M_A_DQ23 162
(5) M_A_CLK0# CK0# DQ23 VSS40
102 57 M_A_DQ24 198 167
(5) M_A_CLK1 CK1 DQ24 M_A_DQ25 (4) PM_EXTTS#0 EVENT# VSS41
(5) M_A_CLK1# 104 CK1# DQ25 59 (15,16) DDR3_DRAMRST# 30 RESET# VSS42 168
73 67 M_A_DQ26 172
(5) M_A_CKE0 CKE0 DQ26 VSS43
74 69 M_A_DQ27 173
(5) M_A_CKE1 CKE1 DQ27 VSS44
115 56 M_A_DQ28 +SMDDR_VREF_DQ0 1 178
(5) M_A_CAS# CAS# DQ28 VREF_DQ VSS45
110 58 M_A_DQ29 +SMDDR_VREF_DIMM 126 179
(5) M_A_RAS# RAS# DQ29 VREF_CA VSS46
113 68 M_A_DQ30 184
(5) M_A_WE# W E# DQ30 VSS47
R214 10K_4 DIMM0_SA0 197 70 M_A_DQ31 185
R215 10K_4 DIMM0_SA1 SA0 DQ31 M_A_DQ32 VSS48
201 SA1 DQ32 129 2 VSS1 VSS49 189
CLK_SCLK 202 131 M_A_DQ33 3 190
(3,15,28) CLK_SCLK CLK_SDATA SCL DQ33 M_A_DQ34 VSS2 VSS50
200 141 8 195
(204P)
(3,15,28) CLK_SDATA SDA DQ34 M_A_DQ35 VSS3 VSS51
C DQ35 143 9 VSS4 VSS52 196
116 130 M_A_DQ36 13
(5) M_A_ODT0 ODT0 DQ36 M_A_DQ37 VSS5
(5) M_A_ODT1 120 ODT1 DQ37 132 14 VSS6
140 M_A_DQ38 19
(5) M_A_DM[7:0] DQ38 VSS7
M_A_DM0 11 142 M_A_DQ39 20
M_A_DM1 DM0 DQ39 M_A_DQ40 VSS8
28 DM1 DQ40 147 25 VSS9
M_A_DM2 46 149 M_A_DQ41 26 203
M_A_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_A_DQ42 +1.5V_SUS 31
VSS10
VSS11
VTT1
VTT2 204
M_A_DM4 136 159 M_A_DQ43 32
M_A_DM5 DM4 DQ43 M_A_DQ44 VSS12
153 DM5 DQ44 146 37 VSS13 GND 205
M_A_DM6 170 148 M_A_DQ45 38 206
M_A_DM7 DM6 DQ45 M_A_DQ46 R172 VSS14 GND
187 DM7 DQ46 158 43 VSS15
160 M_A_DQ47 10K/F_4
(5) M_A_DQS[7:0] DQ47
M_A_DQS0 12 163 M_A_DQ48
M_A_DQS1 DQS0 DQ48 M_A_DQ49 DDR3-DIMM0_H=4_STD
29 DQS1 DQ49 165
M_A_DQS2 47 175 M_A_DQ50 R173 *0_6 +SMDDR_VREF_DIMM
DQS2 DQ50 +SMDDR_VREF
M_A_DQS3 64 177 M_A_DQ51
M_A_DQS4 DQS3 DQ51 M_A_DQ52
137 DQS4 DQ52 164
M_A_DQS5 154 166 M_A_DQ53 R182 C338
M_A_DQS6 DQS5 DQ53 M_A_DQ54
171 DQS6 DQ54 174 10K/F_4 470p/50V_4
M_A_DQS7 188 176 M_A_DQ55
(5) M_A_DQS#[7:0] DQS7 DQ55
M_A_DQS#0 10 181 M_A_DQ56
M_A_DQS#1 DQS#0 DQ56 M_A_DQ57
27 DQS#1 DQ57 183
M_A_DQS#2 45 191 M_A_DQ58
62 DQS#3 DQ59 193
M_A_DQS#4 135 180 M_A_DQ60
152 DQS#5 DQ61 182
B M_A_DQS#6 169 192 M_A_DQ62
186 DQS#7 DQ63 194
DDR3-DIMM0_H=4_STD +1.5V_SUS
R117
10K/F
Place these Caps near So-Dimm0.
R120 *0_6 +SM
+SMDDR_VREF
+1.5V_SUS
+SMDDR_VREF_DIMM +SMDDR_VREF_DQ0 R11
C341 C286 C311 C287 C292 10K
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 0.1u/10V_4 0.1u/10V_4 R121 *0_6
(7) VREF_DQ_DIMM0
C335 + C333 C345 C346 C251 C250
330u/2V_7343
10u/6.3V_6 0.1u/10V_4 0.1u/10V_4
STD 4H STD 8H
C314 C326 C336 C316 C309 2.2u/6.3V_6 2.2u/6.3V_6
10u/6.3V_6 10u/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 M1:PWR SMDRR_VR
FOX
M1+:voltage div
A
+3V +0.75V_DDR_VTT LTK DGMK4000004 DGMK4000097 M3:CPU VREF_DQ_
SUY
C373 C375 C374 C372 C382 C371 C370
C365 C358 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 Quanta
2.2u/6.3V_6 0.1u/10V_4 *10u/6.3V_6 *10u/6.3V_6 10u/6.3V_6 MLX DGMK4000011 DGMK4000080
PROJECT
maybe can save Standard 4H type:DDR-C-2013289-204p Size Document Number
DDRIII SO-DIMM-0
5 4 3 2
1
+0.75V_DDR_VTT
SUS
R117
10K/F_4
+SMDDR_VREF_DQ0
R118
10K/F_4
R_VREF
divider(Default)
A
_DQ_DIMM0
nta Computer Inc.

ECT : ZQ1
Rev
1A
Sheet 14 of 48
1
5 4 3 2
DDR_STD(DDR) +1.5V_SUS
JDIM1A M_B_DQ[63:0] (5) JDIM1B
(5) M_B_A[15:0] M_B_A0 M_B_DQ0
98 A0 DQ0 5 75 VDD1 VSS16 4
M_B_A1 97 7 M_B_DQ1 76 4
M_B_A2 A1 DQ1 M_B_DQ2 VDD2 VSS17
96 A2 DQ2 15 81 VDD3 VSS18 4
M_B_A3 95 17 M_B_DQ3 82 5
92 A4 DQ4 4 87 VDD5 VSS20 5
M_B_A5 91 6 M_B_DQ5 88 6
90 A6 DQ6 16 93 VDD7 VSS22 6
M_B_A7 86 18 M_B_DQ7 94 6
D
M_B_A9
89
85
A8 DQ8 21
23 M_B_DQ9
2.48A 99
100
VDD9 VSS24 6
7
107 A10/AP DQ10 33 105 VDD11 VSS26 7
M_B_A11 M_B_DQ11

84 A11 DQ11 35 106 VDD12 VSS27 1
M_B_A12 83 22 M_B_DQ12 111 1
M_B_A13 A12/BC# DQ12 M_B_DQ13 VDD13 VSS28
119 A13 DQ13 24 112 VDD14 VSS29 1
M_B_A14 80 34 M_B_DQ14 117 1
78 A15 DQ15 36 118 VDD16 VSS31 1
39 M_B_DQ16 123 1

DQ16 M_B_DQ17 VDD17 VSS32
(5) M_B_BS#0 109 BA0 DQ17 41 124 VDD18 VSS33 1
108 51 M_B_DQ18 1
(5) M_B_BS#1 BA1 DQ18 VSS34
79 53 M_B_DQ19 199 1
(5) M_B_BS#2 BA2 DQ19 +3V VDDSPD VSS35
114 40 M_B_DQ20 1
(5) M_B_CS#0 S0# DQ20 VSS36
121 42 M_B_DQ21 77 1
(5) M_B_CS#1 S1# DQ21 M_B_DQ22 NC1 VSS37
(5) M_B_CLK0 101 CK0 DQ22 50 122 NC2 VSS38 1
103 52 M_B_DQ23 125 1
(5) M_B_CLK0# CK0# DQ23 NCTEST VSS39
102 57 M_B_DQ24 R210 *10K_4 1
(5) M_B_CLK1 CK1 DQ24 M_B_DQ25 +3V VSS40
(5) M_B_CLK1# 104 CK1# DQ25 59 (4) PM_EXTTS#1 198 EVENT# VSS41 1
73 67 M_B_DQ26 30 1
(5) M_B_CKE0 CKE0 DQ26 (14,16) DDR3_DRAMRST# RESET# VSS42
74 69 M_B_DQ27 1
(5) M_B_CKE1 CKE1 DQ27 VSS43
115 56 M_B_DQ28 1
(5) M_B_CAS# CAS# DQ28 VSS44
110 58 M_B_DQ29 +SMDDR_VREF_DQ1 1 1
(5) M_B_RAS# RAS# DQ29 VREF_DQ VSS45
113 68 M_B_DQ30 126 1
(5) M_B_WE# W E# DQ30 +SMDDR_VREF_DIMM VREF_CA VSS46
R218 10K_4 DIMM1_SA0 197 70 M_B_DQ31 1
R211 10K_4 DIMM1_SA1 SA0 DQ31 M_B_DQ32 VSS47
+3V 201 SA1 DQ32 129 VSS48 1
202 131 M_B_DQ33 2 1
(3,14,28) CLK_SCLK SCL DQ33 M_B_DQ34 VSS1 VSS49
200 SDA DQ34 141 3 VSS2 VSS50 1
(3,14,28) CLK_SDATA 143 M_B_DQ35 8 1
(204P)
C DQ35 VSS3 VSS51
116 130 M_B_DQ36 9 1
(5) M_B_ODT0 ODT0 DQ36 M_B_DQ37 VSS4 VSS52
(5) M_B_ODT1 120 ODT1 DQ37 132 13 VSS5
140 M_B_DQ38 14
(5) M_B_DM[7:0] DQ38 VSS6
M_B_DM0 11 142 M_B_DQ39 19
M_B_DM1 DM0 DQ39 M_B_DQ40 VSS7
28 DM1 DQ40 147 20 VSS8
M_B_DM2 46 149 M_B_DQ41 25
M_B_DM3 63
DM2
DM3
(204P) DQ41
DQ42 157 M_B_DQ42 26
VSS9
VSS10 VTT1 2
M_B_DM4 136 159 M_B_DQ43 31 2
M_B_DM5 DM4 DQ43 M_B_DQ44 VSS11 VTT2
153 DM5 DQ44 146 32 VSS12
M_B_DM6 170 148 M_B_DQ45 37 2
M_B_DM7 DM6 DQ45 M_B_DQ46 VSS13 GND
187 DM7 DQ46 158 38 VSS14 GND 2
160 M_B_DQ47 43
(5) M_B_DQS[7:0] DQ47 VSS15
M_B_DQS0 12 163 M_B_DQ48
M_B_DQS1 DQS0 DQ48 M_B_DQ49
29 DQS1 DQ49 165
M_B_DQS2 47 175 M_B_DQ50 DDR3-DIMM1_H=8_STD
64 DQS3 DQ51 177
M_B_DQS4 137 164 M_B_DQ52
154 DQS5 DQ53 166
M_B_DQS6 171 174 M_B_DQ54
(5) M_B_DQS#[7:0] 188 DQS7 DQ55 176
M_B_DQS#0 10 181 M_B_DQ56
M_B_DQS#1 DQS#0 DQ56 M_B_DQ57
27 DQS#1 DQ57 183
M_B_DQS#2 45 191 M_B_DQ58
62 DQS#3 DQ59 193
M_B_DQS#4 135 180 M_B_DQ60
152 DQS#5 DQ61 182
B M_B_DQS#6 169 192 M_B_DQ62
186 DQS#7 DQ63 194
+1.5V_SU
DDR3-DIMM1_H=8_STD
R4
10
+1.5V_SUS Place these Caps near So-Dimm1.

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1 R405 *0_6
+SMDDR_VREF
C308 C285 C332 C340 C339
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6 0.1u/10V_4 0.1u/10V_4
R
C294 + C337 C342 C343 C549 C550 1
330u/2V_7343 R406 *0_6
(7) VREF_DQ_DIMM1
10u/6.3V_6 0.1u/10V_4 0.1u/10V_4
C323 C300 C330 C302 C324 2.2u/6.3V_6 2.2u/6.3V_6

10u/6.3V_6 10u/6.3V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
+3V +0.75V_DDR_VTT STD 4H STD 8H M1:PWR SMDRR_V

M1+:voltage di
FOX
A C381 C379 C380 C378 C369 C363 C364 M3:CPU VREF_DQ
C359 C360 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
2.2u/6.3V_6 0.1u/10V_4 *10u/6.3V_6 *10u/6.3V_6 10u/6.3V_6 LTK DGMK4000004 DGMK4000097
SUY
maybe can save Quanta
MLX DGMK4000011 DGMK4000080 PROJECT
Standard 8H type:DDR-C-2013310-204p-1 DDRIII SO-DIMM-1
5 4 3 2
1
16 44
17 48
18 49
19 54
20 55
21 60
22 61
23 65
24 66 D
25 71
26 72
27 127
28 128
29 133
30 134
31 138
32 139
33 144
34 145
35 150
36 151
37 155
38 156
39 161
40 162
41 167
42 168
43 172
44 173
45 178
46 179
47 184
48 185
49 189
50 190
51 195 C
52 196
T1 203 +0.75V_DDR_VTT
T2 204
D 205
D 206
V_SUS
R407
10K/F_4
+SMDDR_VREF_DQ1
R408
10K/F_4
RR_VREF
e divider(Default)
F_DQ_DIMM0 A
nta Computer Inc.

ECT : ZQ1
Rev
1A
Sheet 15 of 48
1
1 2 3 4 5 6 7
CPU XDP Connector(CPU) S3 leakage solution(CLG)

+3V_S5
+3V_S5
R503
*10K_4
5
U31
200mA R504 2 R507
CN13 *10K_4 4 R513 *Short_4
3
(4) XDP_PREQ# T42 3 44 1
OBSFN_A0 VCC_OBS_CD *1.5K/F_4 C3C
(4) XDP_PRDY# T96 5 43
OBSFN_A1 VCC_OBS_AB +1.5V_CPUVDDQ *TC7SH08FU R508
A
T30 9 21
3
(4) XDP_OBS0 OBSDATA_A0 OBSFN_B0
(4) XDP_OBS1 T36 11 23 2
OBSDATA_A1 OBSFN_B1
(4) XDP_OBS2 T34 15 4
OBSDATA_A2 OBSFN_C0
3
T33 17 6 Q32
(4) XDP_OBS3 OBSDATA_A3 OBSFN_C1
T35 27 10 *2N7002K *750/F_4
(4) XDP_OBS4 OBSDATA_B0 OBSDATA_C0 B-test
T32 29 12 2 Q31
1
(4) XDP_OBS5 OBSDATA_B1 OBSDATA_C1
(4) XDP_OBS6 T39 33 16
OBSDATA_B2 OBSDATA_C2 *PDTC143TT
(4) XDP_OBS7 T31 35 18
PM_PWRBTN#_R OBSDATA_B3 OBSDATA_C3
(8) PM_PWRBTN#_R T113 41 22
1
HOOK1 OBSFN_D0 PWRGD_1.5VCPU (40)
R184 *0_4 T48 45 24
(4) H_PWRGD_XDP HOOK2 OBSFN_D1
(4) BCLK_ITP_P T97 40 28
ITPCLK/HOOK4 OBSDATA_D0
(4) BCLK_ITP_N T98 42 30
XDP_DBRST# ITPCLK#/HOOK5 OBSDATA_D1
(4,8) XDP_DBRST# T50 48 34
ICH_SMBDATA DBR#/HOOK7 OBSDATA_D2
(3,10,28) ICH_SMBDATA T74 51 36
ICH_SMBCLK SDA OBSDATA_D3
(3,10,28) ICH_SMBCLK T73 53 47
XDP_TDO SCL HOOK3 +1.5V_SUS
(4) XDP_TDO T40 52 55
XDP_TRST# TDO TCK1 H_CPUPWRGD_XDP R161 *1K_4
(4) XDP_TRST# T38 54 39 T29 H_PWRGOOD (4,11)
XDP_TDI TRSTN PWRGOOD/HOOK0 XDP_RST#_R R163 *1K_4
(4) XDP_TDI T37 56 46 T27 H_CPURST# (4)
XDP_TMS TDI RESET#/HOOK6
(4) XDP_TMS T41 58 1
XDP_TCLK TMS GND0 R140
(4) XDP_TCLK T49 57 2
TCK0 GND1
60 7
59
50
49
GND17
GND16
GND15
GND14
CPU XDP GND2
GND3
GND4
GND5
8
13
14
*1K_4
DDR3_DRAMRST# (14,15)
3
38 19
GND13 GND6 Q9
37 20
GND12 GND7
32 25
GND11 GND8 R108 *0_4 RST_GATE#_R
31 26 (11) RST_GATE# 2
GND10 GND9 R139
*Samtec BSH-030-01 *Short_4
*BSS138
C3C
1
B
(4) CPU_DDR3_DRAMRST#
Place near to XDP connector +1.1V_VTT +1.5V_SUS

+0.75V_DDR_VTT +1.5V_CPUVDDQ
XDP_TDO R180 51/F_4

PQ14
PR115 PR116 *AO6402A
*22_8 *220_8
1
2
5
6
(36,40,44) MAIND 3
4
2 MAINON_G 2
(44) MAINON_G
PQ16 PQ17
*DMN601K-7 *DMN601K-7
3A/ma
1
C
Qu
PRO
XDP
1 2 3 4 5 6 7
8
PM_DRAM_PWRGD_R (4)
t_4 PM_DRAM_PWRGD (8)
C3C
A
40)
14,15)
R159 R158
*Short_8 *Short_8
C3C
+1.5V_CPUVDDQ
/maximum

PROJECT : ZQ1
Rev
1A
2010 Sheet 16 of 48
8
5 4 3 2
GPU_1(VGA) U23A
PEG_TXP[0..15] 0518 SWAP PCIE for VGA side

(4) PEG_TXP[0..15]
PEG_TXN[0..15] 0518 SWAP PCIE for VGA side
(4) PEG_TXN[0..15]
PEG_RXP[0..15] PEG_TXP15 AA38 Y33 CPEG_RXP15 C150 SW@0.1u/10V_4

(4) PEG_RXP[0..15] (4) PEG_TXP15 PCIE_RX0P PCIE_TX0P PEG_RXP15 (4)
PEG_TXN15 Y37 Y32 CPEG_RXN15 C160 SW@0.1u/10V_4
D PEG_RXN[0..15] (4) PEG_TXN15 PCIE_RX0N PCIE_TX0N PEG_RXN15 (4)
(4) PEG_RXN[0..15]
PEG_TXP14 Y35 W33 CPEG_RXP14 C139 SW@0.1u/10V_4
(4) PEG_TXP14 PEG_TXN14 PCIE_RX1P PCIE_TX1P CPEG_RXN14 PEG_RXP14 (4)
W36 W32 C148 SW@0.1u/10V_4
(4) PEG_TXN14 PCIE_RX1N PCIE_TX1N PEG_RXN14 (4)
PEG_TXP13 W38 U33 CPEG_RXP13 C127 SW@0.1u/10V_4

V37 U32 C137 SW@0.1u/10V_4
PEG_TXP12 V35 U30 CPEG_RXP12 C125 SW@0.1u/10V_4

U36 U29 C120 SW@0.1u/10V_4
PEG_TXP11 U38 T33 CPEG_RXP11 C118 SW@0.1u/10V_4

T37 T32 C110 SW@0.1u/10V_4
PCI EXPRESS INTERFACE

PEG_TXP10 T35 T30 CPEG_RXP10 C107 SW@0.1u/10V_4
R36 T29 C103 SW@0.1u/10V_4
PEG_TXP9 R38 P33 CPEG_RXP9 C101 SW@0.1u/10V_4

C P37 P32 C91 SW@0.1u/10V_4
PEG_TXP8 P35 P30 CPEG_RXP8 C89 SW@0.1u/10V_4

(4) PEG_TXP8 PCIE_RX7P PCIE_TX7P PEG_RXP8 (4)
PEG_TXN8 N36 P29 CPEG_RXN8 C83 SW@0.1u/10V_4
PEG_TXP7 N38 N33 CPEG_RXP7 C73 SW@0.1u/10V_4

M37 N32 C70 SW@0.1u/10V_4
PEG_TXP6 M35 N30 CPEG_RXP6 C68 SW@0.1u/10V_4

L36 N29 C60 SW@0.1u/10V_4
PEG_TXP5 L38 L33 CPEG_RXP5 C57 SW@0.1u/10V_4

K37 L32 C54 SW@0.1u/10V_4
PEG_TXP4 K35 L30 CPEG_RXP4 C48 SW@0.1u/10V_4

PEG_TXN4 J36 L29 CPEG_RXN4 C43 SW@0.1u/10V_4
PEG_TXP3 J38 K33 CPEG_RXP3 C37 SW@0.1u/10V_4

B PEG_TXN3 H37 K32 CPEG_RXN3 C41 SW@0.1u/10V_4
PEG_TXP2 H35 J33 CPEG_RXP2 C31 SW@0.1u/10V_4

G36 J32 C34 SW@0.1u/10V_4
PEG_TXP1 G38 K30 CPEG_RXP1 C25 SW@0.1u/10V_4

F37 K29 C24 SW@0.1u/10V_4
PEG_TXP0 F35 H33 CPEG_RXP0 C29 SW@0.1u/10V_4

PEG_TXN0 E37 H32 CPEG_RXN0 C27 SW@0.1u/10V_4
CLOCK
(10) CLK_PCIE_VGA AB35
PCIE_REFCLKP
(10) CLK_PCIE_VGA# AA36
PCIE_REFCLKN Madison
For Broadway, Madison and Park CALIBRATION Park

the PWRGOOD ball must be conneccted to ground AJ21 Y30 R45 SW@1.27K/F_4
NC#1 PCIE_CALRP
AK21
A R61 SW@10K_4 NC#2 R40 SW@2K/F_4
AH16
PWRGOOD PCIE_CALRN
Y29 +1V +1.0V
(11) GPU_RST# AA30 PERSTB For M97, Broadway, Madison and Park PCIE_VDDC is 1.0V Quanta
SW@Madison/Park_M2
PROJECT
Madison/Park M2-PCIE I
5 4 3 2
1
n AJ007720T02
AJ077400T08
nta Computer Inc.

CT : ZQ1
Rev
1A
CIE I/F
Sheet 17 of 48
1
5 4 3 2
U23B U23G
GPU_2(VGA)
AU24 LVDS CONTROL AK27
TXCAP_DPA3P EXT_HDMICLK+ (26) VARY_BL EV_LVDS_BRIGHT (25
AV23 EXT_HDMICLK- (26) AJ27 EV_LVDS_VDDEN (25
TXCAM_DPA3N DIGON
AT25 EXT_HDMITX0P (26)
MUTI GFX TX0P_DPA2P
AR24 EXT_HDMITX0N (26)
DPA TX0M_DPA2N
AU26 AK35 C-test
TX1P_DPA1P EXT_HDMITX1P (26) TXCLK_UP_DPF3P
AV25 EXT_HDMITX1N (26) AL36
TX1M_DPA1N TXCLK_UN_DPF3N
AR8 AT27 EXT_HDMITX2P (26) AJ38
DVPCNTL_MVP_0 TX2P_DPA0P TXOUT_U0P_DPF2P
AU8 AR26 EXT_HDMITX2N (26) AK37
D DVPCNTL_MVP_1 TX2M_DPA0N TXOUT_U0N_DPF2N
AP8
NC on Park AW 8
DVPCNTL_0
DVPCNTL_1 TXCBP_DPB3P
AR30
TXOUT_U1P_DPF1P
AH35
AR3 AT29 AJ36
DVPCNTL_2 TXCBM_DPB3N TXOUT_U1N_DPF1N
AR1
GPU Power-on sequence (22) RAM_STRAP0 AU1
AU3
DVPCLK
DVPDATA_0 TX3P_DPB2P
AV31
AU30
TXOUT_U2P_DPF0P
AG38
AH37
(22) RAM_STRAP1 DVPDATA_1 TX3M_DPB2N TXOUT_U2N_DPF0N
AW 3 DPB
1 => +VGPU_CORE (22) RAM_STRAP2
AP6
DVPDATA_2
AR32
TXOUT_U3P
AF35
T85 AW 5 AT31 AG36
2 => +VGPU_IO AU5
DVPDATA_4
DVPDATA_5
TX4M_DPB1N TXOUT_U3N
AR6 AT33
3 => +1V 1.8V GPIO AW 6
AU6
DVPDATA_7 TX5M_DPB0N
AU32 LVTMDP
DVPDATA_8
4 => +1.5V_GPU AT7
AV7
DVPDATA_9
DVPDATA_10
TXCCP_DPC3P
TXCCM_DPC3N
AU14
AV13
T90
T89
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
AP34
AR34
EV_TXLCLKOUT+ (25)
EV_TXLCLKOUT- (25)
AN7
5 => +3V_D AV9
DVPDATA_11
DVPDATA_12 TX0P_DPC2P
AT15 T88 TXOUT_L0P_DPE2P
AW 37 EV_TXLOUT0+ (25)
AT9 AR14 T84 AU35 EV_TXLOUT0- (25)
6 => +1.8V_GPU AR10
AW 10
DVPDATA_13
DVPDATA_14 DPC
TX0M_DPC2N
AU16
TXOUT_L0N_DPE2N
AR37
DVPDATA_15 TX1P_DPC1P T87 TXOUT_L1P_DPE1P EV_TXLOUT1+ (25)
7 => dGPU_PWROK AU10
AP10
DVPDATA_16 TX1M_DPC1N
AV15 T91 TXOUT_L1N_DPE1N
AU39 EV_TXLOUT1- (25)
DVPDATA_17
AV11 AT17 T19 AP35 EV_TXLOUT2+ (25)
DVPDATA_18 TX2P_DPC0P TXOUT_L2P_DPE0P
AT11 AR16 T17 AR35 EV_TXLOUT2- (25)
DVPDATA_19 TX2M_DPC0N TXOUT_L2N_DPE0N
AR12
NC on Park AW 12
DVPDATA_20
DVPDATA_21 TXCDP_DPD3P
AU20
TXOUT_L3P
AN36
AU12 AT19 AP37
DVPDATA_22 TXCDM_DPD3N TXOUT_L3N
AP12
+3V_D DVPDATA_23
AT21
TX3P_DPD2P
AR20
TX3M_DPD2N
Channel D N.C for Park-M2
DPD AU22
TX4P_DPD1P SW @Madison/Park_M2
AV21
R66 R67 TX4M_DPD1N
SW @10K_4 SW @10K_4 I2C AT23
TX5P_DPD0P
AR22
TX5M_DPD0N ramp remove short pad
AK26
SCL
C AJ26
SDA
AD39 EXT_CRT_RED
R EXT_CRT_RED (25)
GENERAL PURPOSE I/O AD37
RB
(22) GPU_GPIO0 AH20
GPIO_0 EXT_CRT_GRN
(22) GPU_GPIO1 AH18 AE36 EXT_CRT_GRN (25)
GPIO_1 G
(22) GPU_GPIO2 AN16 AD35
GPIO_2 GB
(22) GPIO3_SMBDAT AH23
GPIO_3_SMBDATA EXT_CRT_BLU
(22) GPIO4_SMBCLK AJ23 AF37 EXT_CRT_BLU (25)
GPIO_4_SMBCLK B
T11 AH17 AE38
1/21 ramp remove IO_VID0 GPIO_5_AC_BATT DAC1 BB
AJ17
GPIO_6 R54 R51 R48
(25) EV_LVDS_BLON AK17 AC36 EXT_HSYNC (22,25)
GPIO_7_BLON HSYNC SW @150/F_4 SW @150/F_4 SW @150/F_4
(22) SOUT_GPIO8 AJ13 AC38 EXT_VSYNC (22,25)
GPIO_8_ROMSO VSYNC
(22) SIN_GPIO9 AH15
GPIO_9_ROMSI
(22) SCLK_GPIO10 AJ16
+3V_D GPIO_10_ROMSCK R46 SW @499/F_4
(22) GPU_GPIO11 AK16 AB34
GPIO_11 RSET
(22) GPU_GPIO12 AL16
GPIO_12 AVDD
(22) GPU_GPIO13 AM16 AD34
GPIO_13 AVDD
T12 AM14 AE34
R132 GPIO_14_HPD2 AVSSQ
3.3V GPIO (41) VID1 AM13
GPIO_15_PW RCNTL_0 (1.8V@70mA AVDD)
AK14 AC33 VDD1DI
T18 GPIO_16_SSIN VDD1DI
*SW @10K_4 AG30 AC34 AVDD L3 SW @
(22) ALT#_GPIO17 GPIO_17_THERMAL_INT VSS1DI
T20 AN14
GPIO_18_HPD3
AM17
GPIO_19_CTF C146 C183 C176
(41) VID2 AL13 AC30
+3V_D GPIO_20_PW RCNTL_1 R2 SW @0.1u/10V_4 SW @1u/6.3V_4 SW @10u/6.3V_6
T7 AJ14 AC31
R125 GPIO_21_BB_EN R2B
(22) SCS#_GPIO22 AK13
GPIO_22_ROMCSB
AN13 AD30
SW @10K_4 R77 *SW @10K_4GPIO24_TRSTB GPIO_23_CLKREQB G2
AM23
JTAG_TRSTB G2B
AD31 (1.8V@100mA VDD1DI)
R131 +3V_D R78 *SW @10K_4 AN23
T16 JTAG_TDI
27M_CLK AK23 AF30 VDD1DI L4 SW @
(3) 27M_CLK JTAG_TCK B2
*SW @10K/F_4 +3V_D R73 *SW @10K_4 AL24 AF31
JTAG_TMS B2B
T15 AM24
D3D JTAG_TDO C165 C180 C188
(10) PEG_CLKREQ# AJ19
GENERICA DAC2 will be NC on future ASIC
AK19 AC32 SW @0.1u/10V_4 SW @1u/6.3V_4 SW @10u/6.3V_6
GENERICB C
AJ20 AD32
R124 GENERICC Y
AK20 AF32
GENERICD COMP
AJ24
B
*SW @10K/F_4 GENERICE_HPD4 DAC2
AH26
GENERICF
AH24 AD29 T5
GENERICG H2SYNC
AC29 V2SYNC (22)
V2SYNC
(26) EXT_HDMI_HPD
AK24
+1.8V_GPU HPD1 VDD1DI
AG31
VDD2DI
AG32
VSS2DI
R93 AG33 +3V_D (3.3V@130mA A2VDD)

A2VDD
SW @499/F_4
AD33 A2VDDQ
VREFG AH13 A2VDDQ C164
VREFG SW @0.1u/10V_4
AF33
C191 A2VSSQ
R82
SW @249/F_4 SW @0.1u/10V_4 R2SET
AA29 R47 SW @715/F_4
+1.8V(75mA)
+1.8V_GPU L7 SW @SBY100505T-121Y-N/300mA/120ohm_4 DPLL_PVDD DDC/AUX AM26
DDC1CLK EV_HDMI_DDCCK (26)
PLL/CLOCK AN26
C198 C193 C185 DPLL_PVDD AM32
DPLL_PVDD
DDC1DATA EV_HDMI_DDCDAT (26)
HDMI
AN32 AM27 +1.8V
SW @10u/6.3V_6 SW @1u/6.3V_4 SW @0.1u/10V_4 DPLL_PVSS AUX1P
AUX1N
AL27 (1.8V@2mA A2VDDQ)
DPLL_VDDC AN31 AM19 A2VDDQ L35 SW @SBY100505T-
C547 SW @27p/50V_4 DPLL_VDDC DDC2CLK
AL19
DDC2DATA
+1.0V(125mA)
2
XTALI_27M AV33 AN20 C143 C144

L9 SW @SBY100505T-121Y-N/300mA/120ohm_4 DPLL_VDDC Y2 R402 XTALO_27M XTALIN AUX2P SW @0.1u/10V_4 SW @1u/6.3V_4
+1V AU34 AM20
SW @1M/F_4 XTALOUT AUX2N
SW @27MHZ
C212 C200 C190 AL30 T13
1
DDCCLK_AUX3P
AM30 T14
SW @10u/6.3V_6 SW @1u/6.3V_4 SW @0.1u/10V_4 C548 SW @27p/50V_4 DDCDATA_AUX3N
AL29
DDCCLK_AUX4P
AF29 AM29
A
(22) GPU_D+
(22) GPU_D- AG29
DPLUS
DMINUS
THERMAL DDCDATA_AUX4N DDC AUX4 NC for Park_M2
+1.8V(5mA) DDCCLK_AUX5P
AN21 EV_LVDS_DDCCLK (25)
AM21
+1.8V_GPU L5 SW @SBY100505T-121Y-N/300mA/120ohm_4 TS_VDD
T8
TS_VDD
AK32
TS_FDO
DDCDATA_AUX5N EV_LVDS_DDCDAT (25) LVDS
AJ32 AJ30 EV_CRTDCLK (25)
C187 C181 TSVDD DDC6CLK
AJ33 AJ31
TSVSS DDC6DATA EV_CRTDDAT (25) CRT
SW @10u/6.3V_6 SW @0.1u/10V_4 AK30
NC_DDCCLK_AUX7P
AK29
NC_DDCDATA_AUX7N DDC AUX7 NC for Park_M2
Qua
SW @Madison/Park_M2
PRO
Madison/Park M2-
5 4 3 2
1
HT (25)
EN (25)
+ (25)
- (25)
(25)
25)
(25)
25)
(25)
25)
+1.8V_GPU
SW @SBY100505T-121Y-N/300mA/120ohm_4
6.3V_6
SW @SBY100505T-121Y-N/300mA/120ohm_4
6.3V_6
+1.8V_GPU
0505T-121Y-N/300mA/120ohm_4

PROJECT : ZQ1
Rev
1A
M2-HOST I/F
10 Sheet 18 of 48
1
5 4 3 2
GPU_3(VGA)
Park M2-channel B used(S3 package use Channel A
VMA_DQ[63..0] VMB_DQ[63..0]
(23) VMA_DQ[63..0] (24) VMB_DQ[63..0]
VMA_DM[7..0] VMB_DM[7..0]
(23) VMA_DM[7..0] (24) VMB_DM[7..0]
U23C U23D
VMA_RDQS[7..0] DDR2 DDR2 VMB_RDQS[7..0] DDR2 DDR2
(23) VMA_RDQS[7..0] (24) VMB_RDQS[7..0]
GDDR3/GDDR5 GDDR5/GDDR3 GDDR3/GDDR5 GDDR5/GDDR3
VMA_W DQS[7..0] DDR3 DDR3 VMB_W DQS[7..0] DDR3 DDR3
(23) VMA_W DQS[7..0] (24) VMB_W DQS[7..0]
VMA_DQ0 C37 G24 VMA_MA0 VMB_DQ0 C5 P8 VMB_MA0
VMA_DQ1 DQA0_0/DQA_0 MAA0_0/MAA_0 VMA_MA1 VMB_DQ1 DQB0_0/DQB_0 MAB0_0/MAB_0 VMB_MA1
C35 J23 C3 T9
D DQA0_1/DQA_1 MAA0_1/MAA_1 DQB0_1/DQB_1 MAB0_1/MAB_1
MEMORY INTERFACE A
VMA_MA[13..0] VMA_DQ2 A35 H24 VMA_MA2 VMB_MA[13..0] VMB_DQ2 E3 P9 VMB_MA2
(23) VMA_MA[13..0] DQA0_2/DQA_2 MAA0_2/MAA_2 (24) VMB_MA[13..0] DQB0_2/DQB_2 MAB0_2/MAB_2
MEMORY INTERFACE B
VMA_DQ3 E34 J24 VMA_MA3 VMB_DQ3 E1 N7 VMB_MA3
G32 H26 F1 N8
VMA_BA0 VMA_DQ5 DQA0_4/DQA_4 MAA0_4/MAA_4 VMA_MA5 VMB_BA0 VMB_DQ5 DQB0_4/DQB_4 MAB0_4/MAB_4 VMB_MA5
(23) VMA_BA0 D33 J26 (24) VMB_BA0 F3 N9
(23) VMA_BA1 F32 H21 (24) VMB_BA1 F5 U9
(23) VMA_BA2 E32 G21 (24) VMB_BA2 G4 U8
D31 H19 H5 Y9
F30 H20 H6 W9
C30 L13 J4 AC8
A30 G16 K6 AC9
F28 J16 K5 AA7
VMA_DQ13 DQA0_12/DQA_12 MAA1_4/MAA_12 VMA_BA2 VMB_DQ13 DQB0_12/DQB_12 MAB1_4/MAB_12 VMB_BA2
C28 H16 L4 AA8
VMA_DQ14 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 VMA_BA0 VMB_DQ14 DQB0_13/DQB_13 MAB1_5/BA2 VMB_BA0
A28 J17 M6 Y8
VMA_DQ15 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 VMA_BA1 VMB_DQ15 DQB0_14/DQB_14 MAB1_6/BA0 VMB_BA1
E28 H17 M1 AA9
VMA_DQ16 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 VMB_DQ16 DQB0_15/DQB_15 MAB1_7/BA1
D27 M3
VMA_DQ17 DQA0_16/DQA_16 VMA_DM0 VMB_DQ17 DQB0_16/DQB_16 VMB_DM0
F26 A32 M5 H3
VMA_DQ18 DQA0_17/DQA_17 W CKA0_0/DQMA_0 VMA_DM1 VMB_DQ18 DQB0_17/DQB_17 W CKB0_0/DQMB_0 VMB_DM1
C26 C32 N4 H1
VMA_DQ19 DQA0_18/DQA_18 W CKA0B_0/DQMA_1 VMA_DM2 VMB_DQ19 DQB0_18/DQB_18 W CKB0B_0/DQMB_1 VMB_DM2
A26 D23 P6 T3
F24 E22 P5 T5
C24 C14 R4 AE4
A24 A14 T6 AF5
E24 E10 T1 AK6
C22 D9 U4 AK5
VMA_DQ25 DQA0_24/DQA_24 W CKA1B_1/DQMA_7 VMB_DQ25 DQB0_24/DQB_24 W CKB1B_1/DQMB_7
A22 V6
VMA_DQ26 DQA0_25/DQA_25 GDDR5/DDR2/GDDR3 VMA_RDQS0 VMB_DQ26 DQB0_25/DQB_25 GDDR5/DDR2/GDDR3 VMB_RDQS0
F22 C34 V1 F6
VMA_DQ27 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 VMA_RDQS1 VMB_DQ27 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 VMB_RDQS1
D21 D29 V3 K3
+1.5V_GPU VMA_DQ28 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 VMA_RDQS2 VMB_DQ28 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 VMB_RDQS2
A20 D25 Y6 P3
F20
DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3
E20 QSA[7..0] Y1
DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3
V5 QSB[7..0]
VMA_DQ30 D19 E16 VMA_RDQS4 VMB_DQ30 Y3 AB5 VMB_RDQS4
E18 E12 Y5 AH1
C18 J10 AA4 AJ9
R15 VMA_DQ33 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 VMA_RDQS7 VMB_DQ33 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 VMB_RDQS7
A18 D7 AB6 AM5
SW @40.2/F_4 VMA_DQ34 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 VMB_DQ34 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7
F18 AB1
VMA_DQ35 DQA1_2/DQA_34 VMA_W DQS0 VMB_DQ35 DQB1_2/DQB_34 VMB_W DQS0
D17 A34 AB3 G7
MVREFDA VMA_DQ36 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/W DQSA_0 VMA_W DQS1 VMB_DQ36 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/W DQSB_0 VMB_W DQS1
A16 E30 AD6 K1
VMA_DQ37 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/W DQSA_1 VMA_W DQS2 VMB_DQ37 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/W DQSB_1 VMB_W DQS2
F16 E26 AD1 P1
D15
DQA1_6/DQA_38 DDBIA0_3/QSA_3B/W DQSA_3
C20 QSA#[7..0] AD3
DQB1_6/DQB_38 DDBIB0_3/QSB_3B/W DQSB_3
W4 QSB#[7..0]
C C33 VMA_DQ39 E14 C16 VMA_W DQS4 VMB_DQ39 AD5 AC4 VMB_W DQS4
R14 SW @0.1u/10V_4 VMA_DQ40 DQA1_7/DQA_39 DDBIA1_0/QSA_4B/W DQSA_4 VMA_W DQS5 VMB_DQ40 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/W DQSB_4 VMB_W DQS5
F14 C12 AF1 AH3
SW @100/F_4 VMA_DQ41 DQA1_8/DQA_40 DDBIA1_1/QSA_5B/W DQSA_5 VMA_W DQS6 VMB_DQ41 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/W DQSB_5 VMB_W DQS6
D13 J11 AF3 AJ8
F12 F8 AF6 AM3
VMA_DQ43 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/W DQSA_7 VMB_DQ43 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/W DQSB_7
A12 AG4
VMA_DQ44 DQA1_11/DQA_43 VMB_DQ44 DQB1_11/DQB_43
D11 J21 VMA_ODT0 (23) AH5 T7 VMB_ODT0 (24)
VMA_DQ45 DQA1_12/DQA_44 ADBIA0/ODTA0 VMB_DQ45 DQB1_12/DQB_44 ADBIB0/ODTB0
F10 G19 VMA_ODT1 (23) AH6 W7 VMB_ODT1 (24)
VMA_DQ46 DQA1_13/DQA_45 ADBIA1/ODTA1 VMB_DQ46 DQB1_13/DQB_45 ADBIB1/ODTB1
A10 AJ4
+1.5V_GPU VMA_DQ47 DQA1_14/DQA_46 VMA_CLK0 VMB_DQ47 DQB1_14/DQB_46 VMB_CLKP0
C10 H27 VMA_CLKP0 (23) AK3 L9 VMB_CLKP0 (24)
VMA_DQ48 DQA1_15/DQA_47 CLKA0 VMA_CLK0# VMB_DQ48 DQB1_15/DQB_47 CLKB0 VMB_CLKN0
G13 G27 VMA_CLKN0 (23) AF8 L8 VMB_CLKN0 (24)
VMA_DQ49 DQA1_16/DQA_48 CLKA0B VMB_DQ49 DQB1_16/DQB_48 CLKB0B
H13 AF9
VMA_DQ50 DQA1_17/DQA_49 VMA_CLK1 VMB_DQ50 DQB1_17/DQB_49 VMB_CLKP1
J13 J14 VMA_CLKP1 (23) AG8 AD8 VMB_CLKP1 (24)
VMA_DQ51 DQA1_18/DQA_50 CLKA1 VMA_CLK1# VMB_DQ51 DQB1_18/DQB_50 CLKB1 VMB_CLKN1
H11 H14 VMA_CLKN1 (23) AG7 AD7 VMB_CLKN1 (24)
R20 VMA_DQ52 DQA1_19/DQA_51 CLKA1B VMB_DQ52 DQB1_19/DQB_51 CLKB1B
G10 AK9
SW @40.2/F_4 VMA_DQ53 DQA1_20/DQA_52 VMA_RAS0# VMB_DQ53 DQB1_20/DQB_52 VMB_RAS0#
G8 K23 VMA_RAS0# (23) AL7 T10 VMB_RAS0# (24)
VMA_DQ54 DQA1_21/DQA_53 RASA0B VMA_RAS1# VMB_DQ54 DQB1_21/DQB_53 RASB0B VMB_RAS1#
K9 K19 VMA_RAS1# (23) AM8 Y10 VMB_RAS1# (24)
MVREFSA VMA_DQ55 DQA1_22/DQA_54 RASA1B VMB_DQ55 DQB1_22/DQB_54 RASB1B
K10 AM7
VMA_DQ56 DQA1_23/DQA_55 VMA_CAS0# VMB_DQ56 DQB1_23/DQB_55 VMB_CAS0#
G9 K20 VMA_CAS0# (23) AK1 W 10 VMB_CAS0# (24)
VMA_DQ57 DQA1_24/DQA_56 CASA0B VMA_CAS1# VMB_DQ57 DQB1_24/DQB_56 CASB0B VMB_CAS1#
A8 K17 VMA_CAS1# (23) AL4 AA10 VMB_CAS1# (24)
C36 VMA_DQ58 DQA1_25/DQA_57 CASA1B +1.5V_GPU VMB_DQ58 DQB1_25/DQB_57 CASB1B
C8 AM6
R16 SW @0.1u/10V_4 VMA_DQ59 DQA1_26/DQA_58 VMA_CS0# VMB_DQ59 DQB1_26/DQB_58 VMB_CS0#
E8 K24 VMA_CS0# (23) AM1 P10 VMB_CS0# (24)
SW @100/F_4 VMA_DQ60 DQA1_27/DQA_59 CSA0B_0 VMB_DQ60 DQB1_27/DQB_59 CSB0B_0
A6 K27 AN4 L10
VMA_DQ61 DQA1_28/DQA_60 CSA0B_1 VMB_DQ61 DQB1_28/DQB_60 CSB0B_1
C6 AP3
VMA_DQ62 DQA1_29/DQA_61 VMA_CS1# VMB_DQ62 DQB1_29/DQB_61 VMB_CS1#
E6 M13 VMA_CS1# (23) AP1 AD10 VMB_CS1# (24)
VMA_DQ63 DQA1_30/DQA_62 CSA1B_0 R53 VMB_DQ63 DQB1_30/DQB_62 CSB1B_0
A5 K16 AP5 AC10
DQA1_31/DQA_63 CSA1B_1 DQB1_31/DQB_63 CSB1B_1
Used for Park-M2 SW @40.2/F_4
MVREFDA L18 K21 VMA_CKE0 U10 VMB_CKE0
MVREFDA CKEA0 VMA_CKE0 (23) CKEB0 VMB_CKE0 (24)
R28 SW @MD@243/F_4 MVREFSA L20 J20 VMA_CKE1 MVREFDB Y12 AA11 VMB_CKE1
MVREFSA CKEA1 VMA_CKE1 (23) MVREFDB CKEB1 VMB_CKE1 (24)
MVREFSB AA12
R30 SW @PK@243/F_4 VMA_W E0# MVREFSB VMB_W E0#
L27 K26 VMA_W E0# (23) N10 VMB_W E0# (24)
MEM_CALRN0 W EA0B VMA_W E1# C138 D3D W EB0B VMB_W E1#
N12 L15 VMA_W E1# (23) AB11 VMB_W E1# (24)
R59 SW @MD@243/F_4 MEM_CALRN1 W EA1B R49 SW @0.1u/10V_4 W EB1B
+1.5V_GPU AG12
MEM_CALRN2 SW @100/F_4 R68 *SW @10K_4
+3V_D
R36 SW @PK@243/F_4 VMA_MA13 R50 SW @10K_4 AD28 VMB_MA13
GDDR5
M12 H23 T8
GDDR5
MEM_CALRP1 MAA0_8 TESTEN MAB0_8 R79 *S
M27 J19 W8
R29 SW @MD@243/F_4 MEM_CALRP0 MAA1_8 MAB1_8
AH12 AK10
R60 SW @MD@243/F_4 MEM_CALRP2 CLKTESTA R69 SW @51_4
AL10 AH11
CLKTESTB DRAM_RST
B B-test
Note by AN_M96_C1 +1.5V_GPU
AL31 R94 R84 C203
RSVD
Used for Madison-M2 *SW @0_4 *SW @0_4 SW @68p/50V_4 R64
SW @10K_4
SW @Madison/Park_M2 R63 SW @Madison/Park_M2
SW @40.2/F_4
C170
R55 SW @0.1u/10V_4
SW @100/F_4
Qua
PRO
Madison/Park M2-
5 4 3 2
1
l A)
24)
24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
(24)
24)
24)
24)
24)
24)
24)
*SW @4.7K_4 +1.5V_GPU
MEM_RST# (23,24)
B
_4

PROJECT : ZQ1
Rev
1A
M2-MEM I/F
10 Sheet 19 of 48
1
5 4 3 2
GPU_4(VGA)
U23F
U23E
For DDR3, MVDDQ = 1.5V (7.5A)
+1.5V_GPU MEM I/O +1.8V_GPU
PCIE (1.8V@400mA PCIE_VDDR) AB39 A3
PCIE_VDDR L34 SW@HCB1608KF-181T15/1.5A/180ohm_6 PCIE_VSS#1 GND#1
AC7 VDDR1#1 PCIE_VDDR#1 AA31 E39 PCIE_VSS#2 GND#2 A37
AD11 VDDR1#2 PCIE_VDDR#2 AA32 F34 PCIE_VSS#3 GND#3 AA16
AF7 VDDR1#3 PCIE_VDDR#3 AA33 F39 PCIE_VSS#4 GND#4 AA18
C45 C63 C40 C192 C126 AG10 AA34 C128 C526 C121 C117 C142 C525 C527 C528 G33 AA2
SW@10u/6.3V_6 SW@10u/6.3V_6 SW@10u/6.3V_6 VDDR1#4 PCIE_VDDR#4 SW@0.1u/10V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 PCIE_VSS#5 GND#5
AJ7 VDDR1#5 PCIE_VDDR#5 V28 G34 PCIE_VSS#6 GND#6 AA21
SW@10u/6.3V_6 SW@10u/6.3V_6 AK8 W29 SW@0.1u/10V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@10u/6.3V_6 H31 AA23
D VDDR1#6 PCIE_VDDR#6 PCIE_VSS#7 GND#7
AL9 W30 H34 AA26
VDDR1#7 PCIE_VDDR#7 PCIE_VSS#8 GND#8
G11 Y31 H39 AA28
VDDR1#8 PCIE_VDDR#8 PCIE_VSS#9 GND#9
G14 J31 AA6
VDDR1#9 PCIE_VSS#10 GND#10
G17 J34 AB12
VDDR1#10 +1V PCIE_VSS#11 GND#11
G20 VDDR1#11 PCIE_VDDC#1 G30 K31 PCIE_VSS#12 GND#12 AB15
C66 C147 C134 C186 C161 C56 G23 G31 (1.0V@1.1A PCIE_VDDC) K34 AB17
SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 VDDR1#12 PCIE_VDDC#2 PCIE_VSS#13 GND#13
G26 VDDR1#13 PCIE_VDDC#3 H29 K39 PCIE_VSS#14 GND#14 AB20
SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 G29 H30 L31 AB22
VDDR1#14 PCIE_VDDC#4 PCIE_VSS#15 GND#15
H10 VDDR1#15 PCIE_VDDC#5 J29 L34 PCIE_VSS#16 GND#16 AB24
J7 J30 C92 C80 C58 C51 C105 C64 C88 C47 M34 AB27
VDDR1#16 PCIE_VDDC#6 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 PCIE_VSS#17 GND#17
J9 VDDR1#17 PCIE_VDDC#7 L28 M39 PCIE_VSS#18 GND#18 AC11
K11 M28 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@10u/6.3V_6 N31 AC13
K13 N28 N34 AC16
K8 R28 P31 AC18
C46 C59 C116 C75 C42 C65 VDDR1#20 PCIE_VDDC#10 PCIE_VSS#21 GND#21
L12 VDDR1#21 PCIE_VDDC#11 T28 P34 PCIE_VSS#22 GND#22 AC2
SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 L16 U28 P39 AC21
SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 VDDR1#22 PCIE_VDDC#12 +VGPU_CORE PCIE_VSS#23 GND#23
L21 VDDR1#23 R34 PCIE_VSS#24 GND#24 AC23
L23 VDDR1#24 (30A or more) T31 PCIE_VSS#25 GND#25 AC26
L26 VDDR1#25 VDDC#1 AA15 T34 PCIE_VSS#26 GND#26 AC28
L7 CORE AA17 T39 AC6
VDDR1#26 VDDC#2 PCIE_VSS#27 GND#27
M11 VDDR1#27 VDDC#3 AA20 U31 PCIE_VSS#28 GND#28 AD15
N11 AA22 C99 C102 C122 C124 C100 C158 C149 C94 C95 C136 U34 AD17
C106 C52 C67 C79 C53 VDDR1#28 VDDC#4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 PCIE_VSS#29 GND#29
P7 AA24 V34 AD20
SW@1u/6.3V_4 SW@0.1u/10V_4 SW@0.1u/10V_4 VDDR1#29 VDDC#5 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 PCIE_VSS#30 GND#30
R11 AA27 V39 AD22
SW@0.1u/10V_4 SW@0.1u/10V_4 VDDR1#30 VDDC#6 PCIE_VSS#31 GND#31
U11 AB16 W31 AD24
U7 AB18 W34 AD27
Y11 AB21 Y34 AD9
Y7 VDDR1#34 VDDC#10 AB23 Y39 PCIE_VSS#35 GND#35 AE2
VDDC#11 AB26 GND#36 AE6
VDDC#12 AB28 GND#37 AF10
AC17 C175 C178 C151 C129 C173 C166 C154 C109 C153 C168 AF16
VDDC#13 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 GND#38
VDDC#14 AC20 GND#39 AF18
LEVEL AC22 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 AF21
(1.8V@110mA VDD_CT) TRANSLATION VDDC#15
VDDC#16
AC24 GND GND#40
GND#41
AG17
POWER
L17 SW@SBY100505T-121Y-N/300mA/120ohm_4 VDDC_CT AF26 AC27 F15 AG2
+1.8V_GPU VDD_CT#1 VDDC#17 GND#100 GND#42
AF27 AD18 F17 AG20
VDD_CT#2 VDDC#18 GND#101 GND#43
AG26 AD21 F19 AG22
C C228 C172 C159 VDD_CT#3 VDDC#19 GND#102 GND#44
AG27 AD23 F21 AG6
SW@10u/6.3V_6 SW@0.1u/10V_4 VDD_CT#4 VDDC#20 GND#103 GND#45
AD26 F23 AG9 PowerXpr
SW@1u/6.3V_4 VDDC#21 C140 C162 C131 C174 C152 C112 C108 C135 C119 C104 GND#104 GND#46
VDDC#22 AF17 F25 GND#105 GND#47 AH21 If not used
(3.3V@60mA)) I/O AF20 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 F27 AJ10
VDDC#23 GND#106 GND#48 PX_EN = L
+3V_D AF23 AF22 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 F29 AJ11
VDDR3#1 VDDC#24 GND#107 GND#49 PX_EN = H
AF24 VDDR3#2 VDDC#25 AG16 F31 GND#108 GND#50 AJ2
AG23 AG18 F33 AJ28 PX_EN is
C182 C177 C169 C179 VDDR3#3 VDDC#26 GND#109 GND#51 regulators
AG24 AG21 F7 AJ6
SW@10u/6.3V_6 SW@1u/6.3V_4 VDDR3#4 VDDC#27 GND#110 GND#52 output hig
AH22 F9 AK11
SW@1u/6.3V_4 SW@1u/6.3V_4 VDDC#28 GND#111 GND#53 OFF. An o
AH27 G2 AK31
VDDC#29 C132 C113 C130 C114 C85 C115 GND#112 GND#54
AF13 VDDR4#4 VDDC#30 AH28 G6 GND#113 GND#55 AK7 regulators
AF15 M26 SW@10u/6.3V_6 SW@10u/6.3V_6 SW@10u/6.3V_6 H9 AL11 by default
VDDR4#5 VDDC#31 SW@10u/6.3V_6 SW@10u/6.3V_6 SW@10u/6.3V_6 GND#114 GND#56
AG13 VDDR4#7 VDDC#32 N24 J2 GND#115 GND#57 AL14 If this sign
+1.8V_GPU L13 SW@SBY100505T-121Y-N/300mA/120ohm_4 VDDR4 AG15 N27 J27 AL17 connected
VDDR4#8 VDDC#33 GND#116 GND#58
R18 J6 AL2
VDDC#34 GND#117 GND#59
VDDC#35 R21 BIF_VDDC should be connected to VDDC if BACO feature not used. J8 GND#118 GND#60 AL20
C222 C229 AD12 R23 K14 AL21 R112 *
SW@1u/6.3V_4 VDDR4#1 VDDC#36 For BACO, refer to the databook GND#119 GND#61
AF11 R26 K7 AL23
SW@0.1u/10V_4 VDDR4#2 VDDC#37 GND#120 GND#62
AF12 T17 L11 AL26
VDDR4#3 VDDC#38 GND#121 GND#63 R111
AG11 T20 L17 AL32
VDDR4#6 VDDC#39 GND#122 GND#64 *SW@0_4
VDDC#40 T22 L2 GND#123 GND#65 AL6
VDDC#41 T24 L22 GND#124 GND#66 AL8
T27 PIN different between Broadway and Madison L24 AM11
VDDC#43 U16 L6 GND#126 GND#68 AM31
M20 U18 Pin Broadway Madison M17 AM9
T2 NC_VDDRHA VDDC#44 GND#127 GND#69
T1 M21 U21 M22 AN11 Pin AL21 to G
NC_VSSRHA VDDC#45 N27 VDDC BIF_VDDC GND#128 GND#70
U23 M24 AN2
U26 N16 AN30
T4 V12 V17 N18 AN6
NC_VDDRHB VDDC#48 AL31 TS_A NC_TS_A GND#131 GND#73
T3 U12 V20 N2 AN8
NC_VSSRHB VDDC#49 GND#132 GND#74
VDDC#50 V22 N21 GND#133 GND#75 AP11
VDDC#51 V24 N23 GND#134 GND#76 AP7
V27 AL21 GND PX_EN N26 AP9
VDDC#53 Y16 N6 GND#136 GND#78 AR5
(1.8V@40mA PCIE_PVDD) PLL Y18 R15 AW34
L33 SW@SBY100505T-121Y-N/300mA/120ohm_4 PCIE_PVDD VDDC#54 GND#137 GND#79
+1.8V_GPU AB37 PCIE_PVDD VDDC#55 Y21 R17 GND#138 GND#80 B11
VDDC#56 Y23 R2 GND#139 GND#81 B13
MPV18 H7 Y26 R20 B15
B
C523 C522 C521 MPV18#1 VDDC#57 GND#140 GND#82
H8 Y28 R22 B17
SW@10u/6.3V_6 SW@0.1u/10V_4 MPV18#2 VDDC#58 GND#141 GND#83
R24 GND#142 GND#84 B19
SW@1u/6.3V_4 +VGPU_IO R27 B21
SPV18 GND#143 GND#85
AM10
SPV18 (DDR3 1.12V@4A VDDCI) or more R6
GND#144 GND#86
B23
(1.8V@150mA MPV18) VDDCI#1 AA13 T11 GND#145 GND#87 B25
+1.8V_GPU L2 SW@SBY100505T-121Y-N/300mA/120ohm_4 SPV10 AN9 AB13 T13 B27
SPV10 VDDCI#2 GND#146 GND#88
VDDCI#3 AC12 T16 GND#147 GND#89 B29
AN10 AC15 C87 C123 C98 C77 C145 C86 C82 C97 C81 C78 T18 B31
C38 C50 C49 SPVSS VDDCI#4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 GND#148 GND#90
AD13 T21 B33
SW@10u/6.3V_6 SW@0.1u/10V_4 VDDCI#5 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 SW@1u/6.3V_4 GND#149 GND#91
AD16 T23 B7
SW@1u/6.3V_4 VDDCI#6 GND#150 GND#92
M15 T26 B9
VDDCI#7 GND#151 GND#93
M16 U15 C1
VOLTAGE VDDCI#8 GND#153 GND#94
VDDCI#9 M18 U17 GND#154 GND#95 C39
(1.8V@75mA SPV18) SENESE M23 U2 E35
L11 SW@SBY100505T-121Y-N/300mA/120ohm_4 VDDCI#10 +3V GND#155 GND#96
+1.8V_GPU N13 U20 E5
VDDCI#11 GND#156 GND#97
T10 AF28 N15 U22 F11
FB_VDDC VDDCI#12 C157 C69 C111 GND#157 GND#98
VDDCI#13 N17 U24 GND#158 GND#99 F13
C210 C194 N20 SW@10u/6.3V_6 SW@10u/6.3V_6 U27
VDDCI#14 GND#159
1
SW@10u/6.3V_6 T6 AG28 N22 SW@10u/6.3V_6 U6
SW@0.1u/10V_4 FB_VDDCI ISOLATED VDDCI#15 GND#160
R12 V11
CORE I/O VDDCI#16 R13 R635 V16
GND#161
VDDCI#17 *SW@0_6 GND#163
T9 AH29 R16 2 V18
120 ohm/300mA FB_GND VDDCI#18 GND#164
(1.0V@120mA SPV10) VDDCI#19
T12 V21
GND#165
+1V L8 SW@SBY100505T-121Y-N/300mA/120ohm_4 T15 V23
VDDCI#20 SW@AO3413 GND#166
VDDCI#21
V15
Q38
0.5A V26
GND#167
Y13 W2
3
C206 C197 VDDCI#22 GND#168
+3V_D_EXT W6
SW@10u/6.3V_6 GND#169
Y15
SW@0.1u/10V_4 SW@Madison/Park_M2 C806 C807 C808 GND#170
VDDC_SENSE/VSS_SENSE and Y17
Spec: 0.15A GND#171
VDDCI_SENSE/VSS_SENSE route as differetial pair Y20
SW@10u/6.3V_6 SW@0.1u/10V_4 GND#172
Rating: 3A Y22 A39
SW@1u/6.3V_4 GND#173 VSS_MECH#1
Y24 AW1
+3V GND#174 VSS_MECH#2
Y27 AW39
GPU all PWROK U13
GND#175 VSS_MECH#3
GND#152
V13 GND#162
+3V +3V
R410 GPU +3V power SW@Madison/Park_M2
A SW@10K_4 R636
*SW@0_6
1
R24
dGPU_PWROK (11) SW@4.7K_4
R403 R33 B-test
3
SW@10K_4 Fine-tune Power-on sequence 2 *SW@0_6

3
2 Q21 SW@AO3413 0.5A

SW@2N7002K Q2
3
3
+1.5V_GPU R23 *SW@0_4 2 Q1 +3V_D

SW@DTC144EUA
+1.8V_GPU 2 Q20 R19 *SW@Short_4 C84 C62 C96 Spec: 0.15A
(11,41) dGPU_VRON
1
SW@DTC144EUA C55 Rating: 3A

1
C3C *SW@1u/6.3V_4 SW@10u/6.3V_6 SW@0.1u/10V_4

SW@1u/6.3V_4 Size Document Number
1
Madison/Par
5 4 3 2
1
C
owerXpress control signal for Madsion and Park only
not used, can be disconnected.
X_EN = LOW, turn on
X_EN = HIGH, turn off
X_EN is used to turn ON/OFF some
gulators for PowerXpress mode. An
utput high ¯3.3Vˇ will turn the regulators
FF. An output low ¯0Vˇ will turn the
gulators ON. PX_EN outputs low (0V)
y default.
this signal is unused, it can be NC (not
onnected) or connected to ground.
R112 *SW@0_4 +3V_D
11
W@0_4
L21 to Ground for Broadway

PROJECT : ZQ1
mber Rev
1A
n/Park M2 (PWR/GND)
h 30, 2010 Sheet 20 of 48
1
5 4 3 2
GPU_5(VGA)
U23H (1.0V@110mA DPA_VDD10)
DPA_VDD10 L12 SW@SBY10
DP C/D POWER DP A/B POWER
DPC_VDD18 AP20 AN24 DPA_VDD18 C214 C196 C202

DPC_VDD18#1 DPA_VDD18#1 SW@10u/6.3V_6 SW@0.1u/10V_4
AP21 AP24
DPC_VDD18#2 DPA_VDD18#2 SW@1u/6.3V_4
D
DPC_VDD10 AP13 AP31 DPA_VDD10
DPC_VDD10#1 DPA_VDD10#1
AT13 DPC_VDD10#2 DPA_VDD10#2 AP32 (1.0V@110mA DPC_VDD10)
DPC_VDD10 L10 SW@SBY10
AN17 DPC_VSSR#1 DPA_VSSR#1 AN27

+1.8V_GPU AP16 AP27 C220 C211 C201
DPC_VSSR#2 DPA_VSSR#2 SW@10u/6.3V_6 SW@0.1u/10V_4
(1.8V@130mA DPA_VDD18) AP17 DPC_VSSR#3 DPA_VSSR#3 AP28
AW14 AW24 SW@1u/6.3V_4
L15 SW@SBY100505T-121Y-N/300mA/120ohm_4 DPA_VDD18 DPC_VSSR#4 DPA_VSSR#4
AW16 DPC_VSSR#5 DPA_VSSR#5 AW26
C221 C208 C199

SW@10u/6.3V_6 SW@0.1u/10V_4 DPC_VDD18 AP22 AP25 DPA_VDD18
SW@1u/10V_6 DPD_VDD18#1 DPB_VDD18#1
AP23 DPD_VDD18#2 DPB_VDD18#2 AP26
(1.8V@130mA DPC_VDD18) DPC_VDD10 AP14 AN33 DPA_VDD10

DPD_VDD10#1 DPB_VDD10#1
AP15 DPD_VDD10#2 DPB_VDD10#2 AP33
L16 SW@SBY100505T-121Y-N/300mA/120ohm_4 DPC_VDD18
C C224 C218 C209 AN19 AN29

SW@10u/6.3V_6 SW@0.1u/10V_4 DPD_VSSR#1 DPB_VSSR#1
AP18 AP29
SW@1u/10V_6 DPD_VSSR#2 DPB_VSSR#2
AP19 DPD_VSSR#3 DPB_VSSR#3 AP30
AW20 AW30
DPD_VSSR#4 DPB_VSSR#4
AW22 DPD_VSSR#5 DPB_VSSR#5 AW32
R85 SW@150/F_4 DPCD_CALR AW18 AW28 DPAB_CALR R404 SW@150/F_4

DPCD_CALR DPAB_CALR
(1.8V@20mA DPA_PVDD)
DPA_PVDD L19 SW@SBY1005
DP E/F POWER DP PLL POWER
AH34 AU28
DPE_VDD18 DPE_VDD18#1 DPA_PVDD C244 C225 C219
AJ34 DPE_VDD18#2 DPA_PVSS AV27
SW@10u/6.3V_6 SW@0.1u/10V_4
SW@1u/6.3V_4
AL33 AV29 DPB_PVDD (1.8V@20mA DPB_PVDD)

DPE_VDD10 DPE_VDD10#1 DPB_PVDD L18 SW@SBY1005
AM33 DPE_VDD10#2 DPB_PVSS AR28
+1.8V_GPU (1.8V@400mA DPE/F_VDD18)
L36 SW@HCB1608KF-181T15/1.5A/180ohm_6 DPE_VDD18 C243 C230 C227
AN34 AU18 SW@10u/6.3V_6 SW@0.1u/10V_4
DPE_VSSR#1 DPC_PVDD SW@1u/6.3V_4
AP39 DPE_VSSR#2 DPC_PVSS AV17
B C167 C536 C539 AR39
SW@0.1u/10V_4 SW@10u/6.3V_6 DPE_VSSR#3 DPC_PVDD
AU37
DPE_VSSR#4 (1.8V@20mA DPC_PVDD)
SW@1u/6.3V_4 AW35 L14 SW@SBY1005
DPE_VSSR#5
AV19
DPD_PVDD
DPD_PVSS AR18
C245 C231 C545
AF34 SW@10u/6.3V_6 SW@0.1u/10V_4
DPE_VDD18 DPF_VDD18#1 SW@1u/6.3V_4
AG34
+1V DPF_VDD18#2
(1.0V@400mA DPE/F_VDD10) DPE_PVDD
AM37
180 ohm/1.5A AN38 DPD_PVDD (1.8V@20mA DPD_PVDD)
L6 SW@HCB1608KF-181T15/1.5A/180ohm_6 DPE_VDD10 DPE_PVSS L38 SW@SBY1005
AK33 DPF_VDD10#1
DPE_VDD10 AK34
C189 C184 C205 DPF_VDD10#2 C574 C552 C546
AL38
SW@0.1u/10V_4 SW@10u/6.3V_6 NC_DPF_PVDD SW@10u/6.3V_6 SW@0.1u/10V_4
NC_DPF_PVSS AM35
SW@1u/6.3V_4 SW@1u/6.3V_4
AF39
DPF_VSSR#1
AH39
DPF_VSSR#2 (1.8V@40mA DPE/F_PVDD)
AK39 DPE_PVDD L37 SW@SBY1005
DPF_VSSR#3
AL34
DPF_VSSR#4
AM34 DPF_VSSR#5 C541 C542 C540
SW@10u/6.3V_6 SW@0.1u/10V_4
SW@1u/6.3V_4
A R399 SW@150/F_4 DPEF_CALR AM39
DPEF_CALR
SW@Madison/Park_M2
Quanta
PROJECT
Madison/Park M2 (DP_P
5 4 3 2
1
+1V
SBY100505T-121Y-N/300mA/120ohm_4
SBY100505T-121Y-N/300mA/120ohm_4
+1.8V_GPU
Y100505T-121Y-N/300mA/120ohm_4
+1.8V_GPU
Y100505T-121Y-N/300mA/120ohm_4
+1.8V_GPU B
Y100505T-121Y-N/300mA/120ohm_4
+1.8V_GPU
Y100505T-121Y-N/300mA/120ohm_4
+1.8V_GPU
Y100505T-121Y-N/300mA/120ohm_4
nta Computer Inc.

CT : ZQ1
Rev
1A
P_PWR/GND)
Sheet 21 of 48
1
5 4 3 2
PIN STRAPS(VGA)
ROM Table CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
+3V_D Manufacturer Part Number Code THEY MUST NOT CONFLICT DURING RESET
R72 *SW@10K_4 100 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS

(18) GPU_GPIO0 M25P05A
R76 *SW@10K_4
(18) GPU_GPIO1
101 TX_PWRS_ENB GPIO0 0 = 50% TX OUTPUT SWING
D M25P10A 1 = FULL TX OUTPUT SWING
Numonyx
101 TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED
R71 *SW@10K_4 ST
M25P20 0 = TX DE-EMPHASIS DISABLED
(18) GPIO3_SMBDAT
1 = TX DE-EMPHASIS ENABLED
R70 *SW@10K_4
Microelectronics 101 ENABLE EXTERNAL BIOS ROM
(18) GPIO4_SMBCLK M25P40 BIOS_ROM_EN GPIO_22_ROMCSB 0 = DISABLE
1 = ENABLE
SCS#_GPIO22 R119 *SW@10K_4 101
M25P80 ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT
NUMONYX M25P10A : 101
R107 *SW@10K_4 100
(18) GPU_GPIO13 Chingis Pm25LV512A
R114 *SW@10K_4 BIF_GEN2_EN_A GPIO2 0 = PCIE DEVICE AS 2.5GT/S CAPABLE
(18) GPU_GPIO12
PMC 101 1 = PCIE DEVICE AS 5GT/S CAPABLE
R92 *SW@10K_4
Pm25LV010A
(18) GPU_GPIO11
GPIO_8_ROMSO GPIO8
H2SYNC H2SYNC Reserved Only
R80 *SW@10K_4 GPIO_21_BB_EN GPIO21
(18) GPU_GPIO2
ROM Table AUD[1:0]
R395 SW@10K_4 AUD[1] HSYNC 00: NO AUDIO FUNCTION.
(18,25) EXT_HSYNC
EXT_HSYNC EXT_VSYNC Discription 01: AUDIO FOR DISPLAYPORT AND HDMI IF
R394 SW@10K_4 AUD[0] VSYNC ADAPTER IS DETECTED.
(18,25) EXT_VSYNC
10: AUDIO FOR DISPLAYPORT ONLY.
SIN_GPIO9 R109 *SW@10K_4 0 0 No Audio 11: AUDIO FOR BOTH DISPLAYPORT AND HDMI.
R110 *SW@10K_4 Any one by dectec

C
(18) V2SYNC
0 1 GPIO_9_ROMSI GPIO9 0 = VGA controller capacity enable
1 0 DP only VIP_DEVICE_STRAP_ENA V2SYNC 0 = DRIVER would ignore the value sample on VHAD_0 during RESET.
1 1 Both DP & HDMI
EEPROM(VGA) DDR3 Memory Aperture size(GPU)
U10
SIN_GPIO9 5 2 SOUT_GPIO8
DDR3 Memory Aperture size
(18) SIN_GPIO9 D Q SOUT_GPIO8 (18)
(18) SCLK_GPIO10 6 C RAM_STRAP2 RAM_ST

SCS#_GPIO22
Vendor Vendor P/N STN B/S P/N Size
(18) SCS#_GPIO22 1 S DVPDATA_2 DVPDAT
+3V_D_EXT 7 HOLD
B-test R115 *SW@10K_4 3 W
512Mb 1 1
8
VCC VSS
4 Hynix AKD5LZGTW04
R116 H5TQ1G63BFR-12C
*SW@10K_4 *SW@M25P10-AVMN6P (64M*16) 1Gb 1 0
C252
*SW@0.1u/10V_4
B 2Gb 1 0
512Mb
Thermal Sensor(VGA) AKD5LGGT506
K4W1G1646E-HC12 1Gb
Vendor P/N Samsung (64M*16) 0 0
WINDBOND AL83L771K01
K4W2G1646B-HC12 AKD5MGGT500 2Gb
GMT AL000780000 USD0.16
C-test
0 0
23EY2387MA12-SZ AKD5LGGT700 1Gb 0 1
+3V_D_EXT B-test
AMD
+3V_D_EXT
R398 R637 ADDRESS: 98H C535 SW@0.1u/10V_4

SW@10K_4 *SW@10K_4
U25 Samsung - 1Gb +1.8V_GPU
(35) MXM_SMCLK12 8 1 GPU_D+ (18)

SCLK VCC R134 *SW@10K_4
(18) RAM_STRAP2
C534
A
(35) MXM_SMDATA12 7
SDA DXP
2
R127 SW@10K_4 RAM_STRAP2 SET
6 3 SW@2200p/50V_4
(18) ALT#_GPIO17 ALERT# DXN
GPU_D- (18)
RAM_STRAP[1:0]
(35) VGA_THERM# 4 5
OVERT# GND R135 *SW@10K_4
(18) RAM_STRAP1
B-test SW@G780P81U R128 SW@10K_4
ADDRESS: 98H Qua
R133 *SW@10K_4
PROJ
R126 SW@10K_4 Size Document Number
(18) RAM_STRAP0
Strip/Thermal
5 4 3 2
1
DEFAULT REMARK
0 D
101 See ROM table
11 See Audio table
0 C
e
M_STRAP1 RAM_STRAP0
PDATA_1 DVPDATA_0
1 0
0 0
0 1 B
0 0
0 1
1 0
SET DDR3 Vendor A
:0] SET SIZE.

ROJECT : ZQ1
Rev
1A
Sheet 22 of 48
1
5 4 3 2
VMA_DQ[63..0]
(19) VMA_DQ[63..0]
(19) VMA_DM[7..0]
VMA_DM[7..0] CHANNEL A: 512MB DDR3 (16*64M*4pcs) Park, M92M Use Channel B Memory Interface Onl
VMA_RDQS[7..0] QSA[7..0]
(19) VMA_RDQS[7..0]
VMA_W DQS[7..0] QSA#[7..0]
(19) VMA_W DQS[7..0]
U21 U1 U20 U2
VREFC_VMA1 M8 E3 VMA_DQ10 VREFC_VMA2 M8 E3 VMA_DQ5 VREFC_VMA3 M8 E3 VMA_DQ54 VREFC_VMA4 M8

VREFD_VMA1 VREFCA DQL0 VMA_DQ14 VREFD_VMA2 VREFCA DQL0 VMA_DQ0 VREFD_VMA3 VREFCA DQL0 VMA_DQ53 VREFD_VMA4 VREFCA DQL0
H1 F7 H1 F7 H1 F7 H1
VREFDQ DQL1 VMA_DQ9 VREFDQ DQL1 VMA_DQ6 VREFDQ DQL1 VMA_DQ55 VREFDQ DQL1
F2 F2 F2
VMA_MA0 DQL2 VMA_DQ11 VMA_MA0 DQL2 VMA_DQ1 VMA_MA0 DQL2 VMA_DQ50 VMA_MA0 DQL2
N3 F8 N3 F8 N3 F8 N3
(19) VMA_MA0
(19) VMA_MA1
(19) VMA_MA2
VMA_MA1
VMA_MA2
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMA_DQ15
VMA_DQ12
1
VMA_MA1
VMA_MA2
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMA_DQ4
VMA_DQ2
0 VMA_MA1
VMA_MA2
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMA_DQ49
VMA_DQ48
6
VMA_MA1
VMA_MA2
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
VMA_MA3 N2 G2 VMA_DQ8 VMA_MA3 N2 G2 VMA_DQ7 VMA_MA3 N2 G2 VMA_DQ52 VMA_MA3 N2
D (19) VMA_MA3 A3 DQL6 A3 DQL6 A3 DQL6 A3 DQL6
VMA_MA4 P8 H7 VMA_DQ13 VMA_MA4 P8 H7 VMA_DQ3 VMA_MA4 P8 H7 VMA_DQ51 VMA_MA4 P8
(19) VMA_MA4 A4 DQL7 A4 DQL7 A4 DQL7 A4 DQL7
VMA_MA5 P2 VMA_MA5 P2 VMA_MA5 P2 VMA_MA5 P2
(19) VMA_MA5 A5 A5 A5 A5
VMA_MA6 R8 VMA_MA6 R8 VMA_MA6 R8 VMA_MA6 R8
(19) VMA_MA6 A6 A6 A6 A6
VMA_MA7 R2 D7 VMA_DQ20 VMA_MA7 R2 D7 VMA_DQ25 VMA_MA7 R2 D7 VMA_DQ63 VMA_MA7 R2
(19) VMA_MA7 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
VMA_MA8 T8 C3 VMA_DQ19 VMA_MA8 T8 C3 VMA_DQ31 VMA_MA8 T8 C3 VMA_DQ56 VMA_MA8 T8
VMA_MA9 R3 C8 VMA_DQ23 VMA_MA9 R3 C8 VMA_DQ27 VMA_MA9 R3 C8 VMA_DQ62 VMA_MA9 R3
(19) VMA_MA9
(19) VMA_MA10
(19) VMA_MA11
VMA_MA10
VMA_MA11
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMA_DQ18
VMA_DQ22
2
VMA_MA10
VMA_MA11
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMA_DQ28
VMA_DQ26 3 VMA_MA10
VMA_MA11
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMA_DQ59
VMA_DQ60
7
VMA_MA10
VMA_MA11
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
VMA_MA12 N7 A2 VMA_DQ16 VMA_MA12 N7 A2 VMA_DQ30 VMA_MA12 N7 A2 VMA_DQ58 VMA_MA12 N7
(19) VMA_MA12 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
VMA_MA13 T3 B8 VMA_DQ21 VMA_MA13 T3 B8 VMA_DQ24 VMA_MA13 T3 B8 VMA_DQ61 VMA_MA13 T3
T7 A3 VMA_DQ17 T7 A3 VMA_DQ29 T7 A3 VMA_DQ57 T7
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU A15
VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2

(19) VMA_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
VMA_BA1 N8 D9 VMA_BA1 N8 D9 VMA_BA1 N8 D9 VMA_BA1 N8
(19) VMA_BA1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
VMA_BA2 M3 G7 VMA_BA2 M3 G7 VMA_BA2 M3 G7 VMA_BA2 M3
(19) VMA_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2
VDD#K2 VDD#K2 VDD#K2 VDD#K2
K8 K8 K8
N1 N1 N1
VMA_CLK0 VDD#N1 VMA_CLK0 VDD#N1 VMA_CLK1 VDD#N1 VMA_CLK1 VDD#N1
(19) VMA_CLKP0 J7 N9 J7 N9 (19) VMA_CLKP1 J7 N9 J7
VMA_CLK0# CK VDD#N9 VMA_CLK0# CK VDD#N9 VMA_CLK1# CK VDD#N9 VMA_CLK1# CK VDD#N9
(19) VMA_CLKN0 K7 R1 K7 R1 (19) VMA_CLKN1 K7 R1 K7
VMA_CKE0 CK VDD#R1 VMA_CKE0 CK VDD#R1 VMA_CKE1 CK VDD#R1 VMA_CKE1 CK VDD#R1
(19) VMA_CKE0 K9 R9 K9 R9 (19) VMA_CKE1 K9 R9 K9
CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9
VMA_ODT0 K1 A1 VMA_ODT0 K1 A1 VMA_ODT1 K1 A1 VMA_ODT1 K1

(19) VMA_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 (19) VMA_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMA_CS0# L2 A8 VMA_CS0# L2 A8 VMA_CS1# L2 A8 VMA_CS1# L2
(19) VMA_CS0# CS VDDQ#A8 CS VDDQ#A8 (19) VMA_CS1# CS VDDQ#A8 CS VDDQ#A8
VMA_RAS0# J3 C1 VMA_RAS0# J3 C1 VMA_RAS1# J3 C1 VMA_RAS1# J3
(19) VMA_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 (19) VMA_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMA_CAS0# K3 C9 VMA_CAS0# K3 C9 VMA_CAS1# K3 C9 VMA_CAS1# K3
(19) VMA_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 (19) VMA_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMA_W E0# L3 D2 VMA_W E0# L3 D2 VMA_W E1# L3 D2 VMA_W E1# L3
(19) VMA_W E0# WE VDDQ#D2 WE VDDQ#D2 (19) VMA_W E1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9
VDDQ#E9 VDDQ#E9 VDDQ#E9 VDDQ#E9
F1 F1 F1
VMA_RDQS1 VDDQ#F1 VMA_RDQS0 VDDQ#F1 VMA_RDQS6 VDDQ#F1 VMA_RDQS5 VDDQ#F1
F3 H2 F3 H2 F3 H2 F3
VMA_RDQS2 DQSL VDDQ#H2 VMA_RDQS3 DQSL VDDQ#H2 VMA_RDQS7 DQSL VDDQ#H2 VMA_RDQS4 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9
VMA_DM1 E7 A9 VMA_DM0 E7 A9 VMA_DM6 E7 A9 VMA_DM5 E7

VMA_DM2 DML VSS#A9 VMA_DM3 DML VSS#A9 VMA_DM7 DML VSS#A9 VMA_DM4 DML VSS#A9
C D3 B3 D3 B3 D3 B3 D3
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8
VMA_W DQS1 VSS#G8 VMA_W DQS0 VSS#G8 VMA_W DQS6 VSS#G8 VMA_W DQS5 VSS#G8
G3 J2 G3 J2 G3 J2 G3
VMA_W DQS2 DQSL VSS#J2 VMA_W DQS3 DQSL VSS#J2 VMA_W DQS7 DQSL VSS#J2 VMA_W DQS4 DQSL VSS#J2
B7 J8 B7 J8 B7 J8 B7
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1
VSS#M1 VSS#M1 VSS#M1 VSS#M1
M9 M9 M9
P1 P1 P1
MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1
T2 P9 T2 P9 T2 P9 T2
(19,24) MEM_RST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1
VMA_ZQ1 VSS#T1 VMA_ZQ2 VSS#T1 VMA_ZQ3 VSS#T1 VMA_ZQ4 VSS#T1
L8 T9 L8 T9 L8 T9 L8
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
B1 B1 B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
B9 B9 B9
R383 VSSQ#B9 R5 VSSQ#B9 R380 VSSQ#B9 R7 VSSQ#B9
D1 D1 D1
VSSQ#D1 VSSQ#D1 VSSQ#D1 VSSQ#D1
SW @MD@240/F_4 D8 SW @MD@240/F_4 D8 SW @MD@240/F_4 D8 SW @MD@240/F_4
E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 F9 L1 F9 L1 F9 L1
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
SW @MD@VRAM _DDR3 SW @MD@VRAM _DDR3 SW @MD@VRAM _DDR3 SW @MD@VRAM _DDR3
TOP Left BOT Left BOT Right TOP Righ

Group-A0 VREF Group-A1 VREF
+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU
B
R381 R373 R372 R8 R1 R385 R6
SW @MD@4.99K/F_4 SW @MD@4.99K/F_4 SW @MD@4.99K/F_4 SW @MD@4.99K/F_4 SW @MD@4.99K/F_4 SW @MD@4.99K/F_4 SW @MD@4.99K/F_4
VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2 VREFC_VMA3 VREFD_VMA3 VREFC_VMA4
R382 C502 R377 C488 R376 C487 R9 C18 R375 C486 R384 C499 R10 C16
SW @MD@4.99K/F_4 SW @MD@4.99K/F_4 SW @MD@4.99K/F_4 SW @MD@4.99K/F_4 SW @MD@4.99K/F_4 SW @MD@4.99K/F_4 SW @MD@4.99K/F_4
SW @MD@0.1u/10V_4 SW @MD@0.1u/10V_4 SW @MD@0.1u/10V_4 SW @MD@0.1u/10V_4 SW @MD@0.1u/10V_4 SW @MD@0.1u/10V_4 SW @MD@0.1u/10V_4
Group-A0 decoupling CAP Group-A1 decoupling CAP MEM_A1 CLK

MEM_A0 CLK
+1.5V_GPU
+1.5V_GPU
VMA_CLK1
VMA_CLK0
VMA_CLK1
VMA_CLK0# C5 C11 C491 C10 C480 C494 C17 C501
C20 C15 C477 C484 C505 C21 C479 C6 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4
SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4
R4 R3 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4
SW @MD@56.2/F_4 +1.5V_GPU
SW @MD@56.2/F_4 +1.5V_GPU
C14 C8 C506 C493 C476 C478 C496 C492 C7

SW @MD@0.01u/16V_4 C19 C13 C489 C482 C500 C481 C12 C483 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4
A SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4
SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4 SW @MD@1u/6.3V_4
+1.5V_GPU
+1.5V_GPU
C22 C504 C474 C2 C3

C1 C4 C490 C475 C503 SW @MD@10u/6.3V_6 SW @MD@10u/6.3V_6 SW @MD@10u/6.3V_6
SW @MD@10u/6.3V_6 SW @MD@10u/6.3V_6
SW @MD@10u/6.3V_6
SW @MD@10u/6.3V_6
SW @MD@10u/6.3V_6
SW @MD@10u/6.3V_6 SW @MD@10u/6.3V_6 Qua
PRO
MEM
5 4 3 2
1
Only
E3 VMA_DQ40
DQL0 VMA_DQ44
F7
DQL1 VMA_DQ45
F2
DQL2 VMA_DQ42
F8
DQL3
DQL4
DQL5
H3
H8
VMA_DQ46
VMA_DQ41
5
G2 VMA_DQ47
DQL6 VMA_DQ43 D
H7
DQL7
D7 VMA_DQ32
DQU0 VMA_DQ36
C3
DQU1 VMA_DQ33
C8
DQU2
DQU3
DQU4
C2
A7
VMA_DQ39
VMA_DQ35 4
A2 VMA_DQ38
DQU5 VMA_DQ34
B8
DQU6 VMA_DQ37
A3
DQU7
+1.5V_GPU
B2
DD#B2
D9
DD#D9
G7
D#G7
K2
DD#K2
K8
DD#K8
N1
DD#N1
N9
DD#N9
R1
DD#R1
R9
DD#R9 +1.5V_GPU
A1
DQ#A1
A8
DQ#A8
C1
Q#C1
C9
Q#C9
D2
Q#D2
E9
DQ#E9
F1
DQ#F1
H2
Q#H2
H9
Q#H9
A9
SS#A9
B3 C
SS#B3
E1
SS#E1
G8
SS#G8
J2
SS#J2
J8
SS#J8
M1
S#M1
M9
S#M9
P1
SS#P1
P9
SS#P9
T1
SS#T1
T9
SS#T9
B1
SQ#B1
B9
SQ#B9
D1
Q#D1
D8
Q#D8
E2
SQ#E2
E8
SQ#E8
F9
SQ#F9
G1
Q#G1
G9
Q#G9
DDR3
ight
+1.5V_GPU
B
R2
SW @MD@4.99K/F_4
VREFD_VMA4
R374 C485
SW @MD@4.99K/F_4
u/10V_4 SW @MD@0.1u/10V_4
_CLK1
_CLK1#
R379 R378
SW @MD@56.2/F_4
SW @MD@56.2/F_4
C9
SW @MD@0.01u/16V_4

PROJECT : ZQ1
Rev
1A
MEMORY 1 channel A
10 Sheet 23 of 48
1
5 4 3 2
(19) VMB_DQ[63..0]
VMB_DQ[63..0] CHANNEL B: 512MB DDR3 (16*64M*4pcs)
VMB_DM[7..0]
(19) VMB_DM[7..0]
VMB_RDQS[7..0] QSA[7..0]
(19) VMB_RDQS[7..0]
VMB_W DQS[7..0] QSA#[7..0]
(19) VMB_W DQS[7..0]
U3 U22 U24 U5
VREFC_VMB1 M8 E3 VMB_DQ4 VREFC_VMB2 M8 E3 VMB_DQ19 VREFC_VMB3 M8 E3 VMB_DQ36 VREFC_VMB4 M8 E3

VREFD_VMB1 VREFCA DQL0 VMB_DQ3 VREFD_VMB2 VREFCA DQL0 VMB_DQ21 VREFD_VMB3 VREFCA DQL0 VMB_DQ39 VREFD_VMB4 VREFCA DQL0
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1 VMB_DQ5 VREFDQ DQL1 VMB_DQ17 VREFDQ DQL1 VMB_DQ33 VREFDQ DQL1
F2 F2 F2 F2
VMB_MA0 DQL2 VMB_DQ0 VMB_MA0 DQL2 VMB_DQ18 VMB_MA0 DQL2 VMB_DQ35 VMB_MA0 DQL2
N3 F8 N3 F8 N3 F8 N3 F8
(19) VMB_MA0
(19) VMB_MA1
(19) VMB_MA2
VMB_MA1
VMB_MA2
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ6
VMB_DQ1
0 VMB_MA1
VMB_MA2
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ20
VMB_DQ22
2 VMB_MA1
VMB_MA2
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_DQ37
VMB_DQ32
4 VMB_MA1
VMB_MA2
P7
P3
A0
A1
A2
DQL3
DQL4
DQL5
H3
H8
VMB_MA3 N2 G2 VMB_DQ7 VMB_MA3 N2 G2 VMB_DQ16 VMB_MA3 N2 G2 VMB_DQ38 VMB_MA3 N2 G2
D (19) VMB_MA3 A3 DQL6 A3 DQL6 A3 DQL6 A3 DQL6
VMB_MA4 P8 H7 VMB_DQ2 VMB_MA4 P8 H7 VMB_DQ23 VMB_MA4 P8 H7 VMB_DQ34 VMB_MA4 P8 H7
(19) VMB_MA4 A4 DQL7 A4 DQL7 A4 DQL7 A4 DQL7
VMB_MA5 P2 VMB_MA5 P2 VMB_MA5 P2 VMB_MA5 P2
(19) VMB_MA5 A5 A5 A5 A5
VMB_MA6 R8 VMB_MA6 R8 VMB_MA6 R8 VMB_MA6 R8
(19) VMB_MA6 A6 A6 A6 A6
VMB_MA7 R2 D7 VMB_DQ26 VMB_MA7 R2 D7 VMB_DQ15 VMB_MA7 R2 D7 VMB_DQ62 VMB_MA7 R2 D7
(19) VMB_MA7 A7 DQU0 A7 DQU0 A7 DQU0 A7 DQU0
VMB_MA8 T8 C3 VMB_DQ27 VMB_MA8 T8 C3 VMB_DQ11 VMB_MA8 T8 C3 VMB_DQ58 VMB_MA8 T8 C3
VMB_MA9 R3 C8 VMB_DQ28 VMB_MA9 R3 C8 VMB_DQ14 VMB_MA9 R3 C8 VMB_DQ63 VMB_MA9 R3 C8
(19) VMB_MA9
(19) VMB_MA10
(19) VMB_MA11
VMB_MA10
VMB_MA11
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ31
VMB_DQ24 3 VMB_MA10
VMB_MA11
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ10
VMB_DQ12 1 VMB_MA10
VMB_MA11
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_DQ56
VMB_DQ61 7 VMB_MA10
VMB_MA11
L7
R7
A9
A10/AP
A11
DQU2
DQU3
DQU4
C2
A7
VMB_MA12 N7 A2 VMB_DQ29 VMB_MA12 N7 A2 VMB_DQ9 VMB_MA12 N7 A2 VMB_DQ57 VMB_MA12 N7 A2
(19) VMB_MA12 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5 A12/BC DQU5
VMB_MA13 T3 B8 VMB_DQ25 VMB_MA13 T3 B8 VMB_DQ13 VMB_MA13 T3 B8 VMB_DQ60 VMB_MA13 T3 B8
T7 A3 VMB_DQ30 T7 A3 VMB_DQ8 T7 A3 VMB_DQ59 T7 A3
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
M7 M7 M7 M7
A15 +1.5V_GPU A15 +1.5V_GPU A15 +1.5V_GPU A15
VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2 VMB_BA0 M2 B2

(19) VMB_BA0 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2 BA0 VDD#B2
VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9 VMB_BA1 N8 D9
(19) VMB_BA1 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9 BA1 VDD#D9
VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7 VMB_BA2 M3 G7
(19) VMB_BA2 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7 BA2 VDD#G7
K2 K2 K2 K2
K8 K8 K8 K8
N1 N1 N1 N1
VMB_CLK0 VDD#N1 VMB_CLK0 VDD#N1 VMB_CLK1 VDD#N1 VMB_CLK1 VDD#N1
(19) VMB_CLKP0 J7 N9 J7 N9 (19) VMB_CLKP1 J7 N9 J7 N9
VMB_CLK0# CK VDD#N9 VMB_CLK0# CK VDD#N9 VMB_CLK1# CK VDD#N9 VMB_CLK1# CK VDD#N9
(19) VMB_CLKN0 K7 R1 K7 R1 (19) VMB_CLKN1 K7 R1 K7 R1
VMB_CKE0 CK VDD#R1 VMB_CKE0 CK VDD#R1 VMB_CKE1 CK VDD#R1 VMB_CKE1 CK VDD#R1
(19) VMB_CKE0 K9 R9 K9 R9 (19) VMB_CKE1 K9 R9 K9 R9
CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9 +1.5V_GPU CKE VDD#R9
VMB_ODT0 K1 A1 VMB_ODT0 K1 A1 VMB_ODT1 K1 A1 VMB_ODT1 K1 A1

(19) VMB_ODT0 ODT VDDQ#A1 ODT VDDQ#A1 (19) VMB_ODT1 ODT VDDQ#A1 ODT VDDQ#A1
VMB_CS0# L2 A8 VMB_CS0# L2 A8 VMB_CS1# L2 A8 VMB_CS1# L2 A8
(19) VMB_CS0# CS VDDQ#A8 CS VDDQ#A8 (19) VMB_CS1# CS VDDQ#A8 CS VDDQ#A8
VMB_RAS0# J3 C1 VMB_RAS0# J3 C1 VMB_RAS1# J3 C1 VMB_RAS1# J3 C1
(19) VMB_RAS0# RAS VDDQ#C1 RAS VDDQ#C1 (19) VMB_RAS1# RAS VDDQ#C1 RAS VDDQ#C1
VMB_CAS0# K3 C9 VMB_CAS0# K3 C9 VMB_CAS1# K3 C9 VMB_CAS1# K3 C9
(19) VMB_CAS0# CAS VDDQ#C9 CAS VDDQ#C9 (19) VMB_CAS1# CAS VDDQ#C9 CAS VDDQ#C9
VMB_W E0# L3 D2 VMB_W E0# L3 D2 VMB_W E1# L3 D2 VMB_W E1# L3 D2
(19) VMB_W E0# WE VDDQ#D2 WE VDDQ#D2 (19) VMB_W E1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 VDDQ#E9 VDDQ#E9 VDDQ#E9
F1 F1 F1 F1
VMB_RDQS0 VDDQ#F1 VMB_RDQS2 VDDQ#F1 VMB_RDQS4 VDDQ#F1 VMB_RDQS6 VDDQ#F1
F3 H2 F3 H2 F3 H2 F3 H2
VMB_RDQS3 DQSL VDDQ#H2 VMB_RDQS1 DQSL VDDQ#H2 VMB_RDQS7 DQSL VDDQ#H2 VMB_RDQS5 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7 H9
DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9 DQSU VDDQ#H9
VMB_DM0 E7 A9 VMB_DM2 E7 A9 VMB_DM4 E7 A9 VMB_DM6 E7 A9

VMB_DM3 DML VSS#A9 VMB_DM1 DML VSS#A9 VMB_DM7 DML VSS#A9 VMB_DM5 DML VSS#A9
C D3 B3 D3 B3 D3 B3 D3 B3
DMU VSS#B3 DMU VSS#B3 DMU VSS#B3 DMU VSS#B3
E1 E1 E1 E1
VSS#E1 VSS#E1 VSS#E1 VSS#E1
G8 G8 G8 G8
VMB_W DQS0 VSS#G8 VMB_W DQS2 VSS#G8 VMB_W DQS4 VSS#G8 VMB_W DQS6 VSS#G8
G3 J2 G3 J2 G3 J2 G3 J2
VMB_W DQS3 DQSL VSS#J2 VMB_W DQS1 DQSL VSS#J2 VMB_W DQS7 DQSL VSS#J2 VMB_W DQS5 DQSL VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8 DQSU VSS#J8
M1 M1 M1 M1
M9 M9 M9 M9
P1 P1 P1 P1
MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1 MEM_RST# VSS#P1
T2 P9 T2 P9 T2 P9 T2 P9
(19,23) MEM_RST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMB_ZQ1 VSS#T1 VMB_ZQ2 VSS#T1 VMB_ZQ3 VSS#T1 VMB_ZQ4 VSS#T1
L8 T9 L8 T9 L8 T9 L8 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
B1 B1 B1 B1
VSSQ#B1 VSSQ#B1 VSSQ#B1 VSSQ#B1
B9 B9 B9 B9
R32 VSSQ#B9 R389 VSSQ#B9 R62 VSSQ#B9 R65 VSSQ#B9
D1 D1 D1 D1
SW @240/F_4 D8 SW @240/F_4 D8 SW @240/F_4 D8 SW @240/F_4 D8
E2 E2 E2 E2
VSSQ#E2 VSSQ#E2 VSSQ#E2 VSSQ#E2
J1 E8 J1 E8 J1 E8 J1 E8
NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8 NC#J1 VSSQ#E8
L1 F9 L1 F9 L1 F9 L1 F9
NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9 NC#L1 VSSQ#F9
J9 G1 J9 G1 J9 G1 J9 G1
NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1 NC#J9 VSSQ#G1
L9 G9 L9 G9 L9 G9 L9 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
100-BALL 100-BALL 100-BALL 100-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
SW @VRAM _DDR3 SW @VRAM _DDR3 SW @VRAM _DDR3 SW @VRAM _DDR3
BOT Down TOP Down TOP Up BOT Up
Group-B0 VREF Group-B1 VREF

+1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GP
B
R34 R13 R391 R388 R56 R393 R52 R74

SW @4.99K/F_4 SW @4.99K/F_4 SW @4.99K/F_4 SW @4.99K/F_4 SW @4.99K/F_4 SW @4.99K/F_4 SW @4.99K/F_4 SW @
VREFC_VMB1 VREFD_VMB1 VREFC_VMB2 VREFD_VMB2 VREFC_VMB3 VREFD_VMB3 VREFC_VMB4
R35 C76 R21 C35 R390 C517 R387 C512 R57 C171 R392 C520 R58 C163 R75
SW @4.99K/F_4 SW @4.99K/F_4 SW @4.99K/F_4 SW @4.99K/F_4 SW @4.99K/F_4 SW @4.99K/F_4 SW @4.99K/F_4 SW @
SW @0.1u/10V_4 SW @0.1u/10V_4 SW @0.1u/10V_4 SW @0.1u/10V_4 SW @0.1u/10V_4 SW @0.1u/10V_4 SW @0.1u/10V_4
Group-B0 decoupling CAP Group-B1 decoupling CAP MEM_B1 CLK

MEM_B0 CLK
+1.5V_GPU +1.5V_GPU
VMB_CLK1
VMB_CLK0 VMB_CLK1#
C514 C529 C508 C515 C511 C28 C235 C507 C141 C204 C216 C155 C532 C74 C538 C537
VMB_CLK0# SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4
SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4
R25 R22
SW @56.2/F_4 +1.5V_GPU +1.5V_GPU
SW @56.2/F_4
A
C518 C133 C23 C44 C531 C93 C32 C236 C510 C226 C570 C232 C543 C530 C217 C509
C61 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4
SW @0.01u/16V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4 SW @1u/6.3V_4
+1.5V_GPU +1.5V_GPU
Qua
C519 C26 C498 C497 C516 C223 C72 C524 C571 C569
SW @10u/6.3V_6 SW @10u/6.3V_6 SW @10u/6.3V_6 SW @10u/6.3V_6 SW @10u/6.3V_6 SW @10u/6.3V_6
SW @10u/6.3V_6 SW @10u/6.3V_6 SW @10u/6.3V_6 SW @10u/6.3V_6 PRO
MEM
5 4 3 2
1
E3 VMB_DQ52
0 VMB_DQ50
F7
1 VMB_DQ55
F2
2 VMB_DQ49
F8
3
4
5
H3
H8
VMB_DQ53
VMB_DQ48
6
G2 VMB_DQ54
6 VMB_DQ51 D
H7
7
D7 VMB_DQ40
0 VMB_DQ47
C3
1 VMB_DQ42
C8
2
3
4
C2
A7
VMB_DQ46
VMB_DQ43 5
A2 VMB_DQ45
5 VMB_DQ41
B8
6 VMB_DQ44
A3
7
+1.5V_GPU
B2
2
D9
9
G7
7
K2
2
K8
8
N1
1
N9
9
R1
1
R9
9 +1.5V_GPU
A1
1
A8
8
C1
1
C9
9
D2
2
E9
9
F1
1
H2
2
H9
9
A9
9
B3 C
3
E1
1
G8
8
J2
2
J8
8
M1
1
M9
9
P1
1
P9
9
T1
1
T9
9
B1
1
B9
9
D1
1
D8
8
E2
2
E8
8
F9
9
G1
1
G9
9
.5V_GPU
B
R74
SW @4.99K/F_4
VREFD_VMB4
R75 C195
SW @4.99K/F_4
SW @0.1u/10V_4
K1
K1#
R396 R397
SW @56.2/F_4
SW @56.2/F_4
C533 A
SW @0.01u/16V_4

PROJECT : ZQ1
Rev
1A
MEMORY 2 channel B
10 Sheet 24 of 48
1
1 2 3 4 5 6 7
CRT(CRT) +5V
C573 0.22u/6.3V_4
1A/30V
C3C
INT_CRT_RED R83 IV@0_4 VGA_RED_SYS D7
C207 INT_CRT_GRN R88 IV@0_4 VGA_GRN_SYS F1 2 1 SMD1206P100TF CRTVDD5
16
+5V 2 1
SW @0.22u/6.3V_4 U6 INT_CRT_BLU R87 IV@0_4 VGA_BLU_SYS CN15
16 8 INT_VSYNC R400 IV@0_4 VSYNC RSX101M-30 CRT
VCC GND INT_HSYNC R401 IV@0_4 HSYNC 6
C3C INT_CRT_DDCDAT R98 IV@0_4 CRTDDAT VGA_RED_SYS L41 BLM18BA470SN1/300mA/47ohm_6 CRT_R1 1 11 CR
2 INT_CRT_DDCCLK R91 IV@0_4 CRTDCLK 7
(18) EXT_CRT_RED IA0
5 4 VGA_RED_SYS INT_LVDS_EDIDDATA R90 IV@0_4 LCD_EDIDDATA VGA_GRN_SYS L40 BLM18BA470SN1/300mA/47ohm_6 CRT_G1 2 12 DD
(18) EXT_CRT_GRN IB0 YA
11 INT_LVDS_EDIDCLK R97 IV@0_4 LCD_EDIDCLK 8
(18) EXT_CRT_BLU IC0
14 7 VGA_GRN_SYS VGA_BLU_SYS L39 BLM18BA470SN1/300mA/47ohm_6 CRT_B1 3 13 CR
ID0 YB
9
3 9 VGA_BLU_SYS 4 14 CR
(8) INT_CRT_RED IA1 YC
6 R413 R412 R411 C598 C596 C578 C579 C597 C599 10
(8) INT_CRT_GRN IB1
10 12 5 15 DD
A (8) INT_CRT_BLU IC1 YD
13 150/F_4 150/F_4 150/F_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4 10p/50V_4
ID1
17
dGPU_SELECT# 1 15 C3C
S OE C3B
SW @SN74CBT3257CPW R +5V R99 *SW @Short_6 +3V
U8
S Yn +5V C241 SW @0.22u/6.3V_4 16 8
VCC GND
0 EV 2
+3V
(18) EV_CRTDDAT IA0
C544 5 4 CRTDDAT R89 R95 C254 R101 *short_4 CRTVSYNC
U26 (18) EV_CRTDCLK IB0 YA
SW @0.22u/6.3V_4 R113 *short_4 CRTHSYNC
1 IV 16 8
(18) EV_LVDS_DDCDAT 11
14
IC0
7 CRTDCLK 2.2K_4 2.2K_4 0.1u/10V_4 U11
VCC GND (18) EV_LVDS_DDCCLK ID0 YB +3V
CRTVDD5 1 16 CRT_VSYNC1
LCD_EDIDDATA VCC_SYNC SYNC_OUT2 CRT_HSYNC1
(8) INT_CRT_DDCDAT 3 9 14
IA1 YC SYNC_OUT1 B-test
(18) EV_LVDS_BLON 2 (8) INT_CRT_DDCCLK 6 7
IA0 LVDS_BLON IB1 LCD_EDIDCLK C256 0.22u/25V_6 CRT_BYP VCC_DDC
(18) EV_LVDS_VDDEN 5 4 (8) INT_LVDS_EDIDDATA 10 12 8
IB0 YA IC1 YD BYP VSYNC C572 0.1u/
(18,22) EXT_VSYNC 11 (8) INT_LVDS_EDIDCLK 13 15
IC0 LVDS_VDDEN ID1 SYNC_IN2 HSYNC R104 R103 CRTVDD5
(18,22) EXT_HSYNC 14 7 +3V 2 13
ID0 YB VCC_VIDEO SYNC_IN1 2.7K_4 2.7K_4 C238 *10p/
3 9 VSYNC 1 15 C255
(8) INT_LVDS_BLON IA1 YC (10) dGPU_EDIDSEL# S OE
6 CRT_R1 3 10 CRTDCLK R105 R102 C246 *10p/
(8) INT_LVDS_DIGON IB1 VIDEO_1 DDC_IN1
10 12 HSYNC SW @SN74CBT3257CPW R 0.1u/10V_4 CRT_G1 4 11 CRTDDAT 2.7K_4 2.7K_4
(8) INT_VSYNC IC1 YD VIDEO_2 DDC_IN2
13 CRT_B1 5 C551 10p/5
(8) INT_HSYNC ID1 VIDEO_3
9 DDCCLK_1
DDC_OUT1 DDCDAT_1 C239 10p/5
6 12
dGPU_SELECT# 1 GND DDC_OUT2
15
S OE
CM2009-02QR
SW @SN74CBT3257CPW R
LVDS(LDS) LCD Power(LDS)

B +3V +3V
+3V VIN
S Yn
C240 0 EV U7
C30 C39 C71 C90 C233
SW @0.22u/6.3V_4 1u/6.3V_4 6 1 LCD
0.1u/10V_4 1000p/50V_4 4.7u/25V_8 1000p/50V_4 IN OUT
C3C U9 1 IV 4 2
IN GND C242 C237 C234
R106 *SW @Short_4 5 6 LVDS_VDDEN 3 5
(35) CONTRAST VCC S PW M_SELECT# (10) ON/OFF GND 1u/6.3V_4 *0.1u/10V_4 0.01u/1
R100 *SW @0_4 3 4 LVDS_BRIGHT_R R666 LVDS_BRIGHT AAT4280-4

(18) EV_LVDS_BRIGHT B0 YA SBY100505T-121Y-N/300mA/120ohm_4 R86
1 2 C3C 100K_4
(8) INT_LVDS_BRIGHT B1 GND
SW @74LVC1G3157GW CN5
G_0
+3V LCDVCC
1
R96 IV@0_4 2
3 G_1
LCD_EDIDCLK 4
LCD_EDIDDATA 5
6
U4 TXLOUT0- 7
TXLOUT0+ 8
TXLCLKOUT+ 9
(18) EV_TXLCLKOUT+ 46 6
A2P C2P TXLCLKOUT- TXLOUT1- 10
(18) EV_TXLCLKOUT- 45 7
A2N C2N TXLOUT1+ 11
TXLOUT2+ 12
(18) EV_TXLOUT2+ 44 9
A1P C1P TXLOUT2- TXLOUT2- 13
(18) EV_TXLOUT2- 43 10
A1N IN_A OUT_C C1N +1.8V TXLOUT2+ 14
TXLOUT1+ 15 G_2
(18) EV_TXLOUT1+ 41 15
A0P C0P TXLOUT1- TXLCLKOUT- 16
(18) EV_TXLOUT1- 40 16
3
A0N C0N TXLCLKOUT+ 17

C
TXLOUT0+ 18
(18) EV_TXLOUT0+ 39 18
ACLKP CCLKP TXLOUT0- 19
(18) EV_TXLOUT0- 38 19
ACLKN CCLKN 20
2 dGPU_SELECT# (10) 21
Q5 B-test 22
SW @2N7002K LVDS_BRIGHT 23
BL_ON 24
(8) INT_TXLCLKOUT+ 35
1
B2P LVDS_SEL# 25
(8) INT_TXLCLKOUT- 34 13 (35) DCR_EN
B2N SEL VIN 26
27
(8) INT_TXLOUT2+ 33
B1P 0.8A 28 G_4
32 R37 R39 *Short_8
(8) INT_TXLOUT2- B1N 29
1 SW @100K_4 R38 *Short_8 INVCC0
VSS 30
G_3
(8) INT_TXLOUT1+ 30 3
B0P VSS C3C
(8) INT_TXLOUT1- 29 5
B0N IN_B VSS LVD-A30SFYG+
8
VSS B-test
(8) INT_TXLOUT0+ 28 11
+1.8V BCLKP VSS
(8) INT_TXLOUT0- 27 14
BCLKN VSS
17
R81 *SW @Short_6 +1.8V_LVDS 48
VDD
VSS
VSS
20 Backlight Control(LDS)
36 22
C3C C215 C213 C156 25
VDD
VDD
VSS
VSS
24 CCD&DMIC Conn.(CCD) B-test
23 26
*SW @2.2u/6.3V_6 SW @0.1u/10V_4 VDD VSS +3V
21 31
*SW @0.1u/10V_4 VDD VSS
12 37
VDD VSS CN4
4 42
VDD VSS R12 *Short_6 CCD_POW ER
2 47 +3V 1
VDD VSS
2
2~3pin share one cap C3C USBP8-_R 3 R43
SW @PI3HDMI412 USBP8+_R 4 10K_4
5
6 BL_ON D1 2 1 BAS316 LID5
7 9 R42
(30) DMIC_CLK
(30) DMIC_DAT 8 10
10K_4
3
CCD&MIC
3
D BL# 2
2
3
Q7
INT_LVDS_DIGON RN5 1 2 IV@0_4P2R LVDS_VDDEN 2N7002K Q8
INT_LVDS_BLON 3 4 LVDS_BLON CAMERA Module(CCD) DTC144EUA
1
INT_TXLCLKOUT+ RN1 3 4 IV@0_4P2R TXLCLKOUT+ LVDS_BLON 2
INT_TXLCLKOUT- 1 2 TXLCLKOUT-
INT_TXLOUT0+ RN4 3 4 IV@0_4P2R TXLOUT0+ Q6
dGPU_SELECT# Output INT_TXLOUT0- 1 2 TXLOUT0- L1 2N7002K
TI AL3DV421V00 INT_TXLOUT1+ RN3 3 4 IV@0_4P2R TXLOUT1+ 4 3 USBP8-_R R41
(10) USBP8-
1
INT_TXLOUT1- TXLOUT1- 4 3 USBP8+_R
1 2 1 2
L EV_LVDS INT_TXLOUT2+
INT_TXLOUT2-
RN2 3 4 IV@0_4P2R TXLOUT2+
TXLOUT2-
(10) USBP8+ 1 2 100K_4 Qua
Pericom AL000412W00 1 2 DLW 21HN900SQ2L/330mA/90ohm
H INT_LVDS
PRO
F3A
CRT
1 2 3 4 5 6 7
8
CRT_11 T94
DDCDAT_1
CRTHSYNC
CRTVSYNC
DDCCLK_1
A
0.1u/10V_4 CRTVDD5
*10p/50V_4 CRTVSYNC
*10p/50V_4 CRTHSYNC
10p/50V_4 DDCCLK_1
10p/50V_4 DDCDAT_1
LCDVCC_R R409 *Short_8 LCDVCC
C3C
C234 C247
0.01u/16V_4 22u/6.3V_8
6 LID591# LID591# (32,35)
D
EC_FPBACK# (35)

PROJECT : ZQ1
Rev
1A
CRT/LVDS
10 Sheet 25 of 48
8
5 4 3 2
HDMI HPD(HDM) HDMI LEVEL SHIFTER(HDM) PS8101 :: AL008101000

+3V C3C
HDMI_MB_HP R439 *IV@Short_6 +3V_HDMI
+3V_HDMI R433 *IV@4.7K_4 HDMI_DDCDATA C628 C654 C

HDMI_DDCCLK
DDCBUF_EN IV@2.2u/6.3V_6 IV@.1u/10V_4 IV
CFG
+3V +3V +3V_HDMI +3V_HDMI C-test
Active Buffer HP_EV
D
R143 R424
OE# control for power saving
36
35
34
33
32
31
30
29
28
27
26
25
10K_4 SW@10K_4 U27
CCT2
CCT1
HPD_SINK
SDA_SINK
SCL_SINK
OE#
GND
VCC
DDC_EN
GND
GND
VCC
B-test C3C
EXT_HDMI_HPD (18)
3
R638 *Short_4 37 24
(35) HDMI_HPD_EC# GND GND
38 23 HDMI_TX0N
(8) INT_HDMITX0N IN_D1- OUT_D1-
R639 *0_4 39 22 HDMI_TX0P
(9) HDMI_HPD_PCH# (8) INT_HDMITX0P IN_D1+ OUT_D1+
HP_EV 2 +3V_HDMI 40 21 +3V_HDMI PC0 interna
VCC VCC HDMI_CLK-
(8) INT_HDMICLK- 41 20 PC1 interna
IN_D2- OUT_D2-
3
Q25 42 19 HDMI_CLK+
(8) INT_HDMICLK+ IN_D2+ OUT_D2+ DDCBUF_EN i
SW@2N7002K From INT 43 18
GND GND HDMI_TX1N
(8) INT_HDMITX1N 44 17 CFG interna
1
HDMI_MB_HP IN_D3- OUT_D3- HDMI_TX1P
2 (8) INT_HDMITX1P 45 16 DDC_EN inte
IN_D3+ OUT_D3+
+3V_HDMI 46 VCC VCC 15 +3V_HDMI
Q11 47 14 HDMI_TX2N
(8) INT_HDMITX2N IN_D4- OUT_D4-
2N7002K 48 13 HDMI_TX2P
(8) INT_HDMITX2P IN_D4+ OUT_D4+
49
HPDEN
HPD_S
SDA_S
1
SCL_S
GND
REXT
TRIM
GND
GND
GND
VCC
VCC
NC
C-test IV@PS8101
1
2
3
4
5
6
7
8
9
10
11
12
+3V_HDMI
C R460 *IV@4.7K_4
+3V_HDMI +3V_HDMI
LS_REXT
PC0 R459 IV@4.7K_4
PC1
R431 *IV@4.7K_4
R461 IV@499/F_4 R432 *IV@4.7K_4
(8) INT_HDMI_HPD
Equalization Control (8) SDVO_CTRLDAT
(8) SDVO_CTRLCLK
PC1 PC0 R463 IV@4.7K_4
R462 IV@4.7K_4
PIN4 PIN3 EQ Control +3V_HDMI
L L 8dB
L H 4dB
H L 12dB
H H 0dB
+5V
(HDM) D9 RB501V-40 EMI reserve for HDMI(HDM) HDMI connector(HDM)
2 1
C3B D10 RB501V-40
2 1
R664 R665
B
SW@1.5K_4 SW@1.5K_4 ESD Protect HDMI_TX2P
2
Q43 Q44 R437 R440

SW@BSN20 SW@BSN20 1.5K_4 1.5K_4 HDMI_TX2N
1 3 1 3 close to HDMI connector HDMI_TX1P
HDMI_TX2P
U14 HDMI_TX1N
R435 *SW@0_4 HDMI_DDCCLK R155 HDMI_CLK+ 1 10 HDMI_CLK+ HDMI_TX0P
(18) EV_HDMI_DDCCK 1 10
R434 *SW@0_4 HDMI_DDCDATA *100/F_4 HDMI_CLK- 2 9 HDMI_CLK-
(18) EV_HDMI_DDCDAT 2 9
HDMI_TX2N 3 +5V HDMI_TX0N
C305 SW@0.1u/10V_4 HDMI_TX2N HDMI_DDCCLK GND_3/8 HDMI_DDCCLK HDMI_CLK+
(18) EXT_HDMITX2N 4 7
C310 SW@0.1u/10V_4 HDMI_TX2P HDMI_TX1P HDMI_DDCDATA 4 7 HDMI_DDCDATA
(18) EXT_HDMITX2P 5 5 6 6
HDMI_CLK-
C297 SW@0.1u/10V_4 HDMI_TX1N R154 *RClamp0524P
(18) EXT_HDMITX1N C-test
C303 SW@0.1u/10V_4 HDMI_TX1P *100/F_4 R427
(18) EXT_HDMITX1P
HDMI_TX1N *10K_4 HDMI_DDCCLK
C278 SW@0.1u/10V_4 HDMI_TX0N U15 F2 HDMI_DDCDATA
(18) EXT_HDMITX0N
C282 SW@0.1u/10V_4 HDMI_TX0P HDMI_TX0P HDMI_TX2P 1 10 HDMI_TX2P SMD1206P100TF D8 RSX101M
(18) EXT_HDMITX0P 1 10
HDMI_TX2N 2 9 HDMI_TX2N 2 1 2 1
C289 SW@0.1u/10V_4 HDMI_CLK- R150 2 9 HDMI_MB_HP
(18) EXT_HDMICLK- 3
C293 SW@0.1u/10V_4 HDMI_CLK+ *100/F_4 HDMI_TX1P GND_3/8 HDMI_TX1P
(18) EXT_HDMICLK+ 4 7
HDMI_TX0N HDMI_TX1N 4 7 HDMI_TX1N
5 6
5 6 R430
From EXT VGA R443 R442 R441 R438 R449 R446 R454 R452 HDMI_CLK+ *RClamp0524P C617
*0.1u/10V_4 100K_4
SW@499/F_4 SW@499/F_4 SW@499/F_4 SW@499/F_4 R152
SW@499/F_4 SW@499/F_4 SW@499/F_4 SW@499/F_4 *100/F_4 U13
HDMI_CLK- HDMI_TX0P 1 10 HDMI_TX0P
1 10
3
A HDMI_TX0N 2 9 HDMI_TX0N
2 9
3
HDMI_MB_HP GND_3/8 HDMI_MB_HP
4 4 7 7
+5V 2 Close connector 5
5 6
6
Q30 *RClamp0524P
R456 SW@2N7002K
B-test
Qu
SW@100K_4
1
PRO
HDMI
5 4 3 2
1
MI
C622 C639 C655
_4 IV@.1u/10V_4 IV@.1u/10V_4 IV@.1u/10V_4
ernal PD
ernal PD
internal PD
ernal PD
internal PU
7K_4 PC1 C
K_4 PC0
7K_4 CFG
7K_4 DDCBUF_EN
CN18
20
SHELL1 B
1 22
D2+SHELL3
2
D2 Shield
3
D2-
4
D1+
5 D1 Shield
6
D1-
7
D0+
8
D0 Shield
9 D0-
10
CK+
11 CK Shield
12
CK-
13
CE Remote
14
NC
15
A DDC CLK
16
SX101M-30 DDC DATA
17
+5V_HDMI 18 GND
1 +5V
19 23
HP DET
SHELL4
21
SHELL2
C620 QJ1119C-NK01-8F
0.22u/6.3V_4

PROJECT : ZQ1
Rev
1A
10 Sheet 26 of 48
1
5 4 3 2
Giga-LAN AR8151(LAN)
close Pin1
+3V_S5 30mil
C-test
R522 *Short_6 +3V_LAN
C3C C712 C714 C708 C702 C694 U32
10u/6.3V_8 10u/6.3V_8 1u/6.3V_4 0.1u/10V_4 *1000p/50V_4 1 22 AVDDH C687 0.1u/10V_4

VDD33 AVDDH
2 23 LED2 T99
(4,10,11,28,31,35) PLTRST# PERSTn CLKREQn/LED2
D 3 24 DVDDL C686 0.1u/10V_4
(8) PCIE_WAKE# B-test WAKEn DVDDL
R523 *Short_4 8151_CLKREQ# 4 25 SMCLK_8151 R506 *0_4
(10) CLK_PCIE_LAN_REQ# CLKREQn SMCLK SMB_CLK_ME0 (10)
C697 0.1u/10V_4 +VDDCT 5
VDDCT
AR8151
5X5mm SMDATA
26 SMDATA_8151 R505 *0_4
SMB_DATA_ME0 (10)
C698 1u/6.3V_4 20mil AVDDL 6 40-Pin QFN 27 SMBus PU at PCH side already
AVDDL_REG TESTMODE
C699 0.1u/10V_4 XTLO 7 28 R648 *0_4 AVDDH C-test
XTLO TEST_RST For EMI
XTLI 8 29 PCIE_RXN1_C C685 0.1u/10V_4
XTLI TX_N PCIE_RX1- (10)
C700 1u/6.3V_4 20mil AVDDH 9 30 PCIE_RXP1_C C684 0.1u/10V_4
AVDDH_REG TX_P PCIE_RX1+ (10)
C701 0.1u/10V_4 R511 2.37K/F_4 RBIAS 10 31 AVDDL C689 0.1u/10V_4
RBIAS AVDDL
TX0P 11 32
TRXP0 REFCLK_N CLK_PCIE_LOM# (10)
Wake# and CLKREQ# PU at PCH side already TX0N 12 33
TRXN0 REFCLK_P CLK_PCIE_LOM (10)
C386 0.1u/10V_4 AVDDL 13 34 AVDDL C690 0.1u/10V_4
NC/AVDDL AVDDL
TX1P 14 35
TRXP1 RX_P PCIE_TX1+ (10)
TX1N 15 36
TRXN1 RX_N PCIE_TX1- (10)
C383 0.1u/10V_4 AVDDH 16 37 DVDDL C692 1u/6.3V_4
C709 33p/50V_4 XTLO NC/AVDDH DVDDL_REG C691 0.1u/10V_4
TX2P 17 38 LAN_ACTLED R510 5.1K_4
NC/TRXP2 LED0
1
1.2H Y5 TX2N 18 39 LAN_LINKLED#

25MHz NC/TRXN2 LED1
C376 0.1u/10V_4 AVDDL 19 40 LX 40mil L47 4.7uH/1A_2X2 +VDDCT
2
C
C710 33p/50V_4 XTLI NC/AVDDL LX
TX3P 20 41 C706 C707 C713
NC/TRXP3 GND
TX3N 21 NC/TRXN3
*1000p/50V_4 0.1u/10V_4 10u/6.3V_8 RJ45(LAN)
AR8151
TRANSFORMER(LAN)
C
9
LAN_ACTLED R478 220_8 10
TX0P
TX1P
TX0N
TX1N
R226
R224
R223
R222
X-TX0P 1
X-TX0N 2
X-TX1P 3
Close Transformer U28 X-TX2P 4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
X-TX2N 5
X-TX1N 6
AVDD_CEN L45 +VDDCT X-TX3P 7
PBY160808T-181Y-N/2A/180ohm_6 X-TX3N 8
LAN_N1
LAN_N2
C680 1u/6.3V_4 +3V_LAN

LAN_LINKLED# 11
R502 220_8 LAN_LNK_LED_PWR 12
U30
B C388 C384 C674 0.1u/10V_4 1 24 R
C811 5.6pF/50V_4 L60 4.7nH/1.3A_4 TX0P TCT1 MCT1 X-TX0P
2 23
0.1u/10V_4 0.1u/10V_4 C812 5.6pF/50V_4 L61 4.7nH/1.3A_4 TX0N TD1+ MX1+ X-TX0N
3 22
TD1- MX1-
C675 0.1u/10V_4 4 21
5 TD2+ MX2+ 20
C814 5.6pF/50V_4 L63 4.7nH/1.3A_4 TX1N 6 19 X-TX1N
TD2- MX2-
C676 0.1u/10V_4 7 18
8 TD3+ MX3+ 17
TD3- MX3-
TX2P
TX3P
TX2N
TX3N
C678 0.1u/10V_4 10 15
11 TD4+ MX4+ 14
R221
R220
R217
R216

TD4- MX4- LAN_ACTLED
D3D TRANSFORMER
B-test LAN_LINKLED#
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
R179 R189 R199 R208

75/F_8 75/F_8 75/F_8 75/F_8
C334 C683
Delta LFE9276C-R (DB0ZR1LAN00)
LAN_N3
LAN_N4
*0.1u//50V_8 *0.1u//50V_8
FCE NS892407 (DB0LL1LAN00)
Bothhand GST5009B (DB0Z06LAN00)
C368 C356 C350
1500p/3KV_18
0.1u/10V_4 0.1u/10V_4
Qu
PRO
LAN
5 4 3 2
1
CN19
9
YELLOW_N
10
YELLOW_P
14
GND2
1 13
0+ GND1
2
0-
3
1+
4
2+
5
2-
6 1-
7
3+
8
3-
11
GREEN_N
12 GREEN_P
RJ45 B

PROJECT : ZQ1
Rev
1A
LAN (AR8151)
10 Sheet 27 of 48
1
5 4 3 2
MINI-CARD WLAN(MPC)
+3V
+WL_VDD
+3.3V: 1000mA
+3.3Vaux:330mA
H=5.6mm R280 *Short_8 +WL_VDD
CN23
+1.5V:500mA 51 52 C3C
Reserved +3.3V +WL_VDD
R242 *0_4 CL_RST1#_WLAN 49 50 R521 C422 C771 C734 C400
(10) CL_RST1# Reserved GND
R275 *0_4 CL_DATA1_WLAN 47 48 +1.5V *10K_4 Active Low 10u/10V_8 0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4
(10) CL_DATA1 Reserved +1.5V
R274 *0_4 CL_CLK1_WLAN 45 46
(10) CL_CLK1 Reserved LED_WPAN#
43 44 RF_LED#
Reserved LED_WLAN# RF_LED# (33,35)
+WL_VDD 41 42
Reserved LED_WWAN#
39 40
D Reserved GND
37 38 USBP13+ (10)
Reserved USB_D+
35 36 USBP13- (10)
GND USB_D-
(10) PCIE_TX6+ 33 34
PETp0 GND R261 *0_4
(10) PCIE_TX6- 31 32 CLK_SDATA (3,14,15)
PETn0 SMB_DATA R265 *0_4
29 GND SMB_CLK 30 CLK_SCLK (3,14,15)
27 28 +1.5V
GND +1.5V +1.5V
(10) PCIE_RX6+ 25 26
PERp0 GND
(10) PCIE_RX6- 23 24 +WL_VDD
PERn0 +3.3Vaux
21 GND PERST# 22 PLTRST# (4,10,11,27,31,35)
19 20 RF_EN (35)
UIM_C4 W_DISABLE#
17 UIM_C8 GND 18
15 16 A_LFRAME#_R R547 *Short_4

GND UIM_VPP A_LAD3_R LPC_LFRAME# (9,35)
13 14 R549 *Short_4 C766 C728 C722
(10) CLK_PCH_SRC2 REFCLK+ UIM_RST LPC_LAD3 (9,35)
11 12 A_LAD2_R R553 *Short_4 1000p/50V_4 0.1u/10V_4 10u/6.3V_8
(10) CLK_PCH_SRC2# REFCLK- UIM_CLK LPC_LAD2 (9,35)
9 10 A_LAD1_R R557 *Short_4
GND UIM_DATA LPC_LAD1 (9,35)
7 8 A_LAD0_R R561 *Short_4
(10) CLKREQ_WLAN# CLKREQ# UIM_PWR LPC_LAD0 (9,35)
5 6 +1.5V
Reserved +1.5V C-test
3 4
GND
GND
WLAN_WAKE# Reserved GND
T112 1 WAKE# +3.3V 2 +WL_VDD
MINI-CARD 5.6H
53
54
(10) PCI_RST# R266 *Short_4 CL_DATA1_WLAN
R267 *Short_4 CL_CLK1_WLAN
(10) CLK_LPC_DEBUG
C
C-test
MINI-CARD 3G(MNC)Reserve for JV41-CP

+1.5V
+1.5V +3G_VDD
+3G_VDD H=7.0mm
1
CN16 C606
51 52 +3G_VDD R426 *3G@10K_4 C608 C611
Reserved +3.3V *3G@0.1u/10V_4 *3G@0.47u/10V_6 *3G@10u/6.3V_8
49 50 Active Low
2
Reserved GND
47 Reserved +1.5V 48
45 46 C3C R423 3G@0_4
T92 Reserved LED_WPAN# 3G_LED# (33)
43 44 R417 *3G@0_4
Reserved LED_WLAN# 3G_LED#_R R418 3G@0_4 R428 *3G@0_4 RF_LED#
41 Reserved LED_WWAN# 42 (3,10,16) ICH_SMBDATA 3
39 40
Reserved GND
37 38 USBP10+ (10)
Reserved USB_D+ +3G_VDD R422
35 36 USBP10- (10)
GND USB_D-
(10) PCIE_TX2+ 33 34
PETp0 GND 3G_SMDATA
(10) PCIE_TX2- 31 PETn0 SMB_DATA 32
29 30 3G_SMCLK
GND SMB_CLK C609 C618
27 28
GND +1.5V
(10) PCIE_RX2+ 25 PERp0 GND 26
23 24 3G@0.1u/10V_4 *3G@10u/6.3V_8
(10) PCIE_RX2- PERn0 +3.3Vaux
21 22 PLTRST#_3G R420 3G@0_4 PLTRST# C3C 3
GND PERST# (3,10,16) ICH_SMBCLK
19 20 R421 3G@0_4
UIM_C4 W_DISABLE# 3G_EN (35)
17 18
B UIM_C8 GND R416 *3G@0_4 RF_EN R425
15 16 UIM_VPP
GND UIM_VPP UIM_RST
(10) CLK_PCH_SRC1 13 14
REFCLK+ UIM_RST UIM_CLK
(10) CLK_PCH_SRC1# 11 12
REFCLK- UIM_CLK UIM_DATA L53 3G@0_8 100mil
9 10 +3V
GND UIM_DATA UIM_PWR
(10) CLKREQ_3G# 7 8
CLKREQ# UIM_PWR L52 *3G@0_8 +3G_VDD
5 Reserved +1.5V 6 +3VSUS
3 4
GND
GND
Reserved GND
1
T93 1 2
WAKE# +3.3V C613 C607 C614 C577 C612 C6
3G@MINI-CARD 7.0H 3G@10u/6.3V_8 3G@0.1u/10V_4 3G@0.1u/10V_4
53
54
2
3G@0.1u/10V_4 3G@0.47u/10V_6 3G
A:(10/17)FAE confirm:
3G module need +3VSUS and no need +1.5V and no need S
SIM CARD FFC connector(RFM) B-test
CN1
UIM_PWR 1 1
2
2
3
A R640 *3G@0_4 4 3
(10) USBP5+ 4
R641 *3G@0_4 5
(10) USBP5- 5
6
UIM_VPP 6
7 7
UIM_RST 8
UIM_CLK 8
9 11
UIM_DATA 9 11
10 12
10 12 Q
3G@SIM_CARD CON
P
Mini-Card/WL/3
5 4 3 2
1
+3G_VDD +3G_VDD
4
2
B-test R419
Q26 *3G@4.7K_4P2R
2
*3G@2N7002K
3
1
3 1 3G_SMDATA
R422 *3G@0_4
+3G_VDD
Q27
2
*3G@2N7002K
3 1 3G_SMCLK
B
R425 *3G@0_4
C610
_6 3G@10p/50V_4
ed SMBUS

PROJECT : ZQ1
r Rev
1A
WL/3G/SIM
0, 2010 Sheet 28 of 48
1
1 2 3 4
SATA HDD(HDD) SATA ODD (ODD)
CN21
23
GND23 CN17
GND1 1 GND14 14
2 SATA_TX0+ (9)
A RXP
RXN 3 SATA_TX0- (9) GND 1
4 2 SATA_TX1+ (9)
GND2 SATA_RX0-_C C411 0.01u/16V_4 A+
TXN 5 SATA_RX0- (9) A- 3 SATA_TX1- (9)
6 SATA_RX0+_C C407 0.01u/16V_4 4
TXP SATA_RX0+ (9) GND
7 5 SATA_RX1-_C C276 0.01u/16V_4
GND3 B- SATA_RX1+_C SATA_RX1- (9)
6 C274 0.01u/16V_4
B+ SATA_RX1+ (9)
7
GND
3.3V 8
9
3.3V SATA_DP
10 8 R142 1K_4 1.8A (MAX.)
3.3V DP +5V_ODD
11 9
GND 5V
GND 12 5V 10
13 11 C603 C602 C604 C605 C601
GND +5V_HDD MD
14 12
5V GND 0.01u/16V_4 0.01u/16V_4 *0.1u/10V_4 *0.1u/10V_4 *10u/6.3V_6
5V 15 GND 13
16
5V
GND 17 GND15 15
18
RSVD SATA_ODD
GND 19
12V 20
12V 21
22 1A (MAX.)
12V R227 *Short_8 +5V_HDD
+5V
B GND24 24
+
C3C C362 C367 C377 C387 C385
MAIN_SATA C354
100u/6.3V_3528 10u/6.3V_6 0.1u/10V_4 *0.1u/10V_4 0.01u/16V_4 0.01u/16V_4
HOLE(OTH) ODD POWER(ODD)

HOLE5 HOLE3 HOLE12 HOLE11 HOLE14 HOLE15
*HG-C315D118P2 *HG-C315D118P2 *H-C236D142P2 *H-C236D142P2 *H-C236D142P2 *H-C236D142P2
7 6 7 6
8 5 8 5
Q24
9 4 9 4
+5V AO6402A
+3VPCU
1
2
3
1
2
3
1
6
5 4
2
1
C 1
HOLE25 HOLE24 HOLE4 HOLE6 HOLE18 HOLE9 R138
*HG-C295D118P2 *HG-C315D118P2 *H-C197D122P2 *H-C197D122P2 *H-C197D122P2 *H-C197D122P2 100K_4 R141
3
7 6 7 6 2 1 MOD_EN_5V
+15V
8 5 8 5 100K_4
3
9 4 9 4
1
2
3
1
2
3
1
2
B-test
3
Q23
C3C DMN601K-7
HOLE13 HOLE26 HOLE23 HOLE2 HOLE7 HOLE16 HOLE21
1
*HG-C295D110P2 *HG-C315D118P2 *HG-C315D118P2 *H-C236D118P2 *H-C276D142P2 *H-C197D87P2 *H-C197D51P2 (35) EC_ODD_EN R137 *Short_4 ODD_EN 2
7 6 7 6 7 6
1
8 5 8 5 8 5 (9) PCH_ODD_EN R136 *0_4 Q22
9 4 9 4 9 4 DMN601K-7
R129
1
*100K_4
1
2
3
1
2
3
1
2
3
2
ADOGND
HOLE10 HOLE17
D *HG-C276D118P2 *HG-C315D118P2
7 6 7 6 HOLE1 HOLE22 HOLE20 HOLE19 HOLE8
*H-C95D95N *H-TC177BC217D142P2 *H-C177D79P2 *HG-C236D118P2 *H-C315D87P2
8
9
5
4
8
9
5
4 7 6
Connect to PCH(GPIO21) pin Y9
8 5 and EC pin28(GPIO53) Quanta
9 4
1
2
3
1
2
3
PROJECT
1
1
2
3

SATA-HDD/O
1 2 3 4
A
+5V_ODD
+
C615
3V_6 100u/6.3V_3528
+5V_ODD +5V
R429
*0_8 C
N_5V
1
01K-7
C259
0.1u/25V_6
2
nta Computer Inc.

CT : ZQ1
Rev
1A
D/ODD/HOLE
Sheet 29 of 48
5 4 3 2 1
HPR
Codec(ADO) HPL
LINE-OUT/SPDIFO(AMP) +3V_SPD
reverse R441
R560 *0_4 ADOGND +3V 1 3
MIC1-VREFO-L Q36 C774

ME2347
2
MIC1-VREFO-R LINEOUT_JD: 0.22u/6.3V_4
reverse R429 HP not insert->H
ADOGND
MIC1-VREFO-L
HP insert->L
R308 *0_4 ADOGND CN25
D3D 1
C764 10u/6.3V_6 ADOGND HP_JD 2
C750 HPL R315 75_4 HPL-1 L30 SBK160808T-121Y-N/400mA/120ohm_6 HPL_SYS 3

Place next to pin 27 HPR R319 75_4 HPR-1 L31 SBK160808T-121Y-N/400mA/120ohm_6 HPR_SYS 4
+
2.2u/6.3V_6 ADOGND 5
R327 R312 C468 C459
D 7 LED
C770 C769 *1K_4 *1K_4 2200p/50V_4 2200p/50V_4 SPDIF_OUT 8 Drive
C749 ADOGND +5VA 6 IC
+5VA 10u/6.3V_6 0.1u/10V_4
+
SPDIF_BLACK
2.2u/6.3V_6 ADOGND
Normal OPEN J
C743 C745 C787
10u/6.3V_6 0.1u/10V_4
36
35
34
33
32
31
30
29
28
27
26
25
U37 C783 +5VA HP_JD
0.1u/10V_4 10u/6.3V_6
CBN
HP-OUT-R
MIC1-VREFO-R
CBP
CPVEE
LDO-CAP
VREF
HP-OUT-L
MIC1-VREFO-L
MIC2-VREFO
AVSS1
AVDD1
LINEOUT_JD
1
ADOGND ADOGND
ANALOG
Place next to pin 38 R582 D22
3
Spilt by AGND 37 24 ADOGND +5VA Near CN25
AVSS2 LINE1-R 10K_4 *VPORT_6
Place next to pin 25
2
38 23
C3C AVDD2 LINE1-L LINE_JD# 2
+5V R535 *Short_6 +5VPVDD1 39 22 MIC1_R1 R585 Q17
PVDD1 MIC1-R
3
ADOGND
L_SPK+ 40 21 MIC1_L1 22K_4 2N7002K
C732 C729 C739 C744 SPK-L+ MIC1-L HPL_SYS
1
L_SPK- 41 20 HP_JD 2
SPK-L- MONO-OUT
3
10u/6.3V_6 0.1u/10V_4 10u/6.3V_6 0.1u/10V_4 Q16
GND_EARTH 42 19 R575 20K/F_4 EAPD_HP 2 Q46
PVSS1 (Vista Premium Version) JDREF ADOGND
2N7002K ADOGND *MMBT3904
43 18
1
PVSS2 Sense-B
Place next to pin 39 R_SPK- 44 17
SPK-R- MIC2-R Placement near Audio Codec ADOGND
R_SPK+ 45 16 ADOGND
SPK-R+ MIC2-L HPR_SYS
C3C Spilt by PGND
+5V R532 *Short_6 +5VPVDD2 46 15
PVDD2 LINE2-R
3
GPIO0/DMIC-DATA
EAPD# 47
GPIO1/DMIC-CLK
14 2 Q47
C731 C726 C738 C742 SPDIFO2/EAPD LINE2-L
Spilt by DGND *MMBT3904
SPDIF_OUT_R48 13 SENSEA R577 39.2K/F_4 LINEOUT_JD
SDATA-OUT
1
10u/6.3V_6 0.1u/10V_4 10u/6.3V_6 0.1u/10V_4 SPDIFO Sense A D3D
SDATA-IN
DVDD-IO
PCBEEP
RESET#
BIT-CLK
49 R576 20K/F_4 MIC1_JD
DVDD1
DVSS2
PGND
SYNC
ANALOG
PD#
ADOGND
C
Place next to pin 46 ALC271X apply for codec suggestion
1
10
11
12
PCBEEP dont coupling any signals if possible
DIGITAL 8/17 separate PCBEEP to Digital from Realtek suggestion
C3C 1.6Vrms
+3V R543 *Short_6 +AZA_VDD
PCBEEP C781 1u/10V_6 BEEP_1 R583 47K_4
SPKR (9)
C788 R574
C747 C751 4.7K_4 If either HDA device io power use +1.5V,
0.1u/10V_4 10u/6.3V_6 100p/50V_4 all device IO power change to +1.5V
Place next to pin 1

R565 *Short_6 +AZA_VDD
DMIC_DAT_R
DMIC_CLK_R C-test
C767 C768
PCH_AZ_CODEC_RST#
PCH_AZ_CODEC_RST# (9)
PD# 0.1u/10V_4 10u/6.3V_6
0V : Power down Class D SPK amplifer PCH_AZ_CODEC_SYNC (9)
3.3V : Power up Class D SPK amplifer
Close to codec ACZ_SDIN0_R R562 22_4 MIC1-VREFO-R
R552 DMIC_DAT_R
PCH_AZ_CODEC_SDIN0 (9)
Place next to pin 9 MIC(AMP) MIC1-VREFO-L
(25) DMIC_DAT PCH_AZ_CODEC_SDOUT (9)
SBK160808T-301Y-N/0.2A/300ohm_6
R559 DMIC_CLK_R R281 R276
(25) DMIC_CLK
SBK160808T-301Y-N/0.2A/300ohm_6 4.7K/F_4 4.7K/F_4
PCH_AZ_CODEC_BITCLK (9)
BLACK
C456 *22p/50V_4 1 CN24 7
C748 C760 MIC1_L1 C439 4.7u/6.3V_6 MIC1_L2 R287 1K/F_4 MIC1_L3 L27 MIC1_L 2
*150p/50V_4 *150p/50V_4 SBK160808T-121Y-N/400mA/120ohm_6 6
MIC1_R1 C412 4.7u/6.3V_6 MIC1_R2 R268 1K/F_4 MIC1_R3 L26 MIC1_R 3
SBK160808T-121Y-N/400mA/120ohm_6 4
MIC1_JD 8
5
JA6331-0230T3B-8H
C410 C444
470p/50V_4 470p/50V_4 Normal OPEN Jack
B SPDIF_OUT L51 SBY100505T-121Y-N/300mA/120ohm_4 SPDIF_OUT_R R345 *0_6 GND_EARTH don't coupling AGND and SPK signals Max. 100mVrms input for Mic-IN
R364 *0_6
R368 *0_6
R612 *0_6 GND_EARTH R282 0_6
C733 R628 *0_6 ADOGND ADOGND
*33p/50V_4 R257 *0_6 R284 *0_6 MIC1_JD
R610 *0_6 R278 *0_6
1
R317 0_6 D4
R299 *0_6
R587 *0_6 *VPORT_6 Near CN28
2
R258 *0_6
Power (ADO) R310 0_6
Tied at one point only under the
C795 *1000p/50V_4
L65 Place close to Codec C800 *1000p/50V_4 ALC269 or near the ALC269
Demodulation Filter ADOGND
DIGITAL ANALOG ADOGND
L50 PBY201209T-300Y-N/4A/30ohm_8 10/29 modify

+5V +5VA
C3D
U34 Reserve R568 for codec Internal Speaker(AMP)
3
IN OUT
4 Mute(ADO) C3C
+5VA
2 +AZA_VDD +5V
GND
1 5 R528 *29.4K/F_4
SHDN SET R653
*G923-330T1UF R566 R568 40mil for each signal
R530 + C736 C730 *10K_4
*10K/F_4 10K_4 *1K_4
10u/10V_3216 0.1u/10V_4 R_SPK+ R586 0_6 R_SPK+_1
C716 C719 PD# BAS316 D21 PCH_AZ_CODEC_RST# EAPD_HP R_SPK- R588 0_6 R_SPK-_1
+ R524 *0_4 L_SPK- R468 PBY160808T-221Y-N/2A/220ohm_6 L_SPK-_1
3
Q45 L_SPK+ R471 PBY160808T-221Y-N/2A/220ohm_6 L_SPK+_1

0.1u/10V_4 10u/10V_3216 *2N7002K
A
ADOGND *BAS316 D19 EAPD# 2 C3C C791 C793 C663 C670
*0.22u/25V_6 *0.22u/25V_6 68p/50V_6 68p/50V_6
ADOGND
1
BAS316 D20
AMP_MUTE# (35)
C730, C787 close U37 pin3 and L65
ADOGND
apply for codec suggestion Quanta

Vset =1.25V PROJECT
Vout =Vset[1+AR(1,2)/AR(2,GND)] Size Document Number
ALC271X
5 4 3 2 1
25
PEN Jack
CN25
LACK
7
B-8H 10/5 modify
N Jack B
C3C
CN12
2
1
Speak CN1
CN8
1
2
A
Speak CN2
anta Computer Inc.

JECT : ZQ1
Rev
1A
271X / AMP / SPK
Sheet 30 of 48
A B C D
Cardreader(MMC) 4 IN 1 CARD READER (MMC)

CN10
XD_RDY 1 20 MS_DATA1
XD_RE# XD-R/B MS-DATA1 MS_BS
2 XD-RE MS-BS 21
XD_CE# 3 22
XD_CLE XD-CE 4IN1-GND2 VCC_XD
4 23 VC
XD_ALE XD-CLE SD-VCC SD_CLK
5 XD-ALE SD-CLK 24
XD_WE# 6 25 SD_DAT0
XD_WP# XD-WE SD-DAT0 XD_D2
7 XD-WP XD-D2 26
XD_D0 8 27 XD_D3
4 XD_D1 XD-D0 XD-D3 DATA4
9 XD-D1 XD-D4 28
SD_DAT2 10 29 SD_DAT1
SD_DAT3 SD-DAT2 SD-DAT1 DATA5
11 30
SD_CMD SD-DAT3 XD-D5 DATA6
12 SD-CMD XD-D6 31
13 32 DATA7
4IN1-GND1 XD-D7
VCC_XD 14 MS-VCC XD-VCC 33
MS_SCLK 15 34 XD_CD#
MS_DATA3 MS-SCLK XD-CD-SW SD_WP
16 MS-DATA3 SD-WP-SW 35
MS_INS# 17 36 SD_CD#
MS_DATA2 MS-INS SD-CD-SW
18 MS-DATA2
MS_DATA0 19 MS-DATA0 VCC_XD
SHIELD1-GND 37
38
SHIELD2-GND R232
SHIELD3-GND 41
42 *5.1K_4
SHIELD4-GND
CONN_CARDREADER
C-test
Close to CN14
C-test +1.8V_VDD Main DFHD36MS012 4.7u CAP close
+3V_VDD T111T110
R550 *Short_4 XTALSEL C759 C765
Second DFHD38MS013
SD_DAT0
3 Clock input selection 0.1u/10V_4 0.1u/10V_4
XTALSEL
CRMD_N
DATA0 MS_DATA
'1' for 48MHz input [Default]
DATA1
DATA0
DATA7
DATA6
CTRL1
CTRL3
NBMD
'0' for 12MHz input XD_D0
SD_DAT1
DATA1 MS_DATA
48
47
46
45
44
43
42
41
40
39
38
37
U36
CTRL0, CRTL 1 trace length shorter , XD_D1
VDDHM
XTALSEL
CTRL1
CTRL3
DATA1
DATA0
DATA7
DATA6
TRIST
GND
VDD
NBMD
R572 *100K_4 +3V_VDD and surround with GND.
R571 *Short_4 SD_DAT2
(4,10,11,27,28,35) PLTRST#
C-test C776 *0.47u/6.3V_4 1 36 CTRL0 DATA2 MS_DATA
GPON7 CTRL0 DATA5
2 EXT48IN DATA5 35
3 34 CTRL2 XD_D2
C3C R581 330_4 RSTN CTRL2 GPI4
4 REXT GPI4 33
R546 *Short_6 +3V_VDD 5 32 DATA4 T106 SD_DAT3
+3V VD33P DATA4
6 31 DATA3
(10) USBP12+ DP DATA3
C762 7 AU6437-GBL 30 DATA2 DATA3 MS_DATA
(10) USBP12- DM DATA2
8 29 XD_WP#
4.7u/10V_6 C778 C777 XI VS33P XDWPN GPI2 XD_D3
9 28
XO XI GPI2 XD_CE# T107
10 XO XDCEN 27
*5p/50V_4 *5p/50V_4 11 26 EEPDATA
+1.8V_VDD VDD EEPDATA GPI1 T105
12
VDD GPI1
25
T108
Close to co
SDWPEN
AGND5V
EEPCLK
VDDHM
CF_V33
XDCDN
VCC33
CTRL4
R525 SD_
GND
VDD
V18
V33
2 SBK160808T-121Y-N/40
CTRL0 XD_
13
14
15
16
17
18
19
20
21
22
23
24
MS_
crystal trace width needs at least 10 mils.
pin13 output 20mils EEPCLK T109 B-test SD_
C773
C779 18p/50V_4 XI CAP close PIN11,12 CTRL1 XD_
4.7u/10V_6
R233 MS_SC
Y7 R573 SBK160808T-121Y-N/40
12MHz 270K_4 SD_
VCC_XD
*0_4 R544
C780 18p/50V_4 XO XD_CD# CTRL2 XD_
pin14 output 15mils CTRL4 SD write protect
1:decided by SDWP[Default] SD_
+1.8V_VDD
0:letting SD always
+3V_VDD CTRL3 XD_
+3V_VDD write-able
C755 C753 MS_
4.7u/10V_6 0.1u/10V_4 CTRL4 XD_
Quanta
PROJECT
AU6437 Ca
A B C D
E
VCC_XD
2 C395 C392
K_4 4.7u/10V_6 0.1u/10V_4
N14 pin 14 & pin23

lose to pin23
_DAT0
3
_DATA0
_D0
_DAT1
_DATA1
_D1
_DAT2
_DATA2
_D2
_DAT3
_DATA3
_D3
connector
SD_CLK
-N/400mA/120ohm_6 2
XD_ALE
C718
MS_BS *10p/50V_4
SD_WP
XD_CLE
MS_SCLK
-N/400mA/120ohm_6
SD_CMD
C391
XD_RDY *10p/50V_4
SD_CD#
XD_WE#
MS_INS#
XD_RE#
nta Computer Inc.

CT : ZQ1
Rev
1A
7 CardReader
Sheet 31 of 48
E
5 4 3 2
USB PORT(USB) USB BOARD CONN(USB)

+5V_S5
C711 L28
U33 2 1 USBP11-_R
USBPWR1 (10) USBP11- 2 1 USBP11+_R
1u/10V_6 2 8 3 4 CN11
IN1 OUT3 (10) USBP11+ 3 4
3 7 +3VPCU
D IN2 OUT2 DLW21HN900SQ2L/330mA/90ohm 20
OUT1 6 (25,35) LID591# 19
4 +5V_S5
(35) USBON# EN# 18
1 GND 17
OC# 5 USB_OC0# (10) 16
APL3510BXI-TRG 15
14
(10) USB_OC4_5# 13
L29
USBP9-_R (10) USB_OC1# USBON# 12
(10) USBP9- 2 1
2 1 USBP9+_R 11
(10) USBP9+ 3 3 4 4 10
USBP11-_R
B-test USBPWR1 DLW21HN900SQ2L/330mA/90ohm USBP11+_R 9
8
USBP9-_R 7
C688 + USBP9+_R 6
5
330u/6.3V_6.3X5.8 USBP3-_R 4
USBP3+_R 3
L32 2
USBP3-_R 1
CN20 (10) USBP3- 2 1
L24 2 1 USBP3+_R USB_
1 1 8 8 (10) USBP3+ 3 3 4 4
(10) USBP1- 4 3 USBP1-_R 2 7
4 3 USBP1+_R 2 7 DLW21HN900SQ2L/330mA/90ohm
(10) USBP1+ 1 1 2 2 3 3 6 6
C 4 4 5 5
DLW21HN900SQ2L/330mA/90ohm
USB_MB
1
1
RV1 RV2 F3A
F3A
*EGA10402V05AH_4
2
*EGA10402V05AH_4
BLUETOOTH CONN(BTM) TOUCHPAD BOARD CONN(TPD) TP SWITCH(UIF)

30mil
1 3 BT_POWER
+3V_S5
Q15
C361 R213 + C355 C366
2
B .33u/10V_6 47K_4 AO3413 pi-filter

2.2u/6.3V_6 1000p/50V_4 +5V +5V SW2
20mil
L42 +TPVDD LEFT# 1
PBY201209T-300Y-N/4A/30ohm_8 3
R212 4.7K_4 C619 C621
(35) BT_POWERON#
R147 R144 SWITCH_
10K_4 10K_4 *0.1u/10V_4 0.1u/10V_4 CN7
12
11 14 SW3
L21 SBK160808T-121Y-N/400mA/120ohm_6 TPDATA_R 10 13
B-test (35) TPDATA
L20 SBK160808T-121Y-N/400mA/120ohm_6 TPCLK_R 9 RIGHT# 1
(35) TPCLK
8 3
CN9 C269 C261 7
BT_POWER RIGHT# 6 SWITCH_
5 *0.01u/16V_4 5
R225 *Short_4 USBP4+_R 4 *0.01u/16V_4
(10) USBP4+ 4
R228 *Short_4 USBP4-_R 3
(10) USBP4- 3
BT_LED 2 7
T52 2
1 6 LEFT# 1
BT_CONN
C389 TP/B
*0.01u/16V_4
C3C
A
Quanta
PROJECT
eSATA/US
5 4 3 2
1
+5V_S5
C462
*2.2u/6.3V_6
10/29 modify
CN11
20 D
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
USB_CONN
B-test
B
2
2
4
5
TCH_1.5 6
2
4
5
TCH_1.5 6
nta Computer Inc.

CT : ZQ1
Rev
1A
/USB
Sheet 32 of 48
1
5 4 3 2
POWER BOARD CONN(UIF) B-test

LED(UIF)
+3V +3V_S5
+3V_S5 D3D Amber

C809 LED1
R369 806/F_4 4 2
(35) SUSLED#
1
*0.1u/10V_4
D
R365 56_4 3 1
(35) PWRLED#
+3VPCU +3V_S5
PWRLED# 2 LED_A/B
1
Q28
Blue
BSS84 R366 *1M_4 +3VPCU
3
1
R122 SUSLED# 2
*100K_4 D3D R362 *1M_4
Q29 R659 +3VPCU
2 *BSS84 +3V
(35) ACPRN 27_4
CN2 Amber
3
1 LED2
Q10 PWR_LED 2 R370 806/F_4 4 2
SUS_LED (35) BATLED1#
*BSS84 3
3
PIPE_LED 4 R361 56_4 3 1

(35) BATLED0#
D6 BAS316 5
(35) NBSWON#
6 LED_A/B
R660 453/F_4 7
(35) NUMLED#
R661 453/F_4
(35) CAPSLED# SATA_LED#_R R662 453/F_4
8
9
Blue RF_LED_EN#
10 13
D3D 11 14
C 12
+3V C3C
POWER/B R649 *Short_4
Amber 3
(28,35) RF_LED#
LED3
R642 *0_4 R371 806/F_4 4 2 R650
(35) RF_LED_EN#
R130 R367 3G@56_4 3 1
(28) 3G_LED#
5
10K/F_4 1
4 SATA_LED#_R LED_A/B
(9) SATA_ACT# 2
U12
Blue
3
*TC7SH08FU
R123 *Short_4 C-test
SW BOARD CONNECTOR(UIF)
B +3V
+3V 1 3 P_SAVE_LED
B-test
C4
Q40
2
BSS84 +3V *0.
(35) P_SAVE_LED#
+3V D3D CN3
1
R663 2.2K_4 2
(35) ODD_EJ 3 1 3
4
Q41 5 7
R643 BSS84 R651 6 8
2
100K_4 100K_4
SW/LED
+3V
(35) POWER_SAVE 3 1
Q42
A R644 BSS84 R652
2
100K_4 100K_4
Quanta
C-test
PROJECT
POWER BO
5 4 3 2
1
V_S5
VPCU
N#
Q39 +3V
2
BSS84
C
1
650 *0_4
3V B
C495
*0.1u/10V_4
nta Computer Inc.

CT : ZQ1
Rev
1A
BOARD/LED/SW DB
Sheet 33 of 48
1

PROJECT : ZY2 & ZY6
5 4 3 2
14" K/B(KBC) MY0

CN6 EE RETURN-PATH CAPACITORS(EMC) C471 *0.1u/16V
(35) MY0 1 +5V_S5
7 8 MX3 MY1 2
(35) MY1
5 6 MX2 MY2 3 C399 *0.01u/50V_6 C472 *0.01u/50V
(35) MY2 +3VPCU
3 4 MX1 MY3 4
(35) MY3
1 2 MX0 MY4 5 C600 *0.01u/50V_6 C724 *0.01u/50V
(35) MY4
CP6 *100p/50V_8P4C MY5 6
(35) MY5
7 8 MX7 MY6 7 RP3 10K_10P8R
(35) MY6
5 6 MX6 MY7 8 10 1 MX3 C473 *0.01u/50V_6 VIN VIN C513 1u/25V_6
(35) MY7
D 3 4 MX5 MY8 9 MX4 9 2 MX2
(35) MY8
1 2 MX4 MY9 10 MX5 8 3 MX1 +3V C677 *0.01u/50V_6 C819 0.1u/50V_
(35) MY9
CP4 *100p/50V_8P4C MY10 11 MX6 7 4 MX0
(35) MY10
7 8 MY0 MY11 12 MX7 6 5
(35) MY11
5 6 MY1 MY12 13 +5V_S5 C263 *0.01u/50V_6 VIN
(35) MY12
3 4 MY2 MY13 14 C805 *0.01u/50V
(35) MY13
1 2 MY3 MY14 15
(35) MY14
CP3 *100p/50V_8P4C MY15 16 +3V C643 *0.01u/50V_6 VIN
(35) MY15
7 8 MY4 MY16 17 +5V C804 *0.01u/50V
(35) MY16
5 6 MY5 MY17 18
(35) MY17
3 4 MY6 MX7 19
(35) MX7
1 2 MY7 MX6 20 +5V_S5 C798 *0.1u/10V_4 C761 *0.1u/16V
(35) MX6
CP2 *100p/50V_8P4C MX5 21
(35) MX5
7 8 MY8 MX4 22 C725 *0.01u/16V_4
(35) MX4
5 6 MY9 MX3 23
(35) MX3
3 4 MY10 MX2 24 27
(35) MX2
1 2 MY11 MX1 25 28
(35) MX1
CP1 *100p/50V_8P4C MX0 26 +3V C616 *0.1u/10V_4
(35) MX0
7 8 MY12
5 6 MY13 KB C735 *0.01u/16V_4
3 4 MY14
1 2 MY15
CP5 *100p/50V_8P4C
C C576 *100p/50V_4 MY16
C575 *100p/50V_4 MY17
STITCHING for LPC
VIN_SRC C344 *0.1u/25V_4
C349 *0.01u/25V_4
B-test
CPU FAN(THM)
+3V +3V +5V +3V +
R31 R44 R11

R27
10K_4 10K_4 10K_4
R26 10K_4
*10K_4
FAN_PW M_E
(35) FANSIG
2
3
2 Q3 1 3 FAN_PW M_CN
(10,11,35) SML1ALERT#
MMBT3904
Q4 30mil
1
MMBT3904
A
(35) CPUFAN#
Quanta C
PROJECT
KB/FAN/EE RE
Date: Tuesday, March 30, 2010 Sh
5 4 3 2
1
u/16V_6 +3V
1u/50V_6
1u/50V_6
5V_6
D
/50V_6
C-test
1u/50V_6 +1.05V
1u/50V_6 +3V
u/16V_6 +1.05V
+5V
+5V C810
*2.2u/6.3V_6
R386
_4 *Short_6 B-test
C3C
CN14
+5V_FAN
1
2
3
4
FAN CONN
A
a Computer Inc.
CT : ZQ1
Rev
1A
RETURN CAP
Sheet 34 of 48
1
5 4 3 2
EC(KBC) L43 PBY160808T-250Y-N/3A/25ohm_6 +A3VPCU I/O ADDRESS SETTING(KBC)

+3V
C672 C671
30mil
0.1u/10V_4 4.7u/10V_6
+3VPCU E775AGND
D11 C660 C653
R448 2.2_6 +3VPCU_EC 0.03A(30mils)
BAS316 4.7u/10V_6 0.1u/10V_4
C644 C673 C668 C652 C637 C649
115
102
19
46
76
88
4
4.7u/10V_6 0.1u/10V_4 *0.1u/10V_4 0.1u/10V_4 *0.1u/10V_4 0.1u/10V_4 U16
VCC1
VCC2
VCC3
VCC4
VCC5
AVCC
VDD
E775AGND C347 0.01u/50V_6 ICMNT B-test SHBM=0: Enable shared me
D
C669 0.01u/16V_4
(9,28) LPC_LFRAME# 3 97 TEMP_MBAT (45)
LFRAME GPIO90/AD0 WL_SW
(9,28) LPC_LAD0 126 98 T46
LAD0 GPIO91/AD1
(9,28) LPC_LAD1 127 99 SML1ALERT# (10,11,34)
LAD1 GPIO92/AD2
(9,28) LPC_LAD2 128
LAD2 A/D GPIO93/AD3
100 ICMNT (45)
3G_EN
(9,28) LPC_LAD3 1
LAD3 GPIO05
108 SHBM
CLK_PCI_775 2 96 R645 *0_4
(10) CLK_PCI_775 LCLK GPIO04 VGA_THERM# (22) B-test
(8) CLKRUN# 8
GPIO11/CLKRUN
1/13 Comfirm by vendor mail :
101 POWER_SAVE (33) Disabled ('1') if using FWH devic
R475 GPIO94/DA0
121 105
(11) SIO_A20GATE GPIO85/GA20 GPI95/DA1 Enabled ('0') if using SPI flash fo
D/A GPI96/DA2
106 T45
*22_4 122 107
(11) SIO_RCIN# KBRST/GPIO86 GPI97
(11) SIO_EXT_SCI# 29
ECSCI/GPIO54 LPC
64
C667
(25) EC_FPBACK# 6
GPIO24/LDRQ
GPIO01/TB2
GPIO03
95
ACIN (45)
NBSWON# (33)
SM BUS PU(KBC)
MBCLK
*10p/50V_4 93 R450
GPIO06/IOX_DOUT LID591# (25,32) MBDATA
T43 124 94 R445
GPIO10/LPCPD GPIO07 SUSB# (8)
119 MXM_SMCLK12 (22)
GPIO23/SCL3
(4,10,11,27,28,31) PLTRST# 7 109 ACPRN (33)
LREST GPIO30/CIRTX2
120 MXM_SMDATA12 (22)
GPIO31/SDA3 MXM_SMCLK12 R447
(32) USBON# 123 65 BATLED0# (33)
GPIO67/PWUREQ GPIO32/D_PWM MXM_SMDATA12 R451
66 BATLED1# (33)
GPIO33/H_PWM
(9) IRQ_SERIRQ 125 15 VRON (37)
SERIRQ GPIO36
16 SUSLED# (33)
GPIO40/F_PWM ACOFF
(11) SIO_EXT_SMI# 9 17 T24
GPIO65/SMI GPIO42/TCK
GPIO GPIO43/TMS
20
3G_SW AMP_MUTE# (30) 2ND_MBCLK
21 T23 R151
MX0 GPIO44/TDI 2ND_MBDATA R153
(34) MX0 54 22 CPUFAN# (34)
MX1 KBSIN0 GPIO45/E_PWM COLOR_ENG EC_ODD_EN R444
(34) MX1 55 23 T116
MX2 KBSIN1 GPIO46/CIRRXM/TRST B-test
(34) MX2 56 24 VIN_ON (45)
MX3 KBSIN2 GPO47/SCL4
C (34) MX3 57 25 D/C# (45)
MX4 KBSIN3 GPIO50/TDO
(34) MX4 58 26 S5_ON (36,46)
MX5 KBSIN4 GPIO51
(34) MX5 59 27 HDMI_HPD_EC# (26)
MX6 KBSIN5 GPIO52/CIRTX2/RDY
(34) MX6 60 28 EC_ODD_EN (29)
MX7 KBSIN6 GPIO53/SDA4
(34) MX7 61 91 DNBSWON# (8)
KBSIN7 GPIO81
110 T47
MY0 GPO82/TEST B-test
(34) MY0 53 112 RF_LED_EN# (33)
MY1 KBSOUT0/JENK GPO84/TRIST R646 *Short_4
(34) MY1 52 80 DCR_EN (25)
MY2 KBSOUT1/TCK GPIO41
(34) MY2 51
MY3 KBSOUT2/TMS C3C
(34) MY3 50
MY4 KBSOUT3/TDI ODDLED
(34) MY4 MY5
49
KBSOUT4/JEN0 KB GPIO56/TA1
31 T21
(34) MY5 48 117 SUSON (36,40)
MY6 KBSOUT5/TDO GPIO20/TA2/IOX_DIN
(34) MY6 47 63 FANSIG (34)
MY7 KBSOUT6/RDY GPIO14/TB1
(34) MY7 43
MY8 KBSOUT7
(34) MY8
MY9
42
KBSOUT8 TIMER GPIO15/A_PWM
32 CONTRAST (25)
(34) MY9 41 118 NUMLED# (33)
MY10 KBSOUT9/SDP_VIS GPIO21/B_PWM
(34) MY10 40 62 PWRLED# (33)
MY11 KBSOUT10/P80_CLK GPIO13/C_PWM
(34) MY11 39 81 CAPSLED# (33)
MY12 KBSOUT11/P80_DAT GPIO66/G_PWM
(34) MY12 38
MY13 KBSOUT12/GPIO64
37
(34) MY13
(34) MY14
MY14 36
KBSOUT13/GPIO63
KBSOUT14/GPIO62 GPIO77/SPI_DI
84 ODD_EJ (33)
SPI FLASH(KBC)
MY15 35 SPI 83
(34) MY15 KBSOUT15/GPIO61/XOR_OUT GPO76/SPI_DO/SHBM 3G_EN (28)
MY16 34 82 R647 *0_4
(34) MY16 GPIO60/KBSOUT16 GPIO75/SPI_SCK RF_LED# (28,33)
MY17 33 SPI_SDI_uR R476 22_4 SPI_SDI_uR_
(34) MY17 GPIO57/KBSOUT17 B-test
75 RSMRST#_uR R455 *Short_4 R470 100K_4 SPI_SDO_uR
GPIO72/IRRX1/SIN2 ICH_RSMRST# (8)
MBCLK 70 73
(45) MBCLK MBDATA GPIO17/SCL1 GPIO70/IRRX2_IRSL0 PWROK_EC_uR SUSC# (8) SPI_SCK_uR
69 74 R453 *Short_4
(45) MBDATA GPIO22/SDA1 GPIO71/IRTX/SOUT2 PWROK_EC (8)
2ND_MBCLK 67 SMB IR 113
(10) 2ND_MBCLK GPIO73/SCL2 GPIO87/CIRRXM/SIN_CR RF_EN (28)
2ND_MBDATA 68 14 CIRR_X2 R457 10K_4 SPI_CS0#_uR
(10) 2ND_MBDATA GPIO74/SDA2 GPIO34/CIRRXL T25 +3VPCU
114 HWPG
GPIO16/CIRTX
111 P_SAVE_LED# (33)
TPCLK GPO83/SOUT_CR/XORTR
(32) TPCLK 72
TPDATA GPIO37/PSCLK1
(32) TPDATA 71
GPIO35/PSDAT1
1/13 Comfirm by vendor mail :
PCH_ACIN 10 86 SPI_SDI_uR C-test
B (8) PCH_ACIN GPIO26/PSCLK2 F_SDI If the Southbridge enables 'Long Wait Abort' by
11 PS/2 87 SPI_SDO_uR_R R472 22_4 SPI_SDO_uR
(32) BT_POWERON# GPIO27PSDAT2 F_SDO SPI_CS0#_uR default, the flash device should be 50MHz (or faster)
(38,39,40,44) MAINON 12
GPIO25/PSCLK3 FIU F_CS0
90
SPI_SCK_uR_R SPI_SCK_uR
T28 13 92 R473 22_4
GPIO12/PSDAT3 F_SCK
(8) ICH_SUSCLK R466 *Short_4 E775_32KX1 77 30 ECDB_CLOCK T22
GPIO00/32KCLKIN GPIO55/CLKOUT/IOX_DIN
C3C
VCC_POR
85 VCC_POR# R467 47K/F_4 +3VPCU
HWPG(KBC)
VCORF
AGND
GND1
GND2
GND3
GND4
GND5
GND6
R458 *20M_6 E775_32KX2 79 104 VREF_uR R477 *Short_4 +A3VPCU R483 *100K_4
GPIO02 VREF +3V
R482 *100K_4
B-test R480 100K_4
+3VPCU
R464 NPCE781 R479 *100K_4
5
18
45
78
89
116
103
VCORF_uR 44
R481 *100K_4
Y3 *33K/F_4
SM BUS ARRANGEMENT TABLE R569 *100K_4
1 4 D14
(44) HWPG_1.8V
SM Bus 1 Battery
L44 D15
(39) HWPG_1.05V
PBY160808T-250Y-N/3A/25ohm_6
C665 *32.768KHz C666 C636 SM Bus 2 PCH (40) HWPG_VDDR
D12
*15p/50V_4 *15p/50V_4
1u/6.3V_4 D13
(36) SYS_HWPG
E775AGND SM Bus 3 EEPROM
D16
(43) HWPG_GFX
E775AGND D17
(38) HWPG_VTT
POWER-ON Switch(KBC) INTERNAL KEYBOARD STRIP

J3 *SHORT_ PAD
2 1
A
SW1
*SWITCH_1.5 MY0 R14
NBSWON# 1 2
3 4
2
5
D2 6
*VPORT_6
B-test
Q
1
PR
WP
5 4 3 2
1
C)
ed memory with host BIOS

D
R465 10K_4
ail :
device on LPC.
ash for both system BIOS and EC firmware
+3VPCU
450 10K_4
445 10K_4
B-test
+3V_D_EXT
447 10K_4
451 10K_4
+3V
151 10K_4
153 10K_4
444 10K_4
+3VPCU
U29
DI_uR_R 2 8
SO VDD
DO_uR 5 7 C664
SI HOLD
CK_uR 6 3 0.1u/10V_4
SCK WP
S0#_uR 1 4
CE VSS
W25X40BVSSIG
C-test
B
+3V
R469
10K_4
BAS316 HWPG
BAS316
R474 B-test
BAS316 *Short_4
BAS316
MPWROK (4)
BAS316
BAS316
RIP SET(KBC)
A
+3VPCU
R145 10K_4

PROJECT : ZQ1
Rev
1A
WPCE775C_0DG & FLASH
2010 Sheet 35 of 48
1
5 4 3 2
MAIND
MAIND (16,40,44)
C3C
PR126 SHORT_PAD_4 VL
(4,46) SYS_SHDN#
For acoustic no
For acoustic noise take out PD9 for PANA bat

VIN_SRC
1
D D3D C-test
PR137
39K/F_4 VL
2
PC95
2
C3C 3V5V_EN 4.7u/10V_8
PR138
PC179 PC180 PC88 PC220 PC221 C3C SHORT_PAD_4 PC222 PC223
1
2200p/50V_6 10u/25V_1206 *10u/25V_1206 PC219 1u/25V_6 0.1u/50V_6 PR260 0.1u/50V_6 1u/25V_6 PC182
*10u/25V_1206 PR128 PR127 SHORT_PAD_4 PC181 100u/25V
1
PC218 SHORT_PAD_4 SHORT_PAD_4 2200p/50V_4
B-test *10u/25V_1206 PR142 PC98 PR143
C-test 390K_4 PC99 1u/16V_6 *0_4
2
5V_EN
3V_EN
0.1u/50V_6
5
6
7
8
PC96
OCP:10A
2
0.01u/16V_4 PC97
0.1u/50V_6
1
OCP: 10A L(ripple current) REF 4
1
3V_DH PQ65
=(19-5)*5/(2.2u*0.4M*19)
8
7
6
5
Spec: 5.9A PR140 *0_6 AO4468
~4.18A PR139
+5VPCU 150K_4
8
7
6
5
4
3
2
1
Iocp=10-(4.18/2)=7.91A 4 5V_DH
PL16
REF
LDOREFIN
VIN
NC
VCC
TON
LDO
ONLDO
Vth=7.91A*14.2mOhm=112.322mV
3
2
1
B-test B-test 2.2uH
R(Ilim)=(112.322mV*10)/5uA PQ63
AO4468 PR136 3V_LX
~220K
5
6
7
8
1
B-test +5VPCU 9 32 REFIN2 182K/F_6
PL15 BYP REFIN2 PR255
10 31 1 2
1
2
3
2.2uH OUT1 ILIM2
C 11 30 *2.2_6
5V_LX FB1 PU7 OUT2 SKIP
1 2 12 29 4
PR131 200K/F_6 DDPWRGD_R 13 ILIM1 RT8206B SKIP# DDPWRGD_R
28
2
PGOOD1 PGOOD2
1
8
7
6
5
B-test 5V_EN 14 27 3V_EN
PR135 PR250 EN1 EN2
15 26
*0_4 *2.2_6 DH1 DH2 PC184
16 LX1 LX2 25
+ 4 5V_DL 37 *2200p/50V_6
PC194 PAD
36
2
3
2
1
PAD
PGND
PVCC
PC186 PQ66
BST1
BST2
GND
PAD
PAD
PAD
DL1
DL2
0.1u/50V_6 PC94 PC92 AO4710
NC
PC183 0.1u/50V_6 0.1u/50V_6 1 2
PR133 *2200p/50V_6 PQ64 PR122 PR257 *0_4
35
34
33
17
18
19
20
21
22
23
24
SHORT_PAD_4 AO4710 PR125 1/F_6 1 2
1
2
3
1/F_6 1 2 PR132 SHORT_PAD_4

C3C 1 2 3V_DL
PC189 PR124 VL PR259 SKIP PR256 *0_6 REF C3C

*10u/25V_1206 330u/6.3V_7343 *0_6 SHORT_PAD_6 PR144
PC90 *0_6
2 0.1u/50V_6 PC93
PD7 1u/16V_6
1PS302 3 C3C
+5VPCU 1 3 +5V_GPU
OCP:8A PR130
1 SHORT_PAD_6
PQ42 Spec: 0.75A PR123 L(ripple current) 0 ohm change to shot pad 2/12 09
PR211 SW@AO3413 SHORT_PAD_6
=(19-3.3)*3.3/(2.2u*0.5M*19)
2
PC87 2
+5V SW@10K_4 0.1u/50V_6 PD8
3
~2.48A
1PS302
B
PC91 Iocp=8-(2.48/2)=6.67A
1 0.1u/50V_6
PR206 Vth=6.67A*15mOhm=94.714mV
PR117
3
R(Ilim)=(94.714mV*10)/5uA
SW@10K_4 +15V_ALWP DDPWRGD_R
+15V ~191K
dGPU_5V_EN 2 PR254 SH
22_8 PC89
3
PQ45 0.1u/50V_6
SW@DMN601K-7
+5VPCU
1
(11) dGPU_PWR_EN# 2
PQ46
SW@DMN601K-7
1
5
6
7
8
VIN_SRC +1.5V_SUS +SMDDR_VREF +15V
MAIND 4
VIN_SRC +3V_S5 +5V_S5 +15V +5VPCU +3VPCU
PR205 PR212 PR110 PR213 +3VPCU PQ71

1M_6 22_8 22_8 *3G@1M_6 AO4496
PR118 PR148 PR149 PR252
3
3
1M_6 22_8 22_8 1M_6
3
2
1
5
6
7
8
SUSD
S5D 2 2 3.29A
3
A S5D 3
3
4 +5V
3
PQ20 2 PQ70 1.5A

(35,40) SUSON
3
AO3404 2 *3G@AO3404
+3VSUS
1
1
2 PQ73 2 2 PC192
(35,46) S5_ON
2 AO4496 PR210
+3V_S5
1
2 2 PC206 PQ48 1M_6 *3G@2.2n/50V_4

PR119 0.5A DTC144EU PQ50 PQ15 PQ49 Quanta
1
3
2
1
PQ51 1M_6 Spec: 0.63A DMN601K-7 DMN601K-7

1
DTC144EU Rating: 5.8A *3G@DMN601K-7

PROJEC
1
PQ22 PQ23 PQ68 2.2n/50V_4 Spec: 1.88A

1
DMN601K-7 DMN601K-7 DMN601K-7 Size Document Number

+5V_S5
SYSTEM 5V/3V (R
5 4 3 2
1
tic noise
B-test
VIN_SRC D
PC182 PC225
u/25V_6X5.8 *10u/25V_1206
PC224
*10u/25V_1206
OCP : 8A
+3VPCU
5.3A B-test
PR134 +
SHORT_PAD_6 PC190
330u/6.3V_7343
C3C B-test
PC187
0.1u/50V_6
144
6
SYS_HWPG (35)
4 SHORT_PAD_4
C3C
+3VPCU
5
6
7
8
MAIND 4
71
4496 PQ21
AO4496
3
2
1
.29A
3.58A A
+5V
+3V
anta Computer Inc.

JECT : ZQ1
Rev
1A
V (RT8206)
Sheet 36 of 48
1
5 4 3 2 1
[PWM]
VR_PWRGD_CK505# (3) For acoustic noise VIN
VID 1.2875V
DELAY_VR_PWRGOOD (4,8)
1
+3VPCU PR49 *0_4 H_VID0 B-test
+
PC145 PC75 PC74 PC146
PR61 *0_4 H_VID1 2200p/50V_6 4.7u/25V_0805 4.7u/25V_0805 100u/25V_6X7.7
2
PQ54 B-test
5
AOL1448
PR60 *0_4 H_VID2 Spec: 36A
8/4 EMI request Rating: 25A*2
62882_DH1 4
PR59 *0_4 H_VID3
D
1
2
3
+VCC_CORE
PR48 *0_4 H_VID4 VIN +3V
+3VPCU
PL12 0.36uH
62882_LX1 1 2
PR58 *0_4 H_VID5 C3C
PR195 PQ52 PQ53 B-test
4
5
5
SHORT_PAD_6 AOL1718 AOL1718 PR214
PR47 *0_4 H_VID6 + PC76
PR56 PR50 *2.2/F_6
+5V_S5 1.91K/F_4 1.91K/F_4 4 4 330u/2V_7343
PC66
1
2
3
1
2
3
PR196 0.22u/25V_6 5/12 Change pr144 from 10K to 1.91K PC144
C3C 10_6 *1000p/50V_6
PR185 SHORT_PAD_8
PR106 PR107
16
17
40
1
PU5 SHORT_PAD_4 SHORT_PAD_4
CLK_EN#
VDD
VIN
PGOOD
PC65
1u/6.3V_4 C3C
41
+1.1V_VTT PAD
20
7/16 modify UGATE1 PR90 10K/F_4
19 1 2
PR188 BOOT1
*499/F_4 PSI# PR67 10K/F_4 2 PR92 VSUM+ PR89 3.65K/F_4
(6) H_PSI# PSI# 2.2_6 PC60
PR187 147K/F_6 3 0.22u/25V_6
RBIAS VSUM- PR192 1/F_4
21
PHASE1
(4) H_PROCHOT# 4
VR_TT# 62882_DL1A
23
PR113 PR190 LGATE1a PR191 10K/F_4
C Close to Phase 1 Inductor *470K_4 NTC *4.02K/F_4
5 For acoustic noise VIN
PC49 NTC
*0.01u/16V_4 24 62882_DL1B
1
LGATE1b B-test
1 2
22 +
VSSP1 PC73 PC71 PC72 PC143
11 62882_ISEN1 2200p/50V_6 4.7u/25V_0805 4.7u/25V_0805 100u/25V_6X7.7
2
H_VID0 ISEN1
(6) H_VID0 31
VID0 B-test
1
H_VID1 32
(6) H_VID1 VID1 PC59 PQ38 8/4 EMI request
5
H_VID2 33 0.22u/10V_4 AOL1448
2
(6) H_VID2 VID2 VSUM-
H_VID3 34 8/10 modify
(6) H_VID3 VID3 C3C 62882_DH2 4
H_VID4 35 25 PR70 SHORT_PAD_4 +5V_S5
(6) H_VID4 VID4 VCCP
ISL62882
1
2
3
H_VID5 36 PC55 1u/6.3V_4
(6) H_VID5 VID5 +VCC_CORE
1 2
H_VID6 37
(6) H_VID6 VID6 PC56 1u/6.3V_4 PL11 0.36uH
VR_ON 38 1 2 62882_LX2 1 2
(35) VRON VR_ON PQ44 PQ43
5
DPRSLPVR 39 29 AOL1718 AOL1718 B-test
4
(6) H_DPRSLPVR
2
DPRSLPVR UGATE2
PR51 30 1 2 PR209
PR57 499/F_4 BOOT2 62882_DL2 + PC61
4 4
100K/F_4 PR65 *2.2/F_6
2.2_6 PC48 330u/2V_7343
1
1
2
3
1
2
3
8 0.22u/25V_6
FB
28
PHASE2 PR78 PR79
PR189 PC136 26
*10K/F_4 22p/50V_4 LGATE2 PC142 SHORT_PAD_4 SHORT_PAD_4
9 27 *1000p/50V_6
FB2 VSSP2
B
PR69 10 62882_ISEN2 C3C
412K/F_4 PC50 ISEN2
2 1
1
150p/50V_4 7 PC57
COMP 0.22u/10V_4
2
VSUM-
8/10 modify
PC54
10p/50V_4 PR74 6
8.06K/F_4 VW
18 I_MON (6)
IMON
PR76 10K/F_4
1
PR97 PC70
PC53 8.25K/F_4 0.22u/10V_4
1000p/50V_4 VSUM+ PR75 3.65K/F_4
2
5/12 Change pr24 rom 2.87K to 2.8K

ISUM+
ISUM-
VSEN
VSSSENSE
RTN
PR91 VSUM- PR87 1/F_4
5/12 Change pc92 rom 0.33u_4 to 0.22u_6

12
13
14
15
2.8K/F_4 B-test 5/12 stuff pc26 0.068u_6 PR193 10K/F_4
PC141 PC140
PR96 PC69 0.22u/10V_6 0.068u/25V_6
562/F_4 390p/50V_4 VSUM+
1
+VCC_CORE 1 2 PR197 PR98

PR201 *27.4_4 82.5/F_4 2.61K/F_4
2
C3C PC67
PC137 PR94
PR200 SHORT_PAD_4 330p/50V_4 11K/F_4
(6) VCCSENSE
Parallel PC62 PC138 PR111
2700p/50V_4
2
A PR199 SHORT_PAD_4 330p/50V_4 0.01u/16V_4 C3C 10K _6_NTC Panasonic

(6) VSSSENSE
PC68
PR202 ERT-J1VR103J
1
1 2 1000p/50V_4 SHORT_PAD_4
PR198 *27.4_4
VSUM-
5/12 Change pr34 rom 1K to 1.24K
PR93
1.24K/F_4 PC139
0.1u/10V_4 Close to Phase 1 Inductor
Quanta Computer I
PC63 PR95 Load Line setting to 2mV/A
*1000p/50V_4 *100/F_4
PROJECT : ZQ1
5/12 un-stuff PC76,PR140 CPU Core ( ISL62882)
Date: Tuesday, March 30, 2010 Sheet 37 of
5 4 3 2 1
D
er Inc.
Rev
1A
of 48
5 4 3 2
[PWM] L68 *S
VTT_VIN L69 *S
+5V_S5
C3C
PR40 PD6
10_6 RB500V-40
5
D PR52
2.2/F_6
1
PR35
1M/F_6 C3C PC27 4
4.7u/6.3V_6
2
C3C C-test PR39 PC133 PC230 PC39
1
2
3
SHORT_PAD_6 PQ36 2200p/50V_4 0.1u/50V_6 10u/25V_1206
PR36 PU3 AOL1448
SHORT_PAD_6 UP6111AQDD PC32
15 13 0.1u/50V_6
(35,39,40,44) MAINON EN/DEM BOOT PL10 B-test
16 12 UGATE-VTT 2.2uH
PC30 TON UGATE
*0.1u/50V_6 1 11 PHASE-VTT
VOUT PHASE
2 10 PR43 2.4K/F_6 B-test
VDD OC
5
2.2uH
3 9 PC40 0.1u/50V_6 PL9
FB VDDP + +
4 8 LGATE-VTT 4 PR186
(35) HW PG_VTT PGOOD LGATE *4.7_6
6 7 PQ37 PC45
1
2
3
C GND PGND AOL1718 330u/2V_7343
5 17
NC TPAD PC135
14 *680p/50V_6
NC
1
PC37 PC52
330u/2V_7343 0.1u/50V_6
PC34 PC29 PC47
2
1u/16V_6 *1000p/50V_6 10u/10V_8
VOUT=(1+R1/R2)*0.75
PR42 PC134
R1 4.02K/F_6 *33p/50V_6
PR183 VTT_FB
SHORT_PAD_6
B C3C
PR44
R2 10K/F_6
AO1718 Rdson=3~4.3mOhm
TON=3.85p*RTON*Vout/(Vin-0.5)
L(ripple current)
=(19-1.05)*1.05/(1u*272k*19)
Frequency=Vout/(Vin*TON)
~3.64A
TON=3.85p*1M*1/(Vin-0.5) 4.3m*18=RILIM*20uA
RILIM=3.87K --- 3.92K
Frequency=1/(0.0036767)=272K
Quanta C
PROJECT
+VTT (UP6111A)
Date: Tuesday, March 30, 2010 Sh
5 4 3 2
1
*Short_8
*Short_8
VIN
OCP: 18A
1.05V/13.5A
B-test
+1.1V_VTT
2
0V_6
a Computer Inc.
CT : ZQ1
Rev
1A
Sheet 38 of 48
1
5 4 3 2
+5V_S5
PR270 PD11
D
10/F_6 RB500V-40
5
6
7
8
C3C
1
PR272
PR265 2.2/F_6 PC212 4
1M_6 4.7u/6.3V_6 PQ72
2
C3C C-test PR267 AO4468 PC202 PC201
SHORT_PAD_6 2200p/50V_4 10u/25V_120
PR266 PU13
SHORT_PAD_6 UP6111AQDD PC207
15 13 0.1u/50V_6
(35,38,40,44) MAINON
3
2
1
EN/DEM BOOT
16 12 UGATE-1.05V PL17
PC204 TON UGATE 2.2uH
*0.1u/50V_6 1 11 PHASE-1.05V
VOUT PHASE
2 10 PR269 3.9K/F_6
VDD OC
5
6
7
8
B-test
3 9 PC213 0.1u/50V_6
FB VDDP
C
4 8 LGATE-1.05V 4 PR268 + PC210
(35) HW PG_1.05V PGOOD LGATE *4.7_6
6 7
Rds*OCP=RILIM*20uA
GND PGND
5 NC TPAD 17
PQ74 PC211
14 AO4710 *680p/50V_6
3
2
1
NC
1
PC196
*10u/10V_8
PC208 PC203 330u/2V_7343 PC195
2
1u/16V_6 *1000p/50V_6 0.1u/50V_6
B
PR151 PC100
R1 4.02K/F_6 33p/50V_6
1.05V_FB
VOUT=(1+R1/R2)*0.75
PR150
10K/F_6
R2 PR271
SHORT_PAD_6
C3C
TON=3.85p*RTON*Vout/(Vin-0.5)
AO4710 Rdson=11.7~14.2mOhm
Frequency=Vout/(Vin*TON) L(ripple current)
A =(19-1.05)*1.05/(1u*272k*19)
TON=3.85p*1M*1/(Vin-0.5) ~3.646A Quanta
Frequency=1/(0.0036767)=272K 14.2m*10=RILIM*20uA PROJECT
RILIM=7.1K--- 7.15K
VCCP 1.05V(UP6111
Date: Tuesday, March 30, 2010 S
5 4 3 2
1
B-test
VIN
1 OCP: 10A
_1206
1.05V/5.3A
B-test
+1.05V
ta Computer Inc.
CT : ZQ1
Rev
1A
111A)
Sheet 39 of 48
1
5 4 3 2 1
[PWM]
D
PC85
Spec: 0.3A 10u/10V_8
Rating: 2A
C3C PR114 PC83

SHORT_PAD_6 0.1u/50V_6
For acoustic noise
+0.75V_DDR_VTT
8207_DH
PC82 PC84
2A 10u/10V_8 10u/10V_8 8207_LX
5
8207_DL 4.7u/25V_0805
PC86 PC169
4.7u/25V_0805
4
B-test
PC171
25
24
23
22
21
20
19
1
2
3
PQ59 2200p/50V_6
AOL1448 PL14
LL
DRVL
GND
VLDOIN
DRVH
VTT
VBST
1.5uH
1 18
VTTGND PGND
2 17
VTTSNS CS_GND
5
B-test
3 RT8207A 16
GND PU6 CS +5V_S5 PR229
Spec: 0.38A PR109 4 *4.7_6 + +
C Rating: 0.003A +1.5V_SUS 4 15 4.99K/F_6 PC155 PC167
MODE V5IN PR108 PQ58 330u/2V_7343 330u/2V_7343
1
2
3
5.1/F_6 AOL1718
+SMDDR_VREF 5 14
VTTREF V5FILT
1
PC80 PC163
0.003A
VDDQSNS
VDDQSET
PC79 +5V_S5 6 13 1u/6.3V_4 PC81 *680p/50V_6 PC149
2
0.033u/50V_6 COMP PGOOD 1u/6.3V_4 10u/10V_8
2
NC
NC
S3
S5
FOR DDR III

7
10
11
12
HWPG_VDDR (35)
AO1818 Rdson=3.8~4.6m
PR103 (For RT8207A 400KHZ )
C3C 620K/F_4
VIN OCP=12.21+0.5A
S5_1.8V PR102
L(ripple current)
SHORT_PAD_6SUSON (35,36) =(19-1.5)*1.5/(2.2u*4
S3_1.8V PR99 SHORT_PAD_6
MAINON (35,38,39,44)
PR100 *0/F_6
PWRGD_1.5VCPU (16) Add it for S3 leakage circuit ~1.57A
C3C PR101
*0/F_6 +5V_S5
4.6m*12=RILIM*10uA
PR112
RILIM=5.62K
SHORT_PAD_6
PC78 PR104
(10u*PR35)/Rdson+Delt
*33p/50V_6 10K/F_4
Vout = (PR150/PR149) X 0.75 + 0.75
PR105 +1.5V_SUS
10K/F_4 PC77
*0.033u/50V_6
B-test
3
MAIND 2
(16,36,44) MAIND
+1.5V_SUS
PQ60
AO3404
1
VIN_SRC +1.5V_GPU +15V
PR203 PR208 PR194

5
6
7
8
SW@1M/F_6 SW@22_8 SW@1M/F_6
4 0.3
PQ41
3
SW@AO4468
3
A
2 2
(44) PG_1.5V_EN
2
3
2
1
1
ZY9B solution PQ40 Spec: 7.5A

1
PR207 SW@DTC144EUA PQ47 Rating: 10A

1
*SW@100K_4
1
PR204 SW@DMN601K-7 PQ39 PC64

SW@2.2n/50V_4
+1.5V_GPU
Quanta C
2
SW@1M/F_6 SW@DMN601K-7
7.5A PROJECT :
DDR III 1.5V(TPS51116)
Date: Tuesday, March 30, 2010 Shee
5 4 3 2 1
1
36
D
VIN
0805 B-test 14.5A
12A
+1.5V_SUS
.6mOhm
u*400k*19)
elta_I/2=Iocp
US
PQ60
3404
+1.5V
0.38A
a Computer Inc.
T : ZQ1
Rev
1A
16)
Sheet 40 of 48
1
1 2 3 4
+5V_GPU
C-test
PR155
+3V_D_EXT *SW @0_4
PR158
5
SW @200K/F_4
PC8 SW @1u/10V_6 2 7 8792TON
VDD TON PQ27
A
PR6 5 8792DH 4 SW @AOL1448
SW @100K_4 PC1 SW @1u/10V_6 8792VCC DH PC117
13 VCC SW @2200p/50V_4
1
2
3
6 8792BST
8792PGD BST PR20 PC13
(44) PG_GPUIO_EN 14 PGOOD SW @1_6 SW @0.22u/25V_6 PL7
8792EN 1 PU1 SW @0.36
(11,20) dGPU_VRON EN 8792LX
LX 4
PR4 SW @MAX8792ETD+T
*SW @0_4 PC3 8792SKIP# 12
SKIP# 8792DL
DL 3
5
+3V_D_EXT SW @0.1u/10V_4 PR156 *SW @0_4
8792REFIN 10 PR172
PR154 REFIN SW @1_8
FB 8
B-test SW @SHORT_PAD_4 PR153 4 4
REF-2V
C3C SW @100K_4 8792REF 11 9 8792ILIM
1
2
3
1
2
3
REF ILIM
PC127
EP
SW @1000p/50V_4
PR9
15
SW @44.2K/F_4
PR157 C3C
SW @62K/F_4 PR152 PC10
SW @SHORT_PAD_6 *SW @4700P/25V_4 PQ25 PQ26 PC
B-test SW @AOL1718 SW @AOL1718 SW @
Place near GND pin15
PR1 PC7
3
B SW @470K/F_4 SW @1000P/50V_4
PR17
SW @100K_4
2 PQ1
(18) VID1 SW @2N7002E Frequency(PR220=200K) 300K
PR2
SW @100K_4 PR14
1
SW @49.9K/F_4
PR9 = 44.2K
B-test
AMD Madison VID Table PR14 = 49.9K
PC14 PR1 = 470K
SW @0.01u/16V_4 GPU_VID1 (GPIO15) GPU_VID2 (GPIO20) +VGPU_CORE PR19 = 220K
B-test
0 0 1.05V
PR19
1 0 1.0V
3
SW @220K/F_4 0 1 0.95V
PQ2
1 1 0.9V
(18) VID2 2
SW @2N7002E
PR3 PR9 = 39.2K CS339

SW @100K_4
AMD Park VID Table PR14 = 49.9K
1
PR1 = 332K CS433

GPU_VID1 (GPIO15) GPU_VID2 (GPIO20) +VGPU_CORE PR19 = 130K CS413
C 0 0 1.12V
PC2
SW @0.01u/16V_4 1 0 1.05V
0 1 0.95V
1 1 0.9V
8792EN 2
PQ3
SW @DTC14
Size
Date:
1 2 3 4
5
VIN
PC105 B-test
SW @10u/25V_1206
22.5A
OCP=33A
PC113
SW @10u/25V_1206 +VGPU_IO
_4 PC101 B-test
SW @10u/25V_1206
+VGPU_CORE
B-test
@0.36uH
+ +
PC18
SW @330u/2V
0V_4
PC19 PC17
SW @0.1u/50V_6 SW @330u/2V B-test
S33922FB15
S43322FB15
S41302FB00
C
VIN_SRC +VGPU_CORE
PR7 PR21
SW @1M_6 SW @22_8
3
3
PR8 PQ4
SW @1M_6 SW @2N7002E
1
DTC144EU

PROJECT : ZQ1
ze Document Number Rev
1A
GPU CORE(MAX8792)
ate: Tuesday, March 30, 2010 Sheet 41 of 48
5
A B C D E F G
Int_VGA [PWM]
(6) GFX_VID0
(6) GFX_VID1 +1.1V_VTT +1.1V_VTT

(6) GFX_VID2
(6) GFX_VID3
1 PR243 PR242 PR241 PR240 PR239 PR238 PR237

(6) GFX_VID4
*0_6 *0_6 *0_6 *0_6 *0_6 *0_6 *0_6
(6) GFX_VID5
(6) GFX_VID6
GFX_VID6 GFX_VID5 GFX_VID4 GFX_VID3 GFX_VID2 GFX_VID1 GFX_VID0
PC176
*0.01u/25V_4
62881_GND 2 1
PR247 SHORT_PAD_4
(6) GFX_ON
C3C
PR236 SHORT_PAD_4
(6) GFX_DPRSLPVR
B-test
PR217 *short VIN
62881_GND
62881DPRSLPVR
62881_GND
62881VR_ON
1
GFX_VID6
GFX_VID5
GFX_VID4
GFX_VID3
GFX_VID2
PC148 PC150 PC151
10u/25V_1206 10u/25V_1206 PC147
2
0.1u/50V_6 2.2n/50V_4
B-test
30
31
29
28
27
26
25
24
23
22
5
GND
GND
GND
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
GFX_VID1
GFX_VID0
C3C
1
CLK_EN#
2 4
PR234 SHORT_PAD_4 62881PGOOD 2 21 +5V_S5
(35) HWPG_GFX PGOOD VID1
1
2
3
PQ55
PR233 47K/F_4 62881RBIAS 3 20 AOL1448
62881_GND RBIAS VID0
PR231
*150K/F_4 PC175 0616 change to 0.56uH
PR232 8.06K/F_4 62881VW 4 19 1 2
62881_GND VW VCCP
PU11
PC174 4.7u/6.3V_6
22
ISL62881HRZ-T 18 62881LGATE
1000p/50V_4 62881COMP 5 LGATE PL13 +VGF
COMP 0.56uH
PR230 PC173 0616 change to 22pF 17
820K/F_4 22p/50V_4 VSSP
62881FB 6 FB
16 62881PHASE
PC170 0616 change to 8.87k PHASE
100p/50V_4 PR227
5
8.87K/F_4 15 62881UGATE
62881VSEN UGATE PR245 + +
7
VSEN PR235 3.65K/F_4
ISUM+
ISUM-
BOOT
IMON *4.7_6
4 4
VDD
RTN
VIN
PR228 PC165
PR248 PR246
1
2
3
1
2
3
B-test PQ57 PQ56 2.61K/F_4 10K _6_NTC
8
10
62881VDD 11
12
13
14
17.8K/F_4 150p/25V_4 PC158 PR226 PC172 AOL1718 AOL1718
PC166 330p/50V_4 62881BOOT 1 2 PC177
62881ISUM+
62881ISUM-
62881VIN
0616 change to 150pF 330p/50V_4 1_6 *680p/50V_6 PC178 PC168 PC157

62881RTN 0.22u/25V_6 PR244 560u/2.5V_6X5.7 560u/2.5V_6X5.7 10u/6.3V_8
GFX_IMON
GFX_IMON (6)
PC164 11K/F_4
2
62881_GND PR222
1000p/50V_4 *10K/F_4 PC160
*0.22u/10V_4
1
PC152 PC154
3 VSS_AXG_SENSE 0.15u/10V_4 0.1u/10V_4
62881_GND C3C
PR223 VIN
SHORT_PAD_4
PC153 62881_GND
PC159 47n/10V_4
0.22u/25V_6
B-test
62881_GND
+5V_S5 0616 change to 2.49k
PR218 PC156
*180p/50V_4
PR221
PC161 10_6 2.49K/F_4
1u/6.3V_4
PR225
*100/F_4
62881_GND
PR224 PC162
2 1 0616 un-mount
82.5/F_4 0.01u/25V_4
Parallel
PR215 10/F_4
PR219 SHORT_PAD_4
VSS_AXG_SENSE (6)
4
C3C PR216 10/F_4
PR220 SHORT_PAD_4
VCC_AXG_SENSE (6)
Size Document Numb

1.Level 1 Environment-related Substances Should NEVER be Used. +VGFX_A
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners. Date: Tuesday, March 3
A B C D E F G
H
Spec: 16.5A
Rating: 25A
22A
+VGFX_AXG
DRC=2.7~3mOhm/2
Load Line=7mV/A
3m*6.168=0.925m
0.925m/2.49K=371p
371p*2*8.87K=6.58m
OCP
PC157 20u/2*2.42K=24.2m
u/6.3V_8
24.2m/0.6168=36.64m
36.64m/3m=12.21A

PROJECT : ZQ1
nt Number Rev
1A
FX_AXG (ISL62881)
H
5 4 3 2
+5VPCU change footprint 1.76A Spec: 1.32A

B-test Rating: 6A
+1.8V
PC188
PC191 0.1u/25V_4 C-test
10u/10V_8
PU12 HPA00835RTER
16 VIN PH 10
1 11 PL18
VIN PH 1uH/11A_7X7X3
D PR261 B-test
2 12
SHORT_PAD_6 VIN PH
MAINON 15 13 PR264 SHORT_PAD_6
EN BOOT B-test
54418-1.8_VFB 6 14 PC200 PR147
C3C VSNS PWRGD C3C 0.1u/50V_6 51.1/F_4
PC193 7 3
COMP GND
1000p/50V_4
8 RT/CLK GND 4 R1
PAD
PAD
PAD
PAD
PAD
PAD
HWPG_1.8V (35)
9 SS AGND 5
PR262 PR263 PR146
15K/F_4 182K/F_4 100K/F_4 PC214 PC205 PC209
22
21
20
19
18
17
0.1u/25V_4 10u/10V_8 10u/10V_8
PC198
*100P/50V_4 B-test PC199
0.01u/25V_4 54418-1.8_VFB
PC197
1200p/50V_4 V0=0.8*(R1+R2)/R2
R2 PR145
78.7K/F_4
+5VPCU
2A
B-test change footprint
+1V Spec: 1.5A
Rating: 6A
PC12
PC103 SW@0.1u/25V_4 C-test
SW@10u/10V_8
PU8 SW@HPA00835RTER
16
VIN PH 10
1 11 PL3
VIN PH SW@1uH/11A_7X7X3
PR273 2 12 B-test
SW@SHORT_PAD_4 VIN PH
15 13 PR5 SW@SHORT_PAD_6 C-test
(41) PG_GPUIO_EN EN BOOT
54418-1_VFB 6 14 PC4
RAMP C3C VSNS PWRGD C3C SW@0.1u/50V_6 PR15
PC16 7 3 SW@51.1/F_4
COMP GND
SW@1000p/50V_4
8 RT/CLK GND 4 R1
PAD
PAD
PAD
PAD
PAD
PAD
PG_1.5V_EN (40)
9 5 PR25
PR22 PR16 SS AGND PR160
SW@10K/F_4
SW@8.06K/F_4 SW@182K/F_4 +3V_D_EXT SW@20K/F_4
22
21
20
19
18
17
PC5 PC102 PC6

PC111 B-test C-test SW@0.1u/25V_4 SW@10u/10V_8
B PC107 B-test SW@10u/10V_8
*SW@100P/50V_4
SW@0.01u/25V_4 54418-1_VFB B-test
PC15
SW@1200p/50V_4
PR159 V0=0.8*(R1+R2)/R2
SW@78.7K/F_4 VIN_SR
R2
P
S
C3C
3
PR37
SW@SHORT_PAD_4
+1.5V_GPU 2
PR
+3V +5V SW
VIN_SRC +1.8V +1.5V +15V PQ13
1
7/9 change power enable SW@DTC143EUA
PC36
PR141 PR129
net name to +1.5V_GPU SW@1u/10V_4
Add it for S3 leakage circuit
PR120 22_8 22_8 PR249 PR258 (ZY9B solution)
(16) MAINON_G 1M/F_6 22_8 22_8 PR251
1M/F_6
MAINON_G MAIND
A MAIND (16,36,40)
3
3
PR121
2 1M/F_6 2
(35,38,39,40) MAINON PC185
2 2
2 2 PQ67 *2.2n/50V_4
1
PQ62 DMN601K-7
1
PR253 DTC144EUA PQ19

1
*100K_4 PQ18 PQ61 PQ69

1
DMN601K-7
1
DMN601K-7 DMN601K-7 DMN601K-7

2
5 4 3 2
1
+1.8V
IN_SRC +1.8V_GPU +15V
PR38 PR184 PR41

SW@1M/F_6 SW@22_8 SW@1M/F_6 Spec: 1.43A
1
2
5
6
Rating: 7A
3 PQ11
SW@AO6402A
3
2 +1.8V_GPU
3
PR45
SW@1M/F_6
1.9A
2
1
PQ10 PQ12 PC35

1
SW@DMN601K-7 *SW@2.2n/50V_4
SW@DMN601K-7
A

PROJECT : ZQ1
1A
Discharge/1.8V)
1
5 4 3 2
VA PD3 PR174
PL2 SBR1045SP5-13 PQ31 0.01/F_7520 VIN_SRC
POWER_JACK HI0805R800R-00_8 1 FDD6685
4 VDC 3 VA1 3 4 1 2 3
3 2
2
1
1
1
PC25 PC21 PC20 PR33 PC124 PC126 PR28
PJ2 2200p/50V_6 PL1 0.1u/50V_6 PD4 0.1u/50V_6 220K/F_6 PC216 0.1u/50V_6 2200p/50V_6 33K_6
HI0805R800R-00_8 PR34 SMAJ20A VIN_SRC *10u/25V_1206
*33_1210
PC226
2
D PC26 CSIP_1 C-test 1u/25V_6
0.1u/50V_6 1 6
added for EMI suggestion on 1217
PD5 PR32 2 5
SW1010CPT 220K/F_6
PR46 3 4
1/21 ramp reserve for EMI ISN issue *33_1210
PQ7
IMD2AT108
VIN_SRC 2
(35) D/C#
VDC PC28
C3C
CSIP_1
*2.2u/25V_8
VIN_SRC
EC231 EC232 EC233 EC234 EC235
*10u/25V_1206 *10u/25V_1206 *10u/25V_1206 *10u/25V_1206 *10u/25V_1206 PC108
1u/16V_6
ramp apply for power requirment PR166 PR163

VDC 10/F_6 10/F_6
PR164 PC217 PC130

PC115 4.7_6 PC114 *10u/25V_1206 10u/25V_1206
EC236 EC237 0.1u/50V_6 1u/16V_6
22u/25V_1210 22u/25V_1210 PC227 PC228
1u/25V_6 0.1u/50V_6
CSIP CSIN C-test
C-test PD2 PC129
33
32
31
30
28
27
26
21
C
1
+3VPCU PC125 +3VPCU *RB500V-40 2200p/50V_6
5
6
7
8
0.1u/50V_6
NC
GND
GND
GND
GND
CSSN
VCC
CSSP
VDDP
PR23 PC110
2.7_6 0.1u/50V_8 88731_DH 4
PR171 MBDATA 11 25 C3C
100K/F_6 VDDSMB BOOT PQ30
PU2 AO4468 0.01_3720
CM1293A-04SO MBCLK 9 24 PR167
MBDATA SDA UGATE PL6
1 6
CH1 CH4 6.8uH
3
2
1
2 5 +3VPCU 10 23 88731_LX 1 2
VN VP (35) ACIN SCL PHASE
5
6
7
8
TEMP_MBAT 3 4 MBCLK
CH2 CH3
13 20
ACOK LGATE PR173
PC112 88731_DL 4 *4.7_6
PR161 0.1u/50V_6 19
PR12 49.9/F_6 PGND
*Short_6 DCIN 22
DCIN PU9 PR162 PQ28 PC128
PR26 ISL88731A 10/F_6 AO4710 *680p/50V_6 PC119
82.5K/F_6 18 CSOP CSOP_1 2200p/50V_6
3
2
1
CSOP
2
PC106 ACIN 10u/25
0.1u/50V_6 PC121
2 1 PR27 3 0.1u/50V_6
22K/F_6 VREF
B 17 CSON BAT-V
CSON
PC104 4 PR165 CSOP_1
100p/50V_6 ICOMP 10/F_6 C3C
16
NC BAT-V
5 PR168
HI0805R800R-00_8 NC SHORT_PAD_4
PJ1 PL4 15 BAT-V
MBAT+ BAT-V VBF
6
10 1 VCOMP PR169
29
2 GND 100_4 VIN_SRC VIN
GND
3
ICM
NC
NC
PL5 PQ29
4 HI0805R800R-00_8 AOL1413
5 PD1 7 1
14
12
6 RB500V-40 2 5
7 PR170 3
9 8 TEMP_MBAT 2.21K/F_6
TEMP_MBAT (35)
Batt_Conn PR18 PC229
PC9 PC11 *0_6 *10u/25V_1206
4
10/5 modify 47p/50V_6 47p/50V_6 PC215 PR31
ICMNT (35)
PC123 1u/25V_6 150K_6
+3VPCU C-test
0.01u/50V_6
PR13
100K/F_6
PR11 PR10 PC118 B-test
100_4 100_4 *1u/16V_6 PC122
PC120 *0.01u/50V_6 PR30
MBCLK (35) 0.01u/50V_6 39K_6
A
3
MBDATA (35)
(35) VIN_ON 2
PQ6 Quan
DMN601K-7
PROJE
1
CHARGER (ISL8873
5 4 3 2
1
PQ24
FDD6685
3 4 BAT-V
1
D
PR29
10K_6
3
PQ5
DMN601K-7
1
V_1206
3C
BAT-V
19
50V_6
PC116 PC109
10u/25V_1206 10u/25V_1206
uanta Computer Inc.

OJECT : ZQ1
Rev
1A
88731)
Sheet 45 of 48
1
PROJECT :ZH3
1 2 3 4
VIN
A
PD10
SW1010CPT
PR178
1M_6
1
PQ34
AO3409
TH_ON 2
3
Thermal protection
3
S5_ON 2
PQ32
1
B VL VL DTC144EUA
SYS_SHDN# (4,36)
PR179 PR181
? 1K_4 200K/F_4 PR180
200K/_6
PC132
0.1u/50V_6
3
8
PR177
10K _6_NTC 2.469V 3
+
1 2
NTC 2
- PQ35
PU10A DMN601K-7
4
LM393 PC131
1
0.1u/50V_6
PR182
C 200K/F_4
3
S5_ON 2
(35,36) S5_ON
PQ33
DMN601K-7
1
5 +
7 NC_TEMP
T86
6
-
PU10B
LM393 For EC control thermal protection (output 3.3V)
Quanta
PROJECT
Thermal Protection
1 2 3 4
5
nta Computer Inc.

CT : ZQ1
Rev
1A
ion
Sheet 46 of 48
5
5 4 3 2 1
MODEL
ZQ1
Model REV CHANGE LIST FROM To
X 1A
Schematic first released.
ZQ1 MB 1A X 1A
1A 2A
All TP footprint change to "TP3050"
2A 1A 2A
Delete all power jump besides JP3
1A 2A
Page03. Change C772 to CH02706JB06
1A 2A
Page04. Change R493,R205,R204,R156,R489,R486 to shortpad
1A 2A
Page04. Change U35 to AJSLGZS0T07
1A 2A
Page08. Change R351,R354,R353,R355,R622,R514,R513 to shortpad
D
1A 2A D
Page08. Change R248 to CS21002FB24
1A 2A
Page09. Change R609 to shortpad
1A 2A
Page09. Change U40 to AKE38ZP0N01
1A 2A
Page10. Staff Y4,C695,C696,R512 for all sku, and change C695,C696 to CH01006JB08
1A 2A
Page10. Change R235,R234,R620,R515,R516 to shortpad
1A 2A
Page10. Add T114,T115
1A 2A
Page10. Reserved BOARD_ID1~3. Add and reserve R629,R630,R31,R632,R633,R634.
1A 2A
Page10. Change SMbus PU to +3V_S5
1A 2A
Page11. Change R607,R556 to shortpad
1A 2A
Page11. Staff R283 and unstaff R279 for all sku
1A 2A
Page12. Staff R252 and delete R253
1A 2A
Page12. Change R271 to CX08T121001
1A 2A
Page16. Change Q32 to BAM70020002
1A 2A
Page19. Change R69 to CS05102JB35 and swap C203 and R64
1A 2A
Page20. Add and staff Q38,C806,C807,C808. Add and reserve R635,R636 for +3V_D_EXT to separate internal and external power domain.
1A 2A
Page22. Add and reserve R637.
1A 2A
Page25. Change L39,L40,L41 to CX8LL470000, C598,C596,C578,C579,C597,C599 to CH-6806TB01. Staff C572
1A 2A
Page25. Change CN4 to DFHS08FR774. Change netname PANEL_ENG to DCR_EN and delete PANEL_COLOR
1A 2A
Page25. Modify dGPU_SELECT# circuit for leakage and change R37 to CS41002JB20
2A 3A
Page26. Add HDMI_HPD_PCH# to PCH GPIO13. Add and reserve R639
2A 3A
Page26. Change Q30 to BAM70020002
2A 3A
Page27. Change U27 to AL008151003
2A 3A
2A 3A
Page27. Add R648 to AVDDH for EMI
2A 3A
Page28. Change CN1 to DFFC10FR138 and add USB port5. Add and reserve R640,R641
C
2A 3A C
Page28. Change Q26,Q27 to 2N7002K
2A 3A
Page29. Change HOLE13,HOLE25 footprint
2A 3A
Page30. Staff R565 and delete R568
2A 3A
Page30. Change R315,R319 to CS05602JB17
2A 3A
Page30. Change U30 footprint to TRF-10-1-24P-smt
2A 3A
Page31. CN10 change to DFHD39MR001
2A 3A
Page31. R525,R233 change to CX08T121000
2A 3A
Page32. Change U33 to AL003510000
2A 3A
Page32. Unstaff R229,R231,R295,R296,R297,R298,R363,R346 and staff L24,L28,L29,L32 DC09004A014
2A 3A
Page32. Change CN9 to DFW F05MR042
2A 3A
Page32. Change SW 2,SW 3 pin5,6 to GND
2A 3A
Page32. Change C688 to CC73301MZ00
2A 3A
Page33. Add and reserve C809
2A 3A
Page33. Add and reserve R642. Add Q39 for RF_LED function
2A 3A
Page33. Change CN3 to DFFC06FR255 and add P_SAVE_LED. Add R643,R644 CS41002JB20
2A 3A
Page34. Add and reserve C810
2A 3A
Page34. Change C344 to CH4104K9B03, C349 to CH31004KB17
2A 3A
Page35. Add J3 and unstaff SW 1
2A 3A
Page35. Staff C347 CH31006K919
2A 3A
Page35. Change R474,R477,R455,R453 to shortpad
2A 3A
Page35. Add and reserve R645. Add VGA_THERM# to GPU thermal sensor
2A 3A
Page35. Add RE_LED_EN# and RE_LED# for LED function. Add and reserve R647
2A 3A
Page35. Delete PANEL_COLOR and add T116,R646
2A 3A
Page35. Change U29 to AKE38FP0N01
2A 3A
Page36. Change PC190,PC194 to CH73301M8B9, PC180 to CH61004M291
B
2A 3A B
Page36. Change PR139 to CS41502FB18, PR131 to CS42003F919, PR136 to CS41823F914, PR142 to CS21002FB24
3A 3B
Page37. Change PU5 footprint to qfn40-5x5-4-41p-0_75h-smt
3A 3B
Page37. Change PC75,PC74,PC71,PC72 to CH61004M291, PL11,PL12 to CV+18V0MZ04
3A 3B
Page38. Change PR43 to CS23923F910, PL9,PL10 to CV-2280MZ05
3A 3B
Page39. Change PR269 to CS23903F911
3A 3B
Page40. Unstaff PC77. Change PR109 to CS24993F949, PL14 to CV-15K0MZ05, PC86,PC169 to CH61004M291
3A 3B
Page41. Change PR1 to CS44702FB13, PR9 to CS34422FB00, PR14 to CS34992FB10, PR19 to CS42202FB10, PR157 to CS36202FB19
3A 3B
Page41. Change PL7 to CV+18V0MZ04, PC101,PC105,PC113 to CH61004M291, PC17,PC18 toCH733RY8802
3A 3B
Page42. Change PC33,PC31 to CH61004M291
3A 3B
Page42. Change PU4 footprint to TQFN20-1_8X3_2-4-SMT
3A 3B
Page42. Unstaff PQ9,PR62,PR64,PR72,PR80
3A 3B
Page43. Change PC150,PC151 to CH61004M291, PC153 to CH34702KB10
3A 3B
Page43. Change PU11 footprint to QFN28-4X4-4-29P-smt
3A 3B
Page44. Add PU8,PR160 "SW @" and remove PL18 "SW @"
3A 3B
Page44. Change PC191,PC013 to CH6102K9A19, PC197,PC15 to CH21206KB13, PR262 to CS31502FB08, PR22 to CS28062FB21
3A 3B
Page44. Change PC102,PC6,PC205,PC209 to CH6102K9A19, PC197,PC15 to CH2126K1B05, PR262 to CS31502FB24, PR22 to CS28062FB21
3A 3B
Page44. Change PL18 footprint to CHOKE-PCMC063T-3R3MN-NB4
3A 3B
Page44. Change and staff PR25 to CS21002FB24
3A 3B
Page44. Add PR273 and unstaff PR24
3A 3B
Page45. Add PC215 CH5104K9906
3A 3B
Page45. Change PR30 to CS33903J914, PR31 to CS41503J932
3A 3B
3A 3B
Page08. Delete R514,R513 and add R653,R654,R655 for EMI
3A 3B
3A Page09. Staff R249,R245 and unstaff R255,R254. U40 change to AKE391P0N00
3A 3B
A
3A 3B A
Page12. Change C390 to CH6221M9A07 for CRT garbage issue.
3A 3B
Page18. Delete T75,T76,T78,T79,T77,T80,T82,T83 and add R656,R657,R658 for EMI
3A 3B
Page22. Update VRAM strapping table
3A 3B
Page25. Staff L1 DC09004A014 and unstaff R17,R18 for EMI
3A 3B
Page25. Add F1 DK100TPU028 for safety. Add R666 for EMI
Page25. Add R667,R668,R669 for CRT garbage
Page26. Delete R436,Q12, and R143,Q11 remove SW @
Page26. Add and reserve R665,R664,Q43,Q44 for HDMI logo, F2 for safety
DOC NO.
PROJECT MODEL : ZQ1 APPROVED BY: Kevin Hsieh DATE: 2009/10/05 PROJECT : ZQ1
1A
PART NUMBER: 31ZQ1MB0000 DRAWING BY: Benson Yo REVISON: 1A Change list
Date: Thursday, January 21, 2010 Sheet 47 of 48
5 4 3 2 1
5 4 3 2 1
MODEL
ZQ1
Model REV CHANGE LIST FROM To
X 1A
Page27. Unstaff R648. Add and reserve L60,L61,L62,L63,L64,L65,L66,L67,C811,C812,C813,C814,C815,C816,C817,C818 for EMI
ZQ1 MB 3A X 1A
Page27. Change U32 footprint to qfn40-5x5-4-41p-0_8h
1A 2A
Page28. Change R547,R549,R553,R557,R561,R267,R266,R418,R423,R421 to shortpad
1A 2A
1A 2A
1A 2A
Page31. Change CN10 to DFHD36MS006
1A 2A
Page32. Change L22 footprint to CHOKE-W CM2012-4P
1A 2A
Page33. Modfiy W L LED schematic. Add R649. Add and reserve R650
D
1A 2A D
Page33. Change R369,R370,R371 to CS03902JB21, and R365,R361,R367 to CS-4702JB29
1A 2A
Page33. Add Q40 and change P_SAVE_LED netname to P_SAVE_LED#
1A 2A
Page33. Move symbol from D/B to M/B. Add Q41,Q42,R651,R652,R659,R660,R661,R662,R663 and change R663 to CS16802JB27
1A 2A
1A 2A
Page34. Staff C513 CH5104K9906 and add C819 for EMI
1A 2A
Page35. Change U29 to AKE37FN0N01
1A 2A
Page36. Add PC220,PC221,PC222,PC223. Add and reserve PC218,PC219,PC224,PC225 10uF for EMI
1A 2A
Page38. Change PU3 footprint to mlpq16-3x3-5-17p-smt
1A 2A
Page38. Add L68,L69 for CRT noise
1A 2A
Page39. Change PU13 footprint to mlpq16-3x3-5-17p-smt
1A 2A
Page41. PR6 PU change to +3V_D_EXT
1A 2A
Page44. PR25 PU change to +3V_D_EXT
1A 2A
Page44. Change PU8,PU12 footprint to mlpq16-3x3-5-17p-smt and PL3 to CHOKE-PCMC063T-3R3MN-NB4
1A 2A
Page45. Change PU9 footprint to QFN28-5X5-5-33P-smt
1A 2A
Page45. Add PC226,PC227,PC228. Add and reserve PC216,PC217,PC229 10uF for EMI
1A 2A
1A 2A
Page10. Staff R632
3B 1A 2A
Page10. Change Y4 to BG625000788
1A 2A
Page25. Change L39,L40,L41 to CX8BA470003 and C598,C599,C596,C597,C578,C579 to CH01006JB08
2A 3A
Page26. Staff Q43,Q44,R664,R665 and unstaff R435,R434
2A 3A
Page38. L68,L69 change to CX09T170000
2A 3A
2A 3A
Remove +VGPU_IO schematic
3C 2A 3A
2A 3A
Page08. Delete R653,R654,R655
C
2A 3A C
Page10. Update Board_ID table and staff R629 for ZQ1
2A 3A
Page10. Delete T51,T55,T61,T63,T100,T102,T115
2A 3A
Page11. Delete TP5,TP6,TP7,TP8
2A 3A
Page12. Change R529,R526,R292,R539,R540,R309,R230,R294,R322,R325,R314,R246,R238,R338,R337,R578,R288,R269,R252 to shortpad
2A 3A
Page12. Unstaff R286 and change C445 to CS00002JB38
2A 3A
2A 3A
Page18. Delete R656,R657,R658
2A 3A
2A 3A
Page25. Swap F1 and D7 location
2A 3A
Page25. Delete R17,R18,R667,R668,R669
2A 3A
Page25. Change R106,R81,R99,R38,R39,R12,R409 to shortpad
2A 3A
Page25. Change R666 to CX05T121000
2A 3A
2A 3A
2A 3A
Page28. Change R423,R418,R421 to 0ohm
2A 3A
2A 3A
2A 3A
Page30. Add Q45,Q46,Q47,R653 for vendor suggestion
2A 3A
Page30. Change R468,R471 to CX08T221000 and C663,C670 to CH06806J901 for EMI
2A 3A
Page30. Swap CN12 pin define
2A 3A
Page30. Change R535,R532,R543 to shortpad
2A 3A
2A 3A
Page32. Change R225.R228 to shortpad. Delete R229,R231,R295,R296,R297,R298,R363,R346,L22 co-layout parts.
2A 3A
2A 3A
B
2A 3A B
3A 3B
Page36. Change PR123,PR126,PR127,PR128,PR130,PR132,PR133,PR134,PR138,PR254,PR259,PR260 to shortpad
3A 3B
Page37. Change PR70,PR78,PR79,PR106,PR107,PR185,PR195,PR199,PR200,PR202 to shortpad
3A 3B
Page38. Add PC230 CH41006K911
3A 3B
Page38. Change L68,L69,PR36,PR39,PR183 to shortpad
3A 3B
Page39. Change PR266,PR267,PR271 to shortpad
3A 3B
Page40. Change PR99,PR102,PR112,PR114 to shortpad
3A 3B
Page41. Change PR152,PR154 to shortpad
3A 3B
Page42. Change PR219,PR220,PR223,PR234,PR236,PR247 to shortpad
3A 3B
Page43. Change PR5,PR37,PR261,PR264,PR273 to shortpad
3A 3B
Page43. Change PQ13 to BA001430Z49
3A 3B
Page43. Delete PR24
3A 3B
Page44. Change PR168 to shortpad
3A 3B
Page44. Add and reserve PR34,PR46,PC28 for power requirement
3A 3B
Page44. Add EC236,EC237. Add and reserve EC231,EC232,EC233,EC234,EC235 for EMI
3A 3B
Page44. Change PR167 footprint to RC3720-SMT
3A 3B
3A 3B
Update Block Diagram, PW R Status & Flow Chart
3D 3A 3B
Page03. Unstaff R300
3A 3B
Page09. Staff R344
3A 3B
Page10. Staff R634
3A 3B
Page18. Unstaff R77,R73
3A 3B
Page19. Unstaff R68 and staff R50 CS31002JB28
3A 3B
Page27. Staff L60,L61,L62,L63,L64,L65,L66,L67 CVB4713TN09 and C811,C812,C813,C814,C815,C816,C817,C818 CH-5606TB01
3A 3B
Page30. Change R315,R319 to CS07502JB27. Unstaff R653,Q45,Q46,Q47
A
3A 3B A
Page33. Change R660,R661,R662 to CS14532FB14, R663 to CS22202JB18, R369,R370,R371 to CS18062FB29, and R361,R365,R367 to CS05602JB17
3A 3B
Page36. Change PD9 to BDDZS36BZ00
3A 3B
3A 3B
3A 3B

DOC NO.
PROJECT MODEL : ZQ1 APPROVED BY: Kevin Hsieh DATE: 2009/10/05 PROJECT : ZQ1
1A
PART NUMBER: 31ZQ1MB0000 DRAWING BY: Benson Yo REVISON: 1A Change list
Date: Monday, February 08, 2010 Sheet 48 of 48
5 4 3 2 1

Intel: USB Board

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Intel: USB Board

Uploaded by

Copyright:

Available Formats

5 4 3 2

ZQ1 BLOCK DIAGRAM GPU CORE PWR

DDR SYSTEM MEMORY

SPDIF/HP INT MIC DMIC P33

3/5V SYS PWR

CPU CORE PWR D

SIM Card FFC

uanta Computer Inc.

GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

Power States Thermal Follow Chart

VIN +10V~+19V MAIN POWER S0~S5

+VCCRTC +3V~+3.3V RTC S0~S5 NTC

+15V +15V LARGE POWER +15V_ALWP S0~S5

+5V_S5 +5V S5D S0~S5

+3VSUS +3.3V SUSD S0, S3

+1.5V_SUS +1.5V SODIMM POWER SUSON S0, S3

+0.75V_DDR_VTT +0.9V SODIMM POWER MAINON S0 SML1ALERT#

+5V +5V MAIND S0 PCH FAN Driver FAN

+1.8V +1.8V MAINON S0 SM-Bus

+1.5V +1.5V PCH POWER MAIND S0

+1.1V_VTT +1.05V~+1.1V CPU POWER MAINON S0 EC

+VCC_CORE 0V~+1.5V CPU CORE POWER VRON S0

LCDVCC +3.3V LCD Power LVDS_VDDEN S0

MBAT+ +10V~+17V MAIN BATTERY

Quanta Computer Inc.

CLK Gen(CLK) pi-filter

+3V +3V CRB use

nta Computer Inc. A

Arrandale_1(CPU) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JT

AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) Processor Compensation Signals

JTAG & BPM

Thermaltrip protect(CPU) VTT PWR_Good(CPU) Processor pull-up(CPU) JTAG MAPPING(CP

XDP_TMS R165 *51_4 *0_4

0.1u/10V_4 4/9 REV:B MODIFY BY DG1.52

hort_4 PM_EXTTS#0 (14)

hort_4 XDP_DBRST# (8,16) C

STUFF -> R469, R491, R507

STUFF -> R490, R491

Quanta Computer Inc.

(15) M_B_DQ[63:0] SB_CK[0] W8 M_B_CLK0 (15)

DDR SYSTEM MEMORY - B

M_A_DQ35 AK7 F8 M_A_DQS#1 M_B_DQ40 AK3 AR5 M_B_DQS#6

Channel A DQ[15,32,48,54], DM[5] Channel B DQ[16,18,36,42,56,57,60,61,62]

VTT Rail Values are

1.1V RAIL POWER

CPU CORE SUPPLY

PEG & DMI

VCC62 VTT1_52 VTT1_68

VCC88 VCC_SENSE VCCSENSE (37)

R190 R185 R193 R197 R200 R206 R202 R499 R498

C329 C321 C301 C296

Quanta Computer Inc.

Arrandale_4(CPU) AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED,

AT20 AE34 AJ13

AL20 W6 E21 AJ29 E15

1 0 CFG4 R157 *3.01K/F_4

CFG0 CFG[ 1:0 ] - PCI_Epress Configuration Select CFG7 R497 *3.01K/F_4

; EDS/DG suggestion to GND

Quanta Computer Inc.

PCH1(CLG) IBEX PEAK-M (DMI,FDI,GPIO)

Digital Display Interface

R353 *Short_4 PCHPWROK B17 BF41

XDP_TMS R165 51_4 0_4