USN

P.E.S. College of Engineering, Mandya.

(An Autonomous Institution affiliated to VTU, Belagavi)
3rd semester, BE- ECE
Digital Logic Circuits-P21EC304
Semester End Examination
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Note: i) Part – A is compulsory, One question from each unit
ii) Part – B: Answer Two sub questions for Max .of 18 marks from each unit.
Q. No. Questions Marks Bloom’s Taxonomy

PART – A 10 CO’ BL’s PO

All Questions are Compulsory s

a Realize the Boolean function 𝐹 = 𝑌𝑍 + 𝑋𝑍 ′ + 𝑊𝑍 using NAND gate. 2 1 2 1

b Write the Characteristic table and Equation for SR flip-flop. 2 2 2 2

c Design State Graph for Serial Adder 2 3 3 4

d Write a AND-OR plane structure of PLA 2 5 2 3

e Write a block diagram of Accumulator. 2 4 2 2
PART – B 90
Unit – I 18
a Find the minimal sum expression for the following Boolean function 9 1 2 1
using k-map and Realize using only NAND gates. F (W, X, Y, Z) =
∑m(2, 8, 11, 15) + dc (3, 12, 14).
1 b Design and implement full adder and full subtractor circuit with appropriate 9 1 2 2
decoders.
c Design and implement the logic function Y= ∑𝑚(0,2,4,6,9,10,12,13) 9 1 2 2
using optimum configuration of multiplexer.
Unit - II 18
a Write a circuit of Positive edge triggered D-flip-flop and provide explanation for 9 2 3 2
different input conditions.
b Design a Bidirectional shift register with parallel load with register operation 9 2 2 2
for select lines as given in table.
S1 S0 Register operation
2 0 0 Shift left
0 1 Shift right
1 0 Parallel load
1 1 No change
c Design a 4-bit Binary counter with Parallel load using JK flip-flop. 9 2 2 3
Unit - III 18
 a Distinguish between Mealy and Moore model with necessary block 9 3 2 4
diagram

b Design a Mealy type sequence detector to detect a serial input of 101. 9 3 4 5

3
c With an example explain Reducing Incompletely Specified State Tables 9 3 3 4
and its implication charts.

Unit – IV 18
a Implement Boolean function F= A’B’ +ABC’ using 8 to 3 RAM 9 5 4 3

b Implement the following Boolean functions using a 3 × 4 × 2 PLA. 9 5 3 3

4
F1 ( A, B, C) = ∑s(3, 5, 6, 7) and F2 ( A, B, C) = ∑(0, 2, 4, 7).
c Explain with required schematic Architecture of XILINX XC9500 9 5 2 3

Unit – V 18
a With the help of neat diagram explain the working of Integrated –circuit 9 4 2 2
Memory.
5 b Explain the different operations obtained by controlling one set of input 9 4 3 2
to a parallel adder of an ALU.
c Design any 5 micro-operations for accumulator. 9 4 3 2

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