Proceediigs of the 1985ACM Computer Science Conference-Agendafor ComputingResearch:
TheChallengefor Creativity,1985March 12-14
VLSI DESIGN PROCESS
Vishwani D. Agrawal
Samuel H. C. Poon
AT &T Bell Laboratories
Murray Hill, New Jersey 07974
ABSTRACT- This paper presents a review of the computer-
aided design of VLSI devices. For illustrative purposes, the
design methodology is modeled as an idealized two-level process.
In the first level, known as the functional level, the requirements
of the device are converted into logic description and tests are
generated. The second level consists of the physical design
involving layout. In each level, our model represents the design as
a feedback process with verification closing the loop on synthesis
or layout. While the future design methodology might be closer
to this idealization, today’s design process differs significantly
depending upon the specific design environment.
1. INTRODUCTION
The primary objective of VLSI design is to produce the
details of a VLSI device so that it can be physically
realized. The main activities of the design process are
functional design, test generation, and physical design.
The solutions of complex design problems have relied on
experienced experts and on computer-aids. However, with
the tremendous growth in the complexity of VLSI, a
greater use of computer aids can be anticipated.
In this paper, a systems approach is used to model the
design process. This model emphasizes tighter feedback
loops to minimize the time of design cycle. A variety of
computer-aided design (CAD) tools that support the
design activities, are described. Unfortunately, a real
design may rarely follow the idealized model.
2. VLSI DESIGN CYCLE
The design activities can be divided into two phases:
functional and physical. The functional phase consists of
synthesis and testability. The iterations between synthesis
and verification ensure that the design will meet the
requirements. Similarly, tests are verified through fault
simulation. Then the logic design and test data are passed
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on to the physical design phase. The physical design
mainly consists of mask layout. After layout, the design is
further verified for the effects of capacitance and resistance
due to routing and interconnection. Again, the physical
design and the verification form a tight iterative loop. If
the design requirements are satisfied after the physical
layout, the design, in the form of mask and test data, is
passed on to manufacturing.
In order to minimize the design cycle, the design issues, as
much as possible, must be resolved in the functional design
phase. For example, the design cycle would be lengthened
if the design requirements cannot be satisfied during the
physical layout primarily due to difficult to meet timing
requirements. Then the functional design would need
modification and the physical design will have to be
repeated. During functional design, the CAD tools that
help designers, are the tools for floor planning, and
accurate timing and testability analyses.
To elaborate upon this concept further, let us consider the
interaction between the functional design and the physical
design. In Fig. 1, which illustrates our model, the
feedback between the design levels occurs in two ways.
The feedback, that is totally contained within a design
phase, provides efficient verification. However, the feedback
between the phases could lengthen the design process. For
example, certain timing problems discovered during layout
verification may not be correctable on the layout. These
will require modifications in the functional design.
3. COMPUTER-AIDED DESIGN
As shown in Fig. 1, the design is accomplished in two
steps. The functional design, is supported by computer-
aided engineering (CAE) tools. The second step, physical
design, is supported by a variety of computer-aided design
(CAD) took.
Figure 2 shows how the computer-aids would fit in an ideal
design process. The various computer aids [ll used in this
process are described below.
Requirements Analysis. The design begins with an
analysis of the requirements consisting of functional and
physical (package, power, cost, reliability, etc.)
specifications. The analysis is aimed at determining the
completeness and feasibility of the specifications. This
k’roceedmgs of the 1985 ACM Computer Science Conference-Agenda for Computing Research: The Challenge for Creativity, 1985 March 12-14

DESIGN \ MANU;;;CTJRING -+

LOGIC
I DESIGN AND ’ MASK AND VLSI
REQUIREMENTS SYNTHESIS TEST DATA TEST DATA WAFER DEVICES
p AND TEST C LAYOUT w FABRICATION b
4 GENERATION - -b + AND PACKAGING -

- VERIFICATION * - VERIFICATION +- - TESTING *

a -
TIMING, TESTABILITY. TIMING, TESTABILITY,
QUALITY, RELIABILITY QUALITY. RELIABILITY
AND YIELD PROBLEMS AND YIELD PROBLEMS
Fig. 1 VLSI design and manufacturing. The three part process would, in an ideal case, be supported
by computer-aided engineering (CAE), computer-aided design (CAD), and computer-aided
manufacturing (CAM). The feedback shown in heavier lines must be reduced or eliminated for
an efficient design cycle.

VERIFICATION
4k2”KLENTS

t
ARCHITECTURE

1
AUDITS I TESTABILITY, DESIGN CAPTURE
VERIFICATION
SIMULATION FLOOR -FLANNING
TJMING ANALYSIS // \\

\ 1 SYNTHESIS 1 1 SYNTHESIS 1 1 SYNTHESIS 1 1 c&+&s

\ 1 CHIP MOC
GENERATION

VERIFICATION

,FJl+“LCIRCUIT
--I EXTRACTION I I

DESIGN AND 4 I
TEST DATA

Fig. 2 The activities of an ideal design process.

75
 Proceedings of the 1985ACM Computer Science Conference-Agenda for Computing Research:The Challenge for Creativity, 1985March 12-14
analysis is commonly carried out manually by experts
although some computer aids are possible [2].
Algorithms. A conceptual design produces algorithms
which when implemented in hardware will meet the
functional requirements. Complex algorithms can be
simulated and validated using computers. Designers write
programs for this verification as there are no general
purpose C.4D tools. Conceptual design of a chip is
essentially a manual process.
Architecture. The algorithms are implemented by means
of an interconnection of functional blocks. Typical
functional blocks may be arithmetic logic unit (ALU),
memory (RAM, ROM), control unit (finite state
machine), bus, etc. Architectural design is also a manual
process and its correctness must be verified. Although
simulation at this point is not very common, some CAD
tools have been developed. The chip is modeled in a high
level language like C or Pascal. Simulators like AIDE 131
allow simulation of a large number of situations to cover
the functional specifications. Chip stimuli (vectors) and the
expected responses for logic verification are also generated.
Floor planning is an approximate layout of the chip
geometry. Sizes of functional blocks are estimated and
they are placed on the plan. Technology (NMOS, CMOS,
bipolar, and feature size) is taken into account. Floor
planning provides initial information on chip size, speed,
yield, and cost. These are matched with the chip
requirements. Problems will lead to changes in architecture
and/or algorithms.
Synthesis. The design from architecture to layout is
carried out in several stages. The functional blocks in
architecture are transformed into logic (Boolean gate)
design, logic design is transformed into circuit (transistor
or MOS device) design, and finally, the design is iaid out
as a set of geometrical masks. In order to analyze and
verify the design descriptions by computers we need
hardware description languages. Hardware description
languages (HDL) serve the same purpose in hardware
design as the programming languages in software. Various
HDLs describe the circuit at behavior (or register-
transfer), logic, device, and mask levels 141. Synthesis
refers to translation of circuit description either to physical
(mask) or closer to physical level. There is no general
synthesis procedure. Logic synthesis traditionally has been
a manual process. There are, however, CAD tools available
for combinational logic minimization [51, 161. Using these
it is possible to synthesize control logic in the form of finite
state machines and programmable logic arrays (PLAs) [7].
Another popular style of synthesis uses standard cells [8],
[9]. Standard cells are general purpose logic blocks with a
complexity of 30 to 40 MOS transistors and can be very
effectively laid out by interactive CAD tools 1101. Cell
libraries (files cuntaining logic, device and mask level
data) are used for synthesis, verification and layout.
More recent form of synthesis tools, still in the
development stage, are the silicon compilers. These
convert the high level functional description directly into
layout. Algorithms are, of course, devised manually. They
arc then coded in a programming style hardware language.
76
One such system, known as PLEX (111, uses the C
programming language. Synthesis is performed for a fixed
and predetermined architecture. PLEX produces the layout
of a special purpose microprocessor to implement the chip
function. Another silicon compiler is MacPitts [121,
developed at MIT.
Layout of chips, in the absence of CAD tools would have
been the most laborious task. Fortunately, many layout
tools are available. Basic layout problems are placement
and interconnection 1131. Placement produces a detailed
floor plan. Often, placement is done manually and
interconnection (or routing), automatically. However, some
automated placement and routing systems are in use for
standard cell designs 1141, 1151. Most device (transistor)
level layout systems [lo], 1161 are interactive and are used
for layout of standard cells and super-cells (few hundred
transistors). Large memory chips are an exception. These
chips contain thousands of transistors, but interactive
layout tools arc still useful because the chip has a
repetitive structure.
Other layout tools are layout editors 1171, design rule
checkers and circuit extractors 1181, [191. Layout editors
are special purpose editors which allow probing and
modification of mask description language. Layout design
rule checkers audit mask description for design rules
(minimum feature separation, etc.). Circuit extractors
perform reverse synthesis. They convert the mask
description into transistor level description which can be
simulated or compared with the prelayout description for
verification.
VeriJication is the process which ensures correctness of
design after it has been synthesized. For verification,
normally a functional, logic or transistor level model of
circuit is created. This model describes the circuit in
hardware description languages. Dynamic behavior is
verified through simulation. Input stimuli and expected
responses are produced from requirements or from
architectural simulation. Simulators are implementations
of algorithms which compute circuit activity. Logic
simulators treat the circuit as interconnection of Boolean
gates [201. MOS simulators can simulate circuits with
timing information (device characteristics, parasitics,
routing delays, etc.) 1211, [221 or with transistors as ideal
switches 1231. Circuit analysis programs 1241 represent
the most accurate tools. Because of the detailed analysis
they perform these programs are expensive to use. They
are normally used for simulating critical timing paths of
the chip.
Other forms of verification consist of static timing analysis
1251, and circuit comparison (topological isomorphism) of
extracted description with the verified prelayout description
1261. Other methods of verification which are being
developed are based on symbolic simulation and theorem
proving techniques 1271.
The errors discovered during verification must be analyzed,
and their causes, located and removed. These
modifications often impact the high-level design also.
Backward interactions of this type are the main reasons for
lengthy design schedules. It is beneficial to review the
 Fkceedmgs of the 1985ACM Computer Science Conference-Agenda for ComputingResearch:
design at various stages for possible problems of
manufacturability, reliability, verifiability, testability and
design updatability. Such audits are mostly manual but
there is scope for knowledge-based expert systems in this
area 1281.
Testing. A chip, designed and verified, can not be
produced unless tests are available. Processed silicon
wafers are tested on automatic test equipment (ATE).
Each chip on a wafer is tested under the control of a test
program which applies enough stimuli to the chip so as to
test all (or most) internal nodes. Test stimuli (in the form
of binary vectors) are generated as part of the design
process. These stimuli are different from verification
stimuli used in simulation. Unlike verification stimuli, test
stimuli have a fault coverage requirement. Tests are
expected to cover a high percentage (typically, 90 to 100
percent) of stuck-type faults [291. A fault simulator I301
is normally used for evaluating the fault coverage of tests.
It is difficult to guarantee high fault coverage for very
large chips unless testability is considered in the early
phases of design. Testability analysis tools 1311 provide
useful information about the testability of logic design.
The concepts of design for testability take a step further in
defining the design rules which will result in testable
design such that the whole process of test generation can
be completely automated I321. Of course, the cost of
testability is a slight amount (10 to 20 percent) of added
hardware. This added hardware is justified for very large
chips where high fault coverage (and high product quality)
can not be otherwise guaranteed.
4. CONCLUSION
In this paper we have presented the VLSI design as an
idealized model. CAD tools, that support various activities
of design, are reviewed. While today’s design process is
far from being ideal, the model gives some insight into the
future.
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