Computer Architecture and Organization Model Questions

1. Which of the following is not the main function of the computer?

A. Data Movement
B. Data Storage
C. Data Presentation
D. Control

2. Which of the following are not the main components of the computer system?
A. Main Memory
B. Hard Disk
C. I/O modules
D. Central Processing Unit

3. One of the following is not an architectural feature of a computer?

A. Instruction Set
B. I/O mechanism
C. Memory Technology
D. Addressing Techniques

4. What is the name of register that contain the address of the next instruction to be fetched
from memory?
A. Memory buffer register
B. Memory Address Register
C. Instruction Register
D. Program Counter
E. Accumulator

5. One of the following is not the performance assessment method of a computer?

A. Clock speed
B. Cycle Per Instruction
C. Amdahl’s law
D. Benchmarks

6. Which type of bus determines the maximum memory capacity of the system.
A. Data bus
B. Address bus
C. Control bus
D. None

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 Computer Architecture and Organization Model Questions

7. Which of the following is not an element of instruction.

A. Operation Code
B. Source Operand reference
C. Result Operand reference
D. Next Instruction reference
E. Previous Instruction reference

8. Which of the following is not true about direct addressing mode?

A. Operand is part of the instruction
B. Has better performance than indirect addressing
C. Address field of the instruction contains effective address
D. Maximum memory capacity is depended on the width of address field

9. What is the maximum memory space capacity of a simple machine that uses indirect register
addressing mode. Instruction length of a machine is 8 bits, where the opcode takes 4 bits and
the address takes 4 bits and all registers in the machine are 8 bits long.
A. 16
B. 64
C. 256
D. 65,536

10. What type of addressing mode does zero address instructions use.
A. Direct addressing mode
B. Displacement addressing mode
C. Stack addressing mode
D. Register addressing mode
E. Immediate addressing mode

11. One of the following is not a pipeline hazard

A. Resource
B. Data
C. Control
D. Movement

12. Which of the following is not a characteristic of RISC architecture.

A. Register to register operation
B. Few, simple addressing modes
C. Hardwired control unit
D. Less compile time/effort

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 Computer Architecture and Organization Model Questions

13. One of the following is not true about cache memory

A. Data transfer between main memory and cache memory is block transfer
B. Data transfer between CPU and cache memory is word transfer
C. Cache holds a copy of portion of man memory
D. Number of lines in the cache is equal to the number of main memory blocks.

14. Consider a 4-way set-associative cache,

- Data words are 32 bits long
- The cache holds 2 Mbyte of data
- Each block holds 16 data words
- Physical address are 32 bit long
How Many bits of tag (s-r), index (r ), and offset (w) are needed to support reference to the
cache?
A. 13 , 15, 4
B. 15, 13 , 4
C. 12, 12, 8
D. 16, 12, 4

15. Which of the following is not true about Static RAM (SRAM)
A. Expensive than DRA
B. Uses flip-flops to store bits
C. Need refreshing circuit
D. Need constant power supply
E. Faster than DRAM

16. One of the following is not a function of an I/O module

A. Data buffering
B. Error detection
C. Data transfer to/from the environment
D. Data transfer to/from the processor

17. Which of the following is true about Direct Memory Access I/O Operation.
A. CPU controlled all the data transfer activity
B. CPU should check device status periodically
C. DMA controller deals with the transfer
D. I/O module interrupts the CPU when ready

April, 2023
 Computer Architecture and Organization Model Questions

18. One of the following is not an input for control unit of a processor.
A. Clock
B. Flags
C. Control signals within the CPU
D. Instruction Register

19. Which of the following is not true about Hardwired control unit implementation.
A. Difficult to design and test
B. Inflexible design
C. Mostly used by RISC processors.
D. Uses control memory to store microoperations.

20. One of the following is not true about vertical microinstructions.

A. There is one bit for each internal processor control line and for each system bus
control line.
B. They need additional logic to decode micro-instructions.
C. They are more compact (fewer-bit) than the horizontal microinstruction.
D. Slower than horizontal microinstructions.

April, 2023