Modularización en VHDL

Arquitectura del Computador 2017

Modularización VHDL (entity)
library ieee;
use ieee.std_logic_1164.all;

library work;
use work.components.all;

entity fetch is
port(Jump, PCSrc, PCJmp, clk: in std_logic;
PcBranch: in std_logic_vector(31 downto 0);
Instr, PCPLus4: out std_logic_vector(31 downto 0));

end entity;
Modularización VHDL (architecture)
architecture my_arch of fetch is

--mux2_0 to mux2_1
signal PCNext: std_logic_vector (31 downto 0);

--PCPlus4
signal PCPlus4_s: std_logic_vector (31 downto 0);

--mux2_1 out
signal PC1: std_logic_vector (31 downto 0);

--flopr_0 out
signal pc_out: std_logic_vector(31 downto 0);

begin
...
Modularización VHDL (architecture cont.)
begin

mux2_0: mux2 generic map (width => 32)

port map( d0 => PCPlus4_s,
d1 => PCBranch,
s => PCSrc,
y => PCNext);

mux2_1: mux2 generic map (width => 32)

port map( d0 => PCNext,
d1 => PCJump,
s => Jump,
y => PC1);

flopr_0: flopr generic map (width => 32)

port map( d => PC1,
reset => reset,
clk => clk,
q => pc_out);
...
Modularización VHDL (architecture cont.)
...

adder_0: adder port map ( a => pc_out,

b => x”00000004”,
y => PCPlus4_s );

imem_0: imem port map (

A => pc_out(7 downto 2),
Data => Instr );

PCPLus4 <= PCPLus4_s;

end architecture;