Professional Documents
Culture Documents
OEC Workstation
Functional Block 1 –Workstation Overview (1 of 6)........................................................................................................................................... 4
Functional Block 2 – Workstation Overview (2 of 6).......................................................................................................................................... 5
Functional Block 3 – Workstation Overview (3 of 6).......................................................................................................................................... 6
Functional Block 4 – Workstation Overview (4 of 6).......................................................................................................................................... 7
Functional Block 5 – Workstation Overview CPP (5 of 6) ................................................................................................................................. 8
Functional Block 6 – Workstation Overview Cine Options (6 of 6) .................................................................................................................. 9
Functional Block 7 – Workstation Power Distribution (1 of 17)...................................................................................................................... 10
Functional Block 8 – System Power Distribution Incoming AC Power (2 of 17) .......................................................................................... 11
Functional Block 9 – System Power Distribution Incoming AC Power (3 of 17) .......................................................................................... 12
Functional Block 10 – Power Control PCB Power Distribution (4 of 17) ....................................................................................................... 13
Functional Block 11 – Power Control PCB Bad Line Voltage Sensing (5 of 17) ........................................................................................... 14
Functional Block 12 – Key Power Control (6 of 17) ......................................................................................................................................... 15
Functional Block 13 – Workstation AC Power Distribution (7 of 17) ............................................................................................................. 16
Functional Block 14 – Workstation DC Distribution (8 of 17) ......................................................................................................................... 17
Functional Block 15 – Cine 4 Power Distribution (9 of 17).............................................................................................................................. 18
Functional Block 16 – Control Panel Processor Touch Screen DC Power Distribution (10 of 17) ............................................................. 19
Functional Block 17 – Floppy & Jaz Drives DC Power Distribution (11 of 17) .............................................................................................. 20
Functional Block 18 – IDE Hard Drive, Cine 2 Disk Backplane DC Power Distribution (12 of 17) .............................................................. 21
Functional Block 19 – System Interface, External Interface DC Power Distribution (13 of 17) ................................................................... 22
Functional Block 20 – Image Processor, Video Controller DC Power Distribution (14 of 17) ..................................................................... 23
Functional Block 21 – Display Controller, Cine Bridge DC Power Distribution (15 of 17)........................................................................... 24
Functional Block 22 – Host CPU DC Power Distribution (16 of 17)................................................................................................................ 25
Functional Block 23 – Passive Backplane DC Power Distribution (17 of 17)................................................................................................ 26
Functional Block 24 – ARCNET Communications (1 of 4) .............................................................................................................................. 27
Functional Block 25 – ARCNET Communications (2 of 4) .............................................................................................................................. 28
Functional Block 26 – ARCNET Communications Fluoro Functions Waveforms (3 of 4) ........................................................................... 29
Functional Block 27 – ARCNET Communications X-ray Controller Waveforms (4 of 4) ............................................................................. 30
Functional Block 28 – Single Board Computer Connections / Jumpers (1 of 1) .......................................................................................... 31
1
Contents
Functional Block Diagrams Released 11/00
3
Contents
Functional Block Diagrams Released 11/00
Serial Comm. to
Lenzar Camera
Control Panel Video LEFT
Control VCR or RIGHT
and Monitors from MONITOR
Codonics Printer MONITOR
ARCNET 2A CCD
from C-Arm
Image Processor PCB
Vert. & Hor. Image Reversal
Interlace Video
Host Pentium
ISA Bus Processor PCI Bus 0
SCSI Controller
Card
2
VGA
Card Ethernet Card
for DICOM Jazz Drive
IDE Hard 1.44 Meg
Option
Drive Floppy
1 To CINE Option
3B
External Interface PCB
External ARCNET Port Diagnostics Early System Configuration
g
Room Interface Circuit
Power Injector Control Circuit
9800
1 2.1 Gigabyte or larger Hard Drive GE OEC Training Page 1 of 6
DOS readable C: Partition: 2.05 Gigabytes for image storage and data storage 11/00
WSOV.DSF
Non DOS partition: 50 Megabytes for operating system and application software
2 SCSI Controller Card is located on PCI Bus 1 3 Early systems may have a Display Controller PCB installed Workstation System Overview
if CINE Option is installed. See page 3 of 6 which is functionally the same as the Display Adapter PCB
4
Contents
Functional Block Diagrams Released 11/00
LEFT RIGHT
IR Data to Control Panel Processor PCB
MONITOR MONITOR
Q W E R T Y U I O P ~
Tab
'
A S D F G H J K L
Caps Lock ¸/ Æ Enter
æ
Del
g
Serial Comm. from
System Interface PCB 9800
1A GE OEC Training Page 2 of 6
WSOV.DSF 11/00
CINE Disk 1 CINE Disk 2 CINE Disk 3 CINE Disk 4 CINE Disk 5 CINE Disk 6
Disk Status
2
Jazz Drive
1B
g
1 SCSI Controller Card is located on PCI Bus 0
if CINE Option is not installed. See page 1 of 6.
9800
GE OEC Training Page 3 of 6
2 The CINE 2 or CINE 4 Disk Backplane WSOV.DSF 11/00
will be connected to the CINE Bridge PCB
depending on system configuration. Workstation System Overview
Cine Options
6
Contents
Functional Block Diagrams Released 11/00
Serial Comm. to
Control Panel Lenzar Camera
and Monitors Control Video or LEFT RIGHT
VCR
from Codonics Printer MONITOR MONITOR
ARCNET 5A CCD
from C-Arm
Image Processor PCB
Vert. & Hor. Image Reversal
Interlace Video
Passive Backplane
Host Pentium
ISA Bus Single Board Computer
PCI Bus 0
SCSI Controller
W/ VGA Driver Card
2
Ethernet Card
IDE Hard 1.44 Meg for DICOM Jazz Drive
Drive Floppy Option
1
To CINE Option
6B
External Interface PCB
External ARCNET Port Diagnostics Current System Configuration
g
Room Interface Circuit
Power Injector Control Circuit
9800
Page 4 of 6
1 2.1 Gigabyte or larger Hard Drive GE OEC Training
DOS readable C: Partition: 2.05 Gigabytes for image storage and data storage
WSOV.DSF 11/00
Non DOS partition: 50 Megabytes for operating system and application software
7
Contents
Functional Block Diagrams Released 11/00
LEFT RIGHT
MONITOR
IR Data to Control Panel Processor PCB
MONITOR
Q W E R T Y U I O P ~
Tab
'
A S D F G H J K L
Caps Lock ¸/ Æ Enter
æ
Del
g
Serial Comm. from
System Interface PCB 9800
4A GE OEC Training Page 5 of 6
WSOV.DSF 11/00
Workstation System Overview
Control Panel Processor
8
Contents
Functional Block Diagrams Released 11/00
Jazz Drive
4B
g
9800
1 SCSI Controller Card is located on PCI Bus 0 GE OEC Training Page 6 of 6
if CINE Option is not installed. See page 4 of 6.
WSOV.DSF 11/00
9
Contents
Functional Block Diagrams Released 11/00
System Power Distribution Key Power Control Floppy, CDR, Jazz, & Display Adapter,
Incoming AC Power Mag. Opt. Drives CINE Bridge
(115 VAC) Power Control PCB DC Power Distribution DC Power Distribution
Page 3
g
Power Control PCB Control Panel Processor / 9800
Bad Line Voltage Sensing Touch Screen
GE OEC Training 1 of 17
DC Power Distribution
Power Control PCB WSPD.DSF 11/00
Page 10
Page 5 Workstation Power Distribution
Functional Diagram Map
10
Contents
Functional Block Diagrams Released 11/00
Surge Suppressor K1
00-876784
6 5
+24 Volt
CB2 (10A) Power 7
RESET ONLY Supply 4
CB1 (20A) 3
RESET ONLY 1 2
Voltage 2
1 2 3 4 Detector 1
5
8
3 4 Range Overvoltage Power
Switch Lockout Control
Relay PCB
Overvoltage
T1 - Isolation Transformer
J1 Lockout 2 125
TB1 AC1
Comparitor J2 CB4 (5A)
113 230
RESET ONLY
1-2 1 1 101 P1 VAC
AC1_T1
CT 4
3-4 3 2 6
3
RT2 RT4 0 AC2_T1
RV4 6
5-6 5 4 4A
125 E4 E4 2
E1 RV3 AC2 E7 5
9 113 5B
5
RV1 RV2 101 AC_T1
AC 1
6 RT1 RT3
6 4
DS1 RTN_T1
91-128 VAC E2 0 RTN 3
1 E1
Configuration 8 E8 SHLD
CB3 (10A) 115
6
RESET ONLY VAC
E19
g
1 DS1 turns on when the system is connected to facility power. 3 230 VAC 9800
GE OEC Training 2 of 17
4 115 VAC
2 Strap T1 to match facility AC as follows: WSPD.DSF 11/00
Input VAC 91-98 98-104 104-110 110-116 116-122 122-128 5 K1 will not energize if
T1 Taps 101/6 101/0 113/6 113/0 125/6 125/0 the line voltage is System Power Distribution
excessively high. Incoming AC Power (115 VAC)
11
Contents
Functional Block Diagrams Released 11/00
Surge Suppressor K1
00-876784 6 5
+24 Volt
Power 7
Supply 4
3
Voltage 2
Detector 1 5
8 Power
Range Overvoltage
Switch Control
Lockout
Relay PCB
Overvoltage
T1 - Isolation Transformer
CB1 (10A) 2
TB1 J1 Lockout 125
RESET ONLY J2 AC1 CB4 (5A) 230
Comparator
113 VAC
1 2 RESET ONLY P1
1-2 1 1 101
AC1_T1
3 4 CT 4
3-4 3 2 6
3 AC2_T1
RT2 RT4 0
RV4 6
5-6 5 4 4A
125 E4 E4 2
E1 RV3 AC2 E7 5
9 5 113 5B
RV1 RV2 101 AC_T1
AC 1
6 RT1 RT3
DS1 6 4 RTN_T1
E2 0 RTN 3
182-256 VAC 1 E1
SHLD 115
8 E8 CB3 (10A)
Configuration 6 VAC
RESET ONLY
E19
g
1 DS1 turns on when the system is connected to facility power. 3 230 VAC 9800
GE OEC Training 3 of 17
4 115 VAC
2 Strap T1 to match facility AC as follows: WSPD.DSF 11/00
Input VAC 182-196 196-208 208-220 220-232 232-244 244-256
T1 Taps 101/6 101/0 113/6 113/0 125/6 125/0 5 K1 will not energize if System Power Distribution
the line voltage is
excessively high.
Incoming AC Power (230 VAC)
12
Contents
Functional Block Diagrams Released 11/00
g
1 From Bad Line Voltage Alarm Circuit. 9800
If the bad line voltage alarm is activated, 4 of 17
U2 pins 12 &13 will not go low, GE OEC Training
preventing AC power from going to the generator WSPD.DSF 11/00
13
Contents
Functional Block Diagrams Released 11/00
K1 P4
P1 7
6 AC1_CART
AC1_T1 5 1
2B 4
2 AC2_CART 7E
AC2_T1 3 4
4
6
3B 8
2
2 6F
1
K5
1
7
6
6C 5
2
3
+12V 4
Voltage Sensing Network 8
P3
DS3 DS2 DS1 *RELAY_ON 12V_KEY
1 6D
LINE HIGH LINE LOW PWR OK 1
Q1 2
g
1 To Delay Circuit U2. 9800
If the bad line voltage alarm is activated, 5 of 17
GE OEC Training
AC power is prevented from going to the generator
WSPD.DSF 11/00
Functional Block 11 – Power Control PCB Bad Line Voltage Sensing (5 of 17)
14
Contents
Functional Block Diagrams Released 11/00
3 See AC Power to
Power Motor Relay PCB
Page 4 of 6
3
1 If relay K5 is energized by the Voltage Sensing Network,
g
Delay circuit U2 pin 14 disables AC Power to the C-Arm
6 5
9800
2 Relay K1 shown in the de-energized condition.
GE OEC Training 6 of 17
4 WSPD.DSF 11/00
3 Wire connections on the back of SW1:
Pin 3 White Pin 6 Black
Pin 5 Green Pin 4 Red
Key Power Control
Rear View
15
Contents
Functional Block Diagrams Released 11/00
CINE CINE
+VE
FAN 2 FAN 1
-VE
TB5
6
9A
5
4
3 2 1
3
3
2
1
SK1
1 PS2
3 2 1
12345678
Voltage Adjustment
2
+VE
-VE
8B
6
TB3
5
4 3
3 2 1
2
SK1
1
1 PS1
3 2
Voltage Adjustment
12345678
1
2
LF1
0 0 0 0 0 0
HOURS 1/10
TB2
TB4
Power 3 P101 Fan B4 Fan B5
Control 2 AC1 4 LEFT
PCB 1 3 3 MONITOR
P4 AC2 1
6 9 5
AC1_CART
1 7 8
5E
AC2_CART 8
4 1 7
Fan B2 Fan B3 6
2 5
5 P101
4 2 RIGHT
1 3 MONITOR
1
Lenzar Hardcopy Camera
5
connects to TB2 Codonics Printer
connects to TB4
g
9800
With Arches option TB2 will have these additional power connections: GE OEC Training 7 of 17
1
Tracker Computer Enclosure power to the attaches to TB2 pins 8 & 2. WSPD.DSF 11/00
Power Supply PS3 for Flat Panel Display attaches to TB2 pins 1 & 7.
Power Supply PS4 inside of Arches enclosure attaches to TB2 pins 8 & 2.
Ground connections to these power supplies are all attached to Ground connection E6 (not shown). Workstation AC Power Distribution
16
Contents
Functional Block Diagrams Released 11/00
TP3
DC Distribution PCB
VR1 +3.3V
A 3.15 A
+3.3V
DS1 P1 10C
F6
P4 TP2
+5V 5A
1 5A P2
7B F5 11D
+VE
+5V 2 DS4 F4
3 TP1
PS1 GND 5A
10 5A P3 12E
F8
Com
-VE
11 F7
12
SK3 - 7 13 C 6.3 A
Power Fail (NC) TP5 1A F1 P5
6 5 4 3 2 1
(NC) 6
-12V F3
13F
SK2 -12V DS2 B
Com 14
Com 15 C
TP4
+12V 10 A
+12V
7 P7
F2
DS3 A 14H
B
DS14 DS15
P8
B 15G
A
10 A B
U1
DS5 DS6 DS7 DS8 Power F9 P9
Monitor SYSRST* 16I
5A
F10 17J
DS1 +3.3V from PS1 / VR1
DS2 -12V from PS1 DS10 DS11 DS12 DS13
g
DS3 +12V from PS1
DS4 +5V from PS1 9800
GE OEC Training 8 of 17
DS5 sensed +5V from Vid. Cont. DS10 sensed +5V from Disp. Adapter DS14 sensed +5V from CPP WSPD.DSF 11/00
DS6 sensed +3.3V from Vid. Cont. DS11 sensed +3.3V from Disp. Adapter DS15 sensed +12V from CPP
DS7 sensed +5V from IP DS12 sensed +3.3V from Cine Bridge
DS8 sensed +3.3V from IP DS13 sensed +5V from Cine Bridge Workstation DC Distribution
17
Contents
Functional Block Diagrams Released 11/00
Cable Assy
CINE 4 Disk Backplane
00-879466
P3 TP3
10 Amp +5V
7A 1
+VE
+5V P3 CINE Drive 3
F1 2
3
PS2 4 TP5
Com
-VE
P5 CINE Drive 5
(NC)
SK2 -12V
Com TP1, 2, 4, 6, & 7
P6
Com 9 GND CINE Drive 6
+12V 10
11
12
13
14
15
16
g
9800
GE OEC Training 9 of 17
WSPD.DSF 11/00
18
Contents
Functional Block Diagrams Released 11/00
EMI Box
Cable Assy
00-879475 J1
+5V
DC Distribution PCB 1
Cable Assy Right Monitor
00-879428 J1
EMI +12V Touch Screen
8C J1
9
3.15 A 1 11
F6 GND
6
1A 3 12
F3
4 30
19
17
Control Panel Processor PCB
18 J1
TP14
+5V
+5V
35 2
5 TP4
+12V
+12V
4
GND
+5V RTN
3
GND TP1, 10, 8, 13
+12V RTN
5
P3
1
3
P1 4
TP5
IR Reciever PCB
g
4
TP4 1
6
9800
GE OEC Training 10 of 17
WSPD.DSF 11/00
Functional Block 16 – Control Panel Processor Touch Screen DC Power Distribution (10 of 17)
19
Contents
Functional Block Diagrams Released 11/00
Cable Assy
00-879430 J1 3.5" Floppy Disk Drive
+5V
DC Distribution PCB 1
+12V 4
8D
J1
GND 2
5A 1
F5 GND
3
1A 3
F4
6
7
J1 Jazz Drive
2
+5V
4
4
+12V
1
8
GND
2
9 GND
3
g
9800
GE OEC Training 11 of 17
WSPD.DSF 11/00
Functional Block 17 – Floppy & Jaz Drives DC Power Distribution (11 of 17)
20
Contents
Functional Block Diagrams Released 11/00
Cable Assy
00-879427 J1 IDE
+5V Hard Disk Drive
DC Distribution PCB 4
+12V
1
8E J3
GND
2
5A 1
F8 GND
3
5A 4
F7
7
8
J3 CINE Disk 2 Backplane
2 TP1
+5V
1
3 J1 CINE Drive 1
+5V
2
5 TP2
+12V
3
6 J2 CINE Drive 2
+12V TP3, 4, 5
4
9 GND
5
10 GND
6
11
GND
7
12
GND
8
g
9800
GE OEC Training 12 of 17
WSPD.DSF 11/00
Functional Block 18 – IDE Hard Drive, Cine 2 Disk Backplane DC Power Distribution (12 of 17)
21
Contents
Functional Block Diagrams Released 11/00
23 23 12 12 10
TP11, 3, 34, 23
GND
1 1 14 14 15
31 31
32 32
33 33 TP35
+12VMB
15J 14J
34 34
TP27 1 Room Interface
ADC
SENSED VOLTAGES +5VMB
SEE WORKSTATION 2 External Arcnet
TP7
DC DISTRIBUTION 3
-12VMB
3 See System Interface I/O
A/D Sense page 7 of 10
g
SLOT 2
9800
HOST PENTIUM CPU or 13 of 17
GE OEC Training
PASSIVE BACKPLANE
WSPD.DSF 11/00
16A See Host CPU DC Power Distribution
System Interface, External Interface
17A See Host CPU DC Power Distribution DC Power Distribution
Functional Block 19 – System Interface, External Interface DC Power Distribution (13 of 17)
22
Contents
Functional Block Diagrams Released 11/00
Cable Assy
Video Controller PCB
DC Distribution PCB J7 00-879429-01 P7 TP20 TP74
10 A +5V +5VMB
+5V 1 2 ISA +5V
F2 TP58
2 6
TP3 TP22 +5V Analog U60
7805 ISA +12V
+3.3V +3.3V
3 3
4 7 TP59
TP1 TP11
-5V Analog U62
GND GND 7905 ISA -12V
14 5
15 8
SLOT 1
8H TP56
1 +5V SENSE
ISA Gnd
4 +3.3V SENSE ISA Gnd
HOST
P3 Image Processor PCB PENTIUM
TP1 U56
SLOT 6
10 2 +5V CPU
11 6 3.3V
TP2 or
+3.3V PASSIVE
12 3
13 7 BACKPLANE
TP7 TP11
GND PCI +5V
17 5 PCI +5V
18 8
PCI +3.3V
PCI +3.3V
1 +5V SENSE
13J
4 +3.3V SENSE PCI Gnd
PCI Gnd
SENSED VOLTAGES
SEE WORKSTATION
DC DISTRIBUTION
16A
17A
g
9800
GE OEC Training 14 of 17
WSPD.DSF 11/00
Functional Block 20 – Image Processor, Video Controller DC Power Distribution (14 of 17)
23
Contents
Functional Block Diagrams Released 11/00
Cable Assy
P2
Display Adapter PCB
DC Distribution PCB J8 00-879429-02
TP23
6.3 A +5V SENSE +5V
+5V 1 2 PCI +5V
F1 2 U33
TP3 6 +3.3V SENSE
3.3V PCI 3.3V
+3.3V and
3 3 1 TP46
4 7 2.5V
TP1 +12V
PCI +12V
GND TP45
14 5
15 8 -12V
PCI -12V
SLOT 5
8G TP15
1 GND
4 PCI Gnd
HOST
PENTIUM
P3 CINE Bridge PCB TP19 CPU
TP2 TP3 PCI +5V IO
10 2 U1 or
VCC 3.3V TP10
11 6 3.3V PASSIVE
PCI +5V
TP18
U48 BACKPLANE
12 3 +3.3V 3.3V
SLOT 7
13 7
TP7
GND
17 5 TP20
18 8 +3.3V
PCI +3.3V
TP21
1 +5V SENSE PCI +12V
13J TP17
4 +3.3V SENSE PCI -12V
SENSED VOLTAGES PCI Gnd
PCI Gnd
SEE WORKSTATION
DC DISTRIBUTION
16A
17A
g
1 The Display Controller PCB uses a 3.3 volt regulator only. 9800
The Display Adapter PCB can ues a 3.3volt and a 2.5 Volt regulator.
The 2.5 volt regulator voltage is not sensed by the System Interface PCB. GE OEC Training 15 of 17
WSPD.DSF 11/00
Functional Block 21 – Display Controller, Cine Bridge DC Power Distribution (15 of 17)
24
Contents
Functional Block Diagrams Released 11/00
ISA BUS
PCI BUS 0
J1
+5V
1 2
TP5 +12V
5 3 1.44 Meg
-12V -12V
7 4 Floppy
GND HOST
9 5
GND
U1 10 6 PENTIUM
8 RESET* 1
Power CPU
Monitor
J2
10 A +5V
+5V 2 4 IDE Hard
F9 +5V Drive
3 5
+5V
8I 4 6
GND
11 1 13A 14A
GND
12 2
g
9800
GE OEC Training 16 of 17
WSPD.DSF 11/00
Host CPU
DC Power Distribution
ISA BUS
PCI BUS 0
VIDEO CONTROLLER PCB SLOT 1
SLOT 5 DISPLAY CONTROLLER PCB
SYSTEM INTERFACE PCB SLOT 2 o
DC Distribution PCB
5A J9
+12V 6
F10
13
1
J1
+5V
1 2
TP5 +12V
5 3 1.44 Meg
-12V -12V
7 4 Floppy
GND PASSIVE
9 5
GND
U1 10 6 BACKPLANE
8 RESET* 1 1
Power 00-901697-01
Monitor
J2
10 A +5V
+5V 2 4 IDE Hard
F9 +5V Drive
3 5
+5V
8I 4 6
GND
11 1
GND 13A 14A
12 2
g
9800
GE OEC Training 17 of 17
1 See Single Board Computer Functional Diagram.
WSPD.DSF 11/00
Passive Backplane
DC Power Distribution
EMI Interconnect
SYSTEM INTERFACE PCB
R1 R2 BOX Cable
K1 00-879054
P4 150 P2 P4 K1 150 P3 J6 P6 J1
9 13 ARCNET_HI 13 9 ARCNET_HI
1 1 1 1 1 1 7
8 4 ARCNET_LO 4 8 ARCNET_LO
2 2 2 2 2 2 8
+12V INT_GOOD_HI 3
VCC 7 7
ISOLAT_RLY_CNTL BD4 3 INT_GOOD_LO
26 26 8 8 8
CONFIG 0 4
9 22 22 DIAGNOSTIC LEDS
U7 U37 5 6 P2
DIAG_RXD 6 1 20 DS1 DS2
7 20 20 BD(7..0) POWER
DIAG_TXD 7 4 18
6 19 19 CONTROL
P1 U1 U2 1
2 P11
STATUS PCB
RS485 PENTIUM
EXTERNAL TRANSCEIVER ARCNET LEDS 0 0 00-880315
P12
INTERFACE PCB CONTROLLER
U46
00-879184 U32
U36 U43 8 19 MOD_TXD
U20 18 12 24 3
6 1 20
DATA(15..0) 17 14 6 22 21 MOD_RXD MODEM
7 4 18 2
11 9 2 5
REAR RS485 DIAGNOSTIC 7 13 3 4
PANEL TRANSCEIVER ARCNET DIAGNOSTIC
CONTROLLER PROCESSOR U16
MC68HC16Z1
DIAG_RXD
Laptop
DIAG_TXD
running WORKSTATION
RUT REMOTE DIAGNOSTICS NODE
SLOT 2
g
See Power Control PCB Power Distribution
1 9800
Page 4 of 16
2 See Workstation Remote Diagnostics Interface Page 8 of 11 GE OEC Training Page 1 of 4
ARC_NET.DSF 11/00
3 Shown in Workstation Standalone condition. Activated by CNCT_ON circuit.
See Power Control PCB Power Distribution Page 4 of 16. Arcnet Communications
Diagnostic Processor U43 monitors the CONFIG 0 line and activates Relay K1 on the External Interface PCB
4
using the BD4 line when an external ARCNET cable is attached.
Functional Diagram
A3
FLUORO FUNCTIONS PCB U57 P1
P1
00-879099
RS485 TP5 1
TP6 TRANSCEIVER
TP7 24 ARC_INT*
U36
6 DIAGNOSTIC LEDS
17
7 DS1 DS2
18 1
DATA(15..0)
TP4
J2 U10 U5
P1
Y2 U58
ARCNET_HI MICRO
7 6 20 U1 U2 PROCESSOR
TP44 STATUS
MHz MC68HC16Z1
8
ARCNET_LO
2
ARCNET LEDS 5 0
CONTROLLER
INTERCONNECT
CABLE XRAY CONTROLLER PCB
A2 00-879803
P1 RS485 U21
TRANSCEIVER TP15
TP35 TP37 U25
24 INT_*ARC
6 D(31..16)
17 SD(15..0) 486
7
18
TP18 SD BUFFER MICRO
U55 U30
PROCESSOR
Y1 U5 U6
STATUS
20
TP39 0 0 LEDS
DIAGNOSTIC
MHz LEDS
ARCNET
CONTROLLER DS 1-5
g
C-ARM 00-879362
ON THIS PCB
9800
GE OEC Training Page 2 of 4
1 See Control Panel & Fluoro Functions Communications Diagram Page 3 of 3 ARC_NET.DSF 11/00
Arcnet Communications
Functional Diagram
28
Contents
Functional Block Diagrams Released 11/00
TP5 TP44
Fluoro Functions PCB
TP5
GND
ARC_INT*
Y2 2 V/div dc
TP6 TP4
2 ms/div
1
TP7
TP5
ARC_INT*
2 V/div dc
U2
0
5 s/div
4 2
U1
5 TP6
ARCNET_LO
DS2 1 V/div dc
2 us/div
DS1
3
TP7
ARCNET_HI
1 V/div dc
2 us/div
g
1 Active condition, buttons pressed on Control Panel.
9800
2 Idle condition, no buttons pressed on Control Panel. GE OEC Training Page 3 of 4
3 Segment 6 on DS1 blinks at 1Hz rate when Fluoro Functions Micro Controller is running. ARC_NET.DSF 11/00
4 The code displayed on U1-U2 is OE when ARCNET communication is lost. Arcnet Communications
Fluoro Functions Waveforms
29
Contents
Functional Block Diagrams Released 11/00
DS1 TP15
TP37 TP35 INT_ARC*
TP39 2 V/div dc
DS2
200 Ms/div
GND 2
DS3
DS4 TP37
ARCNET_LO
1 V/div dc
DS5
2 us/div
U5
3
0
U6
0
TP15 TP35
ARCNET_HI
1 V/div dc
2 us/div
g
2 ARCNET failed condition.
9800
3 The code displayed on U5-U6 is 00 representing normal operation. GE OEC Training Page 4 of 4
ARC_NET.DSF 11/00
Arcnet Communications
X-Ray Controller Waveforms
30
Contents
Functional Block Diagrams Released 11/00
J12 J14
Com 1 Key board
P8 Power P1 Com Port VGA Port J16
RS232
J15
LPT1 J9 J10 J13
J7 J11
Parallel Port J9 KB Service
28 27
Ctrl Monitor
JPW1 JPW2
26 25 JPW3
24 23
JPW4
JPW1 JPW2
22 21 JPW3
JPW4
20 19
Floppy Drive
18 17
16 15
14 13
BIOS
12 11 J5 J7
10 9
8 7
6 5
4 4 Service Keyboard
Rear Panel
Rear Panel
4 3 J6 CPU fan power
2 1
1 1
JP5
J18
Primary IDE
Secondary IDE
Bat1
J19
J20
J19
J20
1.44 Meg
J3 J4
Floppy
JP5
J18
123
IDE Hard JP6
Drive Socket 7
1
233 mHz MMX
Processor
JP6
SW3
open
1 2 3 4
SW3 1 2 3 4
SW1
ON
ON
1 2 3 4
SW1
BZ1
1 2 3 4
g
ON
ON
g
9800
GE OEC Training Page 1 of 15
WSSCOM.DSF 11/00
Workstation Communications
Functional Diagram Map
32
Contents
Functional Block Diagrams Released 11/00
U1 U10 U4
Static Boot Add. Decode 4A
Ram Prom PAL
g
1 Resets Watchdog timer every 3 ms.
9800
2 TP12 is High under nornal conditions. GE OEC Training Page 2 of 15
TP12 will go Low causing U5 to be reset if VCC drops below 4.65 volts, WSSCOM.DSF 11/00
or if the watchdog timer reset pulses are lost.
Workstation Control Panel
Processor Reset & Bootup
Functional Block 30 – Workstation Control Panel Processor Reset and Boot-up (2 of 15)
33
Contents
Functional Block Diagrams Released 11/00
ASSY 00-876613
U1
TP1 CONTROL PANEL PROCESSOR P1
U2
U4 TP4
1
U5
Y1 U11 U13 TP8
U10 U14
6
DS1 DIAGNOSTIC LED TP11
TP10 TP12
6
U24 P7
TP13 TP14
U24-6
2 V/div dc
1 ms/div
g
9800
GE OEC Training Page 3 of 15
WSSCOM.DSF 11/00
34
Contents
Functional Block Diagrams Released 11/00
Control Panel 2 3 1
Processor PCB DIAG_DISPLAY_WR U20, U21
00-876611 DIAGNOSTIC 10
LED / 1 2 10
LATCH DS1 DIAGNOSTIC LED
AUTO
VCC CONTRAST
CR1
U5 P4
80C196KC LED_WR
U16 10 AUTO
Micro
Controller 19 11
CONTROL PANEL
LED LATCH
COL_READ
U15, U23
KEY BOARD
INPUT LATCH EDGE NOISE
CONTRAST BRIGHTNESS PATIENT IMAGE IMAGE SPECIAL
(COLUMN READ)
ENHANCE FILTER
INFORMATION DIRECTORY ANNOTATION APPLICATIONS CUSTOMIZE HELP
2A ZOOM NEGATE
U4
AUTO
g
1 Segment 10 blinks ON & OFF indicating that the Micro Controller (U5) is running.
9800
2 Segment 1 lights when buttons on the ICON keyboard are pressed. GE OEC Training Page 4 of 15
WSSCOM.DSF 11/00
3 Segment 2 lights when buttons on the TEXT keyboard are pressed.
Workstation Control Panel
Key Board Interface
35
Contents
Functional Block Diagrams Released 11/00
TP5
500 mV/div dc
5 ms/div
g
9800
1 Segment 5 indicates IR data is being received. GE OEC Training Page 5 of 15
U34
U5 U7 U26
Quad UART
80C196KC E5 MAX233 MAX233
TP2 J2 J1 P1 P6 (RS232)
Line Driver 5 Line Driver 2
44 3 4
CTS 8 6 6 1 35 CP_CTS
E3
TP7
17 20 19 18 1
RXD 10 26 26 2 43 CP_RXD
E2
TP6
1 18 19 20
TXD 18 6 7 7 4 44 CP_TXD
E4
TP3
RTS 39 2 5 4 3
4 25 25 3 33 CP_RTS
See
Workstation System Interface
1 2 Communications Overview 1
7 8 Electronics Box
DS1 DIAGNOSTIC LED
g
9800
GE OEC Training Page 6 of 15
WSSCOM.DSF 11/00
1 Segment 7 indicates Serial Data is being received from the System Interface PCB. Workstation Control Panel
2 Segment 8 indicates Serial Data is being sent to the System Interface PCB. Communication to System Interface
37
Contents
Functional Block Diagrams Released 11/00
7 8
DS1 DIAGNOSTIC LED
TP7
2 V/div dc
10 ms/div
TP6
2 V/div dc
10 ms/div
g
9800
1 Segment 7 indicates Serial Data is being received from the System Interface PCB. Page 7 of 15
GE OEC Training
2 Segment 8 indicates Serial Data is being sent to the System Interface PCB. WSSCOM.DSF 11/00
38
Contents
Functional Block Diagrams Released 11/00
See
System Interface PCB
Workstation System Interface
00-879054 Communications Overview 1
U18 U26 P2
U34
Quad UART 74LS244 MAX233
Buffer Line Driver 2
(RS232) P6 J1 P1 RIGHT
Right_RXD 1
MONITOR
TXD 6 23 23
Left_RXD 6
10 21 21
2
Right_TXD
RXD 7 4 4
Left_TXD
11 2 2
TP5
1 R_MON_ON
9 22 22 P2
TP6 2
1 L_MON_ON LEFT
13 1 1
1 MONITOR
6
2
Electronics Box
1 TP5, TP6
g
Monitor ON = +5 Volts
9800
2 Monitor failed = 0 Volts
GE OEC Training Page 8 of 15
2 P2-6
WSSCOM.DSF 11/00
Monitor ON = +11 Volts
Monitor failed = 0 Volts Workstation System Interface
Monitor Serial Communications
Back of Monitor
Video
BNC
Connector
P2-2
5 V/div dc
500 us/div
1
P2
P2-1 6 5 4
5 V/div dc 2
500 us/div
3 2 1
3
g
1 Serial communications are present only while adjusting monitor
9800
sizing or brightness and contrast adjustments using the RUT utility. GE OEC Training Page 9 of 15
2 P2-6 is +11 volts while monitor is in the ON condition. WSSCOM.DSF 11/00
40
Contents
Functional Block Diagrams Released 11/00
U34 U23
Quad UART MAX233
P6 J1 P1
(RS232) Line Driver
20 1 18 TS_RXD
TXDA 14 28 28
19 20 19 TS_TXD
RXDA 15 10 10
TS_RTN
16 29 29
P1 5 2 3
1
See
Workstation System Interface
Communications Overview 1 Right Monitor
Touch Screen
Electronics Box
g
9800
GE OEC Training Page 10 of 15
WSSCOM.DSF 11/00
Functional Block 38 – Workstation Touch Screen to System Interface Communication (10 of 15)
41
Contents
Functional Block Diagrams Released 11/00
1 Red +15Volts
2 Green TS_TXD
3 Blue TS_RXD P1-2
5 White TS_RTN 5 V/div dc
6 Black Ground 1 ms/div
9 Yellow +12 Volts
1 2 3 4 5
6 7 8 9
P1-3
5 V/div dc
1 ms/div
P1
1 2 3 4 5
6 7 8 9
Monitor
g
Rear View
9800
GE OEC Training Page 11 of 15
WSSCOM.DSF 11/00
Functional Block 39 – Workstation Touch Screen to System Interface Waveforms (11 of 15)
42
Contents
Functional Block Diagrams Released 11/00
P11 P1 P4
00-879471
DIAG_RXD 20 20 7
RUT Diagnostic Cable
1
DIAG_TXD 19 19 6
14C
Electronics Box
g
9800
GE OEC Training Page 12 of 15
WSSCOM.DSF 11/00
Workstation
Remote Diagnostics Interface
43
Contents
Functional Block Diagrams Released 11/00
U34
Quad UART U25
(RS232) MAX233 Spare
See Arcnet Communications
Functional Diagram
U26 To Control Panel
MAX233 see page 6 of 15 U7
RS485
Transceiver
U18 U24 To LMON & RMON
74LS244 MAX233 Sel 0
see page 8 of 15
Sel 1 U21 Ext. Relays
Sel 2 U28 Ext. Relays
CE U23 To Touch Screen U37 Sel 3 U38 Ext. Relays
Max233 see page 10 of 15 Pentium ArcnetCS Sel 4 U27 PCB Rev.ID
Controller Sel 5 U35 Config. Switch
Sel 6 U22 DS1 Diagnostics
1 Sel 7 U14 DS2 Diagnostics
Sel 8 U42 Voltage Sense
Host Buffered Data Bus Sel 9 U45 Temp Sense &
Amb. Light Sense
Sel 10 U44 Temp Sense &
Host Buffered Address Bus Voltage Sense
Sel 11 U30 VCR Control
Sel 12 U29 VCR Control
Sel 13 U4 Hex Diag. Display
U57 Sel 14 U34 Quad UART A
U56 U58 2 U59
A CS I/O Map Sel 15
Data Buffer Option Prom Address Buffer
OE Decoder B_RESET 14A
g
ISA Slot 2
9800
Host Pentium CPU GE OEC Training Page 13 of 15
WSSCOM.DSF 11/00
1 See System Interface I/O Map Select Lines Diagram
Pages 2 of 10, 4 of 10, 6 of 10, 7 of 10, 8 of 10, 9 of 10 Workstation System Interface
2 Option Prom U58 prevents access to DOS with a non OEC boot disk. Communications Overview 1
44
Contents
Functional Block Diagrams Released 11/00
U51, U50
U53 - U55 See Arcnet
AM29F010
74HC244 Communications
Diagnostic Address Bus Flash EPROM
Address Functional Diagram
Program / Boot
Buffer Prom
U40, U49
74HTC245 Diagnostic Data Bus P12
Data
Buffer U48, U47 1 MD_DCD
SRAM 2 MD_RXD
Modem Control Lines 3 MD_TXD
4 MD_DTR
U46
5 GROUND 15B
MOD_TXD MAX239
6 MD_DSR
Line Driver
U32 7 MD_RTS
74LS244 8 MD_CTS
MOD_RXD Buffer 9 MD_RI
U16 P11
MAX233 19 DIAG_TXD
System Interface PCB Line Driver 20 DIAG_RXD 12C
00-879054 21 DIAG_RTN
g
1 B_RESET is controlled by the Host Pentium Processor. 9800
GE OEC Training Page 14 of 15
2 WD_STRB resets the Watchdog timer as the Diagnostic Processor runs. WSSCOM.DSF 11/00
3 RESET* at TP25 is normally High. Diagnostic Processor U43 will be reset if VCC drops below 4.65 Volts, Workstation System Interface
WD_STRB signal is lost, or if the Host Pentium Processor issues a reset via B_RESET at TP15. Communications Overview 2
45
Contents
Functional Block Diagrams Released 11/00
Electronics Box
g
9800
1 Not currently installed. GE OEC Training Page 15 of 15
WSSCOM.DSF 11/00
Workstation Modem to
System Interface Communications
46
Contents
Functional Block Diagrams Released 11/00
g
9800
GE OEC Training Page 1 of 10
1 See Workstation System Interface Communications Overview1 Page 13 of 15
SIIOSELC.DSF 11/00
SEL 2 4 3A
12 SPARE3
1B C1 13 13 8
EN 14
15 ISOLAT_RLY_CNTL
11 26
16 5
17
U28 RELAY_+12V
18 10 2
LATCH 19
6 RELAY_GND
9 1
SEL 3 8
1C EN2 P6
5 X-RAY_LMP_RTN
EN1 4 7 12 19 3B
2
11
P5
13 RELAY_GND
U38 15 21
17 8 RELAY_GND 3C
LATCH 24
See Workstation System Interface +12V
Host Buffered Data Bus
Communications Overview1
Page 13 of 15
g
9800
GE OEC Training Page 2 of 10
SIIOSELC.DSF 11/00
48
Contents
Functional Block Diagrams Released 11/00
P4
ARCNET_HI_2
K1 1
P2 ARCNET_LO_2 2
P4 2
g
LAMP
+5V 18 9
9800
ELECTRONICS BOX 1 Room Interface GE OEC Training Page 3 of 10
2C P5 P5
DC DISTRIBUTION SIIOSELC.DSF 11/00
21 21 2 External Arcnet
PCB System Interface I/O
24 24
00-879119 External Relay Control 2
49
Contents
Functional Block Diagrams Released 11/00
+5 SEL 4
1D
VCC
R65 R5 1
10K 10K EN 2
19 EN 1
R48 75 8 12
R46 75 6 14
U27
R44 75 4 LATCH 16
R42 75 2 18
R49 75 11 9
R47 75 13 7
R45 75 15 5
R43 75 17 3
ASSEMBLY 1
I.D. RESISTORS SEL 5
1E
1 1
U15 EN 2
19 EN 1
4 5 8 12
3 6 6 U35 14
2 7 4 LATCH 16
1 8 2 18
2 B_CONFIG_3 11 9
5A
CONFIGURATION B_CONFIG_2 13 7
SWITCHES
B_CONFIG_1 15 5
B_CONFIG_0 17 3
SYSTEM INTERFACE PCB
See Workstation System Interface
00-879054 Communications Overview1 Host Buffered Data Bus
Page 13 of 15
g
1 Installed resistors indicate PCB revision level. 9800
GE OEC Training Page 4 of 10
SIIOSELC.DSF 11/00
2 All switches must be set to the OFF or OPEN position.
System Interface I/O
Config Switch & ID
50
Contents
Functional Block Diagrams Released 11/00
1 P4 P1 P11
CONFIG_3 R9 10K 13 U39 4
12 25 25 U43
CONFIG_2 R8 10K 11 Inverting 5 MCHC16Z1
11 24 24 Latch Diagnostic
CONFIG_1 R7 10K 9 6
10 23 23 Processor
CONFIG_0 R6 10K 5 7
9 22 22
B
I C
PA
LB R2 R3 R4 R5 +5V
AL 1K 1K 1K 1K VCC
NE
E
4A
EXTERNAL INTERFACE
SYSTEM INTERFACE
00-879184
00-879054
ELECTRONICS
BOX
g
9800
GE OEC Training Page 5 of 10
1 External Arcnet
SIIOSELC.DSF 11/00
51
Contents
Functional Block Diagrams Released 11/00
1 2
3 4
Host Buffered Data Bus
+5V
5 6 VCC
7 8
9 10
See E
Workstation System Interface 11 12
1
Communications Overview1 13 14
Page 13 of 15 15 1 16
17 18 DS2
19 20 10
9
SEL 7 8
1G C1
7
EN
6
5
4
U14 3
LATCH 2
1
g
9800
GE OEC Training Page 6 of 10
SIIOSELC.DSF 11/00
1 Function not implemented.
System Interface I/O
DS1, DS2 Diagnostic LEDs
Functional Block 49 – System Interface I/O DS1, DS2 Diagnostic LEDs (6 of 10)
52
Contents
Functional Block Diagrams Released 11/00
P5 R27 SEL 8
D 1H CLK 3.5854 MHZ
CINE_+5V_SEN 2 +5VREF
U42
CINE_+3.3V_SEN 3
VIDCNT_+5V_SEN 4 A/D
VIDCNT_+3.3V_SEN 5
1 DSPCNT_+5V_SEN 6 CONVERTER
DISPCNT_+3.3V_SEN 7
IP_+V5_SEN 8
IP_+3.3V_SEN 9
SEL 10
1J CLK 3.5854 MHZ
PCIDA_+5V_SEN 10 U44 +5VREF
CPP_+5V_SEN 11
-12V D D
SEL 9
TEMP_SEN_2_+ 19 1I CLK 3.5854 MHZ
1 U12
TEMP_SEN_2_- 20 +5VREF
+12VMB U45
VCC
VCC
-12V D A/D
+12V
X-RAY_LMP 18 +5VMB
1 CONVERTER
AMB_LIGHT_2 21
AMB_LIGHT_1 20
-12VMB
P6 U11
-12V
U11
g
D
D 9800
GE OEC Training Page 7 of 10
SYSTEM INTERFACE 00-879054
SIIOSELC.DSF 11/00
53
Contents
Functional Block Diagrams Released 11/00
SELECT 11 VCC
1K R7 TO/FROM
P12 J2 P2 VCR
C1 REWIND*
FFORWARD*
EN
U9 PLAY*
D
U30 PAUSE*
BUFFER RECORD*
LATCH SPARE*
STOP*
SPARE*
SHIELD
U8
SELECT 12 VCC
1L BUFFER D
VCC
EN FFORWARD_IN
EN REWIND_IN SONY
S VHS HI-FI
PAUSE_IN
U29 RECORD_IN EJECT REC
LATCH
PLAY_IN
U17
ELECTRONIC
See Workstation System Interface BOX
Host Buffered Data Bus
Communications Overview1
Page 13 of 15
SYSTEM INTERFACE 00-879054
g
9800
GE OEC Training Page 8 of 10
SIIOSELC.DSF 11/00
54
Contents
Functional Block Diagrams Released 11/00
SELECT 13
1M
U4
Host Buffered Data Bus LATCH
3
1
U2
3
SYSTEM INTERFACE
U1
00-879054 D
g
2 See Workstation System Interface Communications Overview 2 page 14 of 15 9800
GE OEC Training Page 9 of 10
SIIOSELC.DSF 11/00
3 00 code is displayed on U2, U1 during normal operation.
System Interface I/O
U1, U2 Diagnostic Display
55
Contents
Functional Block Diagrams Released 11/00
U57
HOST PENTIUM CPU
ISA SLOT 2
U34
Quad
Host Pentium Address Bus Address
UART
Decoder
1N 1
Sel 14 CS
Sel 15
3 U58
Option
Prom
CS 1
1O
OE
g
9800
GE OEC Training Page 10 of 10
SIIOSELC.DSF 11/00
1 See Workstation System Interface Communications Overview 1 page 13 of 15
System Interface I/O
Arcnet, Quad UART, Opt PROM
Functional Block 53 – System Interface I/O ARCNET, Quad UART, Option PROM (10 of 10)
56
Contents
Functional Block Diagrams Released 11/00
Image Path
Overview
Page 2
Image Path into Image Path out of Image Path in Image Path in
Video Controller PCB Video Controller PCB Display Adapter PCB Display Controller PCB
Page 3 Page 4 Page 5 Page 6
Image Path
Waveforms
Page 7
g
9800
GE OEC Training Page 1 of 7
IMAGEP.DSF 11/00
Image Path
Functional Diagram Map
57
Contents
Functional Block Diagrams Released 11/00
P5 LEFT RIGHT
J7
MONITOR MONITOR
Image
High Voltage & Processor
Control Cable Assy.
J3 P4
P3
J1 Interconnect P6
J3
Cable Assy.
13 8
2 4
1 3
Lemo Receptacle
Cable Assy. Interconnect
Plug Mux A/D
Video
Output J6
J5
g
STOP REW PLAY F FWD PAUSE
Video
Input 9800
VCR Page 2 of 7
GE OEC Training
IMAGEP.DSF 11/00
Image Path
Overview
58
Contents
Functional Block Diagrams Released 11/00
TP1 7A
P6 U14
Video_Lo MUX TP31 TP48
-
4 MUXVID VID
TP15 U5
IN0 U22
MAX452 +
Video_Hi IN1 HFA1103 4A
+ -
8 IN2 X2 Video
Video_Shld IN3 Separator
3 A0 A1 TP11
TP18
BP_CLAMP*
COMP_SYNC 4B
U17 U18
MAX9698 SYNCGEN1
7C Hi Res FPGA TP8
U16
P5 GS4881 Sync Stripper HSYNC*
+ TP16 4C
Sync Stripper
VCR U8 U6 VCR_HSYNC 2
Video MAX452 GS4581 TP7
U23 VSYNC*
-
DG411 VCR 4D
BP Sync Stripper
VIDSEL0
4E
TP2
Pilot Tone
U65 1
ISA Address Decoder
ISA D0 - D7
ISA Slot 1
Host Pentium CPU
g
9800
GE OEC Training Page 3 of 7
1 See Pilot Tone Functional Diagram page 1 of 1.
IMAGEP.DSF 11/00
2 See Frame Sync Functional Diagram page 1 of 2.
Image Path into
Video Controller PCB
59
Contents
Functional Block Diagrams Released 11/00
BP_CLAMP* 3B
Video Controller PCB
DC Restoration
Horizontal Clamp Circuits
HSYNC* 3C Anti-Vignetting U34, U59, U43
Circuit TP47
U23, U60, U54 AVIG
P3
Summing
To Image Processor
Amplifier
Vertical 1
U57 A/D Converter
VSYNC* 3D Anti-Vignetting AD_IN0 Pixel VC_D0
AD5800 to to
Circuit Interpolator
U42 AD_IN11 VC_D11
U23, 60, U55 U46
Shading
Corrected
Voltage Controlled
Video U33 TP43
Gain Amplifier IN0
VID 3A U32 +
IN1
IN2 -
Uncorrected Video IN3
A0 3E
U24
VCR
MAGSEL0 2 Anti Alias Filter TP51
U24 5 MHZ LP
MAGSEL1 TP50
-
U34
3 DG411 U41
MAX452
U65 TP52
Hi Res Video 3E
ISA Address Decoder
Anti Alias Filter
+ U56
25 MHZ LP
ISA D0 - D7 MAX452
ISA Slot 1
Host Pentium CPU
g
9800
1 Interpolates value of low scan VCR video to high scan format.
GE OEC Training Page 4 of 7
2 Shading corrected video is applied in Normal image tube field size. IMAGEP.DSF 11/00
Uncorrected video is applied in Mag 1, Mag 2 image tube field size.
Image Path out of
3 25 mHz filter is used when aquiring video during X-Rays. Video Controller PCB
5 mHz filter is used when reviewing video from a VCR.
60
Contents
Functional Block Diagrams Released 11/00
P9
Display Adapter PCB Left Monitor
Left
Video TP10
Frame P5
LD_D0 U12 Left_Pix_Data 0 RAMDAC3 Video Buffer Fast Scan Video
Buffer
to Latch to L_Display_Data TVP3030 MAX499 to Left Monitor
U26, U21,
LD_D7 Left_Pix_Data 7 U4 U5 75 7B
U22, U23,
U24
1
U36
Left Video
Right Monitor
Control
From Image Processor
g
PCI Slot 5
9800
Host Pentium CPU
GE OEC Training Page 5 of 7
1 The Display Adapter PCB produces a 75 hZ display rate.
IMAGEP.DSF 11/00
Conf_Done and PLX_CS0 LED's on DS1 lit during normal operation.
2
RFPGA_LED and LFPGA_LED blink occassionaly during normal operation. Image Path in
Display Adapter PCB
61
Contents
Functional Block Diagrams Released 11/00
75
Right P12
Frame Video Buffer Interlaced Video
RD_D0 U16 RT_Pix_Data 0 Buffer RAMDAC4 MAX499 to VCR
to Latch to U31, U27, R_Display_Data TVP3030 U6 75
RD_D7 RT_Pix_Data 7 U28, U29, U9 7C
U30
U37
Right Video
Control
TV_Video BT121
AD_D0 U17 AUX_Pix_Data 0 DS1
Control DAC_VID DATA DAC
to Latch to
U40 U32 Left Channel PLX LOAD OK
AD_D7 AUX_Pix_Data 7
Conf_Status UNBLANK
Indicators IP
VIDEO
U43 1
PCI BUS DS2
INTERFACE
Right Channel ALTERA LOAD OK
Conf_Status UNBLANK
Indicators IP
PCI BUS 0 VIDEO
g
PCI Slot 5
Host Pentium CPU 9800
GE OEC Training Page 6 of 7
IMAGEP.DSF 11/00
1 The following LED's are normally on indicating proper operation of the control cirucuits: Image Path in
PLX_LOAD OK< ALTERA LOAD OK, VIDEO.
The UNBLANK and IP LED's blink during normal operation. Display Controller PCB
62
Contents
Functional Block Diagrams Released 11/00
3C
3A 5B 5C
6C
3C
5C
3A 5B
6C
g
9800
GE OEC Training Page 7 of 7
IMAGEP.DSF 11/00
Image Path
Waveforms
63
Contents
Functional Block Diagrams Released 11/00
Pilot_Hi
Pilot_Lo
Pilot_Shld
P4
P2 1 5 6
P3
U18 TP19 Y1
Sync 39 mHz
TP2
Generator
1 V/div dc
10 ns/div
Interconnect TP2 2
Plug Pilot TP6
J1 Tone Pilot
J3 P6
Detect
T1
16 6 U1 U2
5 5 Diff. 74LS123
4 1 Amp Tone 1
Lemo Receptacle Interconnect Detect
g
Cable Assy. Cable Assy.
9800
GE OEC Training Page 1 of 1
1 TP6 is high (4.5 V) when Pilot Tone is detected.
TP6 is low ( .5 V) when Pilot Tone is not detected. PTONE.DSF 11/00
If no Tone is detected Y1 provides the timing signal.
2 See Image Path into Video Controller PCB Functional Diagram page 3 of 7. Pilot Tone Functional Diagram
64
Contents
Functional Block Diagrams Released 11/00
Pilot Tone
2 P4
P7
P3
P6
Video Controller
3 TP7
U18
P1 Interconnect Plug
Sync V_SYNC*
2 Generator
Backplane
X-ray Controller
P8
U21 P10
486
Embedded System Interface Frame
TP24 P1 P2 P3 Sync
Processor
INT_SYNC* OK
10 Frame Sync
20 3 9
IRQ1
21 8 11 10
4
DS1
Backplane
g
1 See Image Path Overview Functional Diagram page 2 of 7.
65
Contents
Functional Block Diagrams Released 11/00
P8
CINE Bridge PCB RX+
5
RX-
PCI Bus 1 Tachlite 9
Fibre 10
Bridge
Channel TX+ CINE Disk 1 CINE Disk 2
Disk 1
TX-
Controller 6
11
P9
PCI Bus1 Status
Interface
J1 J2
U1 U2
P1 DT QR DT QR P2
Frame Buffer 2 3A
1 1
DR QT DR QT
Frame Buffer 1 2 2
3 Disk 1 Disk 2 3
Frame Buffer 0 Router Router
P4
Bypass D1*
Pixel Packer 1 4
Fail D1*
/ Unpacker 11
Bypass D2*
1 5
P1 Fail D2*
P6 12
CINE 2 Disk Backplane PCB
PCI Bus 0
CINE
Host Data
Pentium D0-D9
P1 P6
g
9800
1 Bypass L= DR QT (Failed Condition) GE OEC Training Page 1 of 3
Bypass H= DT QT ( Normal Condition) CINE.DSF 11/00
CINE Option with
CINE 2 Disk Backplane
66
Contents
Functional Block Diagrams Released 11/00
P8
RX+ 5
RX- 9
10
CINE Disk 3 CINE Disk 4 CINE Disk 5 CINE Disk 6
TX+ 1
TX- 6
11
P9
3A J3 J4 J5 J6
Status
U1 U2 U3 U5
P1 DT QR DT QR DT QR DT P2
QR
1 1
DR QT DR QT DR QT DR QT
C 2 2
I 3 Disk 3 Disk 4 Disk 5 Disk 6 3
Router Router Router Router
N
E P4
Bypass D3*
6
1
B 13
Fail D3*
r Bypass D4*
i 7
1 14
d Fail D4*
g Bypass D5*
8
1
e 15 Fail D4*
Bypass D5*
9
P 1 16
C Fail D5* CINE 4 Disk Backplane PCB
B
g
9800
GE OEC Training Page 2 of 3
CINE.DSF 11/00
67
Contents
Functional Block Diagrams Released 11/00
DS3
Disk Fail 1
Disk Fail 2
Disk Fail 3
Disk Fail 4
DS4 Disk Fail 5
Disk Fail 6
Bypass Disk 1
Bypass Disk 2
DS5 Bypass Disk 3
Bypass Disk 4
Bypass Disk 5
Bypass Disk 6
DS6
Interrupt Indicator
g
9800
GE OEC Training Page 3 of 3
CINE.DSF 11/00
68
Contents
Functional Block Diagrams Released 11/00
PCI BUS
SLOT 5
P11
HOST J3 P3
DISPLAY
PENTIUM CODONICS PRINTER
ADAPTER PCB
CPU or OR
881447
PASSIVE LPT PORT LENZAR CAMERA
BACKPLANE
LPT PORT
ELECTRONICS BOX
9800 WORKSTATION
g
9800
GE OEC Training Page 1 of 1
COD_LENZ.DSF 11/00
PCI BUS
SLOT 8 REAR
EXTERNAL PANEL
HOST INTERFACE PCB
ETHERNET 00-879184
PENTIUM P5
BOARD
CPU or TO HOSPITAL NETWORK
00-901551 RJ 45
PASSIVE or
CONNECTOR
BACKPLANE ASPECT DDPI to PRINTER OPTION
P6
ASPECT DDPI
PRINTER
00-881505
ELECTRONICS BOX
g
9800
GE OEC Training Page 1 of 1
DICOM.DSF 11/00
DICOM/DDPI
Functional Diagram