Power Consumption in CMOS

Luca Di Nunzio
di.nunzio@ing.uniroma2.it
0672597810
http://dspvlsi.uniroma2.it
 Supercomputer

20.000 kW➔20 MW

https://www.top500.org/lists/top500/2022/11/
 Supercomputer
• The R.E. Ginna Nuclear Power Plant in New York is the smallest
nuclear power plant in the United States:
• It has one reactor
• Net summer electricity generating capacity of about 582 MW.
Super computer
 Supercomputer

• It Takes 6,000 Gallons of Water

to Cool the World’s Fastest
Supercomputer
Cloud data center
Cloud Data Center
 Embedded
• Smartphones
• Tablet
• Notebook
• Smartwatch

Porwer consumption impacts:

• Battery life
• Device size
• Reduced power➔ reduced battery size
 Energy per Operation
Energy per operation

𝐸𝑜𝑝 = න 𝑃 𝑡 𝑑𝑡
𝑡𝑜𝑝

top is the time elapsed to perform the

operation ad P(t)=V(t)I(t)
 Average Power
Pave is the average power dissipation in top

‫𝑡𝑑 𝑡 𝑃 𝑡׬‬
𝑜𝑝
𝑃𝑎𝑣𝑒 = 𝐸𝑜𝑝 =
𝑡𝑜𝑝
 Time for operation
For multi-cycle operations
𝑡𝑜𝑝 = 𝑇𝑐𝑦𝑐𝑙𝑒 × (𝑛. 𝑜𝑓 𝑐𝑦𝑐𝑙𝑒𝑠 )
 Energy Per Cycle
By dividing Eop by the n. of cycles we get energy per cycle

𝐸𝑜𝑝
𝐸𝑝𝑐 =
𝑛. 𝑜𝑓 𝑐𝑦𝑐𝑙𝑒𝑠

Epc is proportional to Pave average power dissipation

𝐸𝑜𝑝 𝑃𝑎𝑣𝑒
𝐸𝑝𝑐 = = 𝑃𝑎𝑣𝑒 𝑇𝑐𝑦𝑐𝑙𝑒 =
𝑛. 𝑜𝑓 𝑐𝑦𝑐𝑙𝑒𝑠 𝑓
 Energy Efficiency
• S1: N=10, Tc= 10 ns Pave=9 mW
• S2: N=10, Tc= 15 ns Pave=7 Mw

Which system is more power efficient?

 Energy Efficiency
• S1: N=10, Tc= 10 ns Pave=9 mW
• S2: N=10, Tc= 15 ns Pave=7 mW

Which system is more power efficient?

P
9 mw

7 mw

100 150 t
 Energy Efficiency
• S1: Eop=10*10*9=900 pJ Epc=90 W
• S2: Eop=10*15*7=1050 pJ Epc=105 W

P
9 mw

7 mw

100 150 t
 Energy dissipation in CMOS
• Dynamic dissipation due to charge/discharge of load capacitances and
short circuit current
• Static Dissipation due to leakage current and other current drawn
continuosly from the power supply
Total energy dissipation for a CMOS gate:
Egate=Eload+Esc+Eleakage

Eload is the energy dissipated for charge/discharge load CL when ni transitions

occour
Esc is the energy due to short circuits currents when ni transitions occours
 Load energy dissipation
VDD
VDD

t input output

For an output transition 0➔1:

𝑡 𝑡 𝑉𝑑𝑑
𝑑𝑣 1 2
𝐸𝑐 = න 𝑣𝑖 𝑑𝑡 = න 𝑣𝐶𝐿 𝑑𝑡 = 𝐶𝐿 න 𝑣 𝑑𝑣 = 𝐶𝐿 𝑉𝐷𝐷
0 0 𝑑𝑡 0 2
𝑡 𝑡 𝑉𝑑𝑑
𝑑𝑣 2
𝐸𝑔𝑒𝑛 = න 𝑉𝑐𝑐𝑖 𝑑𝑡 = 𝐶𝐿 𝑉𝑐𝑐 න 𝑑𝑡 = 𝐶𝐿 𝑉𝑐𝑐 න 𝑑𝑣 = 𝐶𝐿 𝑉𝐷𝐷
0 0 𝑑𝑡 0
Egen-Ec is dissipated into the pMOS channel resistance
GND
1 2
For n transitions: 𝐸𝑡 = 𝐶𝐿 𝑉𝐷𝐷 𝑛
2
Short circuit energy dissipation
Leakage energy dissipation
Impact of static dissipation
 Dynamic Power considerations
• Dynamic Power depends on the switching activity of the circuit nodes
• Accurate power estimation is possible only knowing the switching activity of the
nodes
• Without switching activity Dynamic power is estimated considering usually a 50% factor (Vector-
less estimation)
• Post-layout simulation allows us to know the switching activity factor

Power estimation procedure:

1. Perform a post-layout simulation using N random input vectors
2. Generate the SAIF file (Switching Activity Interchange Format)
3. Estimate Power using the power estimation tools
How many Input vectors???
How many Input vectors???