Lecture 1:

Introduction
1. Introduction
2. MOS Transistors
3. CMOS Logic Gates
4. IC Design Flow

1: Introduction
 1. Introduction
 Integrated circuits (IC): many transistors on one chip.
 Very Large Scale Integration (VLSI): bucket loads!
 Complementary Metal Oxide Semiconductor (CMOS)
– Fast, cheap, low power transistors
 Today: How to build your own simple CMOS chip
– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
 Rest of the course: How to build a good CMOS chip

1: Introduction CMOS VLSI Design 4th Ed.

 Growth Rate
 53% compound annual growth rate over 50 years
– No other technology has grown so fast so long
 Driven by miniaturization of transistors
– Smaller is cheaper, faster, lower in power!
– Revolutionary effects on society

[Moore65]
Electronics Magazine

1: Introduction CMOS VLSI Design 4th Ed.

 Transistor Types
 Bipolar junction transistors (BJT)
– npn or pnp silicon structure
– Small current into very thin base layer controls
large currents between emitter and collector
– Base currents limit integration density
 Metal Oxide Semiconductor Field Effect Transistors
(MOSFET)
– nMOS and pMOS MOSFETS
– Voltage applied to insulated gate controls current
between source and drain
– Low power allows very high integration
1: Introduction CMOS VLSI Design 4th Ed.
 Interesting Facts from 2013
 1.4 Billion mobile phones & tablets
– About 100 million transistors per phone processor
– About 2 GB per phone/tablet of memory
 180 million PCs, laptops, desktops, and servers
– About 1 Billion transistors per processor
– Average memory of 8 GB each
 Total logic transistors ~ 3.2E17
 Total memory transistors ~ 4.2E18
– And this doesn’t count flash in cameras, SSDs, …
 About 600 million transistors for each earthling/yr
 140 Billion transistors/second
 90% of all transistors ever made were made in the last 4
years!
 50% of all transistors ever made were made in the last 15
months! have been manufactured by Homo Sapiens!
http://www.quora.com/How-many-transistors-are-made-per-year
Introduction CMOS VLSI Design Slide 3
The iPhone: A VLSI Enabled System

Introduction CMOS VLSI Design Slide 4

 iPhone 3G Parts Breakdown

Electronic Components
About one dozen major ICs
Introduction CMOS VLSI Design Slide 5
 iPhone 4 Parts Breakdown

Electronic Components

Introduction CMOS VLSI Design Slide 6

 iPhone 6 Parts Breakdown

Electronic
Components

https://9to5mac.files.wordpress.com/2014/09/msuctmh4vhqmloo2.jpeg

Introduction CMOS VLSI Design Slide 7

 iPhone 6 Chip Set

http://www.nfcworld.com/wp-content/uploads/2014/09/iphone-6-circuit-board.jpg
http://4.bp.blogspot.com/-
QyO7GPfsy6w/VSMHQQHu_uI/AAAAAAAAAjI/XRZBmn2TnvI/s1600/Back.p ng

A8 processor chip
• Dual core 64b ARM
• 2B transistors
• Graphics processor
• 1 GB DRAM chip stacked on top

http://www.ifixit.com/Misc/iphone_processor_crossection.jpg
https://www.chipworks.com/about-
chipworks/overview/blog/inside-iphone-6-and-
iphone-6-plus-part-2

Introduction CMOS VLSI Design Slide 8

 iPhone Functions
iPhone VLSI Design Class
 Digital Functions Yes
– Processor
– Memory
– LCD Driver
– Analog and Radio Interfaces (glue logic)
 Radio Functions NO
– 2G Cell Phone (GSM) Transceiver
– 3G Data Interconnect Transceiver
– GPS Receiver
– Bluetooth Transceiver
– WiFi Transceiver
– Near Field Wireless
 Analog Functions Very Little
– Audio input and output No Some No
– A-to-D and D-to-A converters No No No
– Video Sensor (2 in iPhone 4) Some No No
– Screen Touch Sensor
– Proximity Sensor
– 3D Accelerometer (6D in iPhone 4
– Digital I/O
– USB Interface
– Firewire Interface
Introduction CMOS VLSI Design Slide 9
 iPhone Technology Timeline
iPhone First Use
Digital Functions
– Processor 1971
– Memory 1971
– LCD Driver 1988
– Analog and Radio Interfaces (glue logic) 1972
 Radio Functions
– 2G Cell Phone (GSM-TDMA) Transceiver 1992
– 3G Data Interconnect Transceiver 2003
– GPS Receiver 1993
– Bluetooth Transceiver 1994
– WiFi (IEEE 802.11) Transceiver 2000
 Analog Functions
– Audio input and output 1952
– A-to-D and D-to-A converters ~1970
– Video Sensor (2 in iPhone 4) 1974
– Screen Touch Sensor 2007
– Proximity Sensor
– 3D Accelerometer (6D in iPhone 4 1990
– Digital I/O
– USB Interface 1995
– Firewire Interface
1995
Introduction CMOS VLSI Design Slide 10
 Transistor and IC History

Introduction CMOS VLSI Design Slide 11

 A Short History of Semiconductors
 What would someone in 2000 think of the iPhone?
 1990?
 1980?
 1970?
 1960?
 1950?

1950 Record Album 2011 iPod Nano

16 songs 5500 songs
30 cm X 30 cm X 3 cm 3.75 cm X 4.09 cm X 0.875 cm
170 cm3 / song 2.4E-3 cm3 / song

70,000 X Improvement

Introduction CMOS VLSI Design Slide 12

 The Beginnings:
The Bipolar Transistor Era 1947-1963

 Point Contact Transistor (Brattain,

Bardeen, Shockley, Bell Labs, 1947)
 Western Electric Allentown, PA
plant begins transistor
manufacturing (1952)
 Germanium Bipolar Transistor
(Saby, GE, 1952)
 Silicon Bipolar Transistor (Moll, Bell
Labs, 1955

Introduction CMOS VLSI Design Slide 13

 Discrete Transistors
Circa 1950s
1959

• 6 transistors
• ~ $200 (in 2010 dollars)
• AM stations only

Introduction CMOS VLSI Design Slide 14

 The Small-Medium Scale Integrated
Circuit Era 1963-1974
 The First Integrated Circuit
– Kilby (TI, 1958) mesa transistors and wirebonds Kilby: 1958
– Noyce (Fairchild, 1959) diffused transistors and
deposited metal
 Silicon Field Effect Transistor comes of age
– MOS Transistor
– Self-Aligned Poly-Gate MOS Transistor
 Key Circuits
– Single-chip Operational Amplifiers
– The first microprocessors
 CAD Fairchild: 1961
– Primitive circuit & logic design
– SPICE developed at UC Berkeley
 The IC business characteristics
– Mfg equipment made by Semiconductor Companies
– Each transistor is unique. Every chip has a device
engineer

Introduction CMOS VLSI Design Slide 15

 Early Chips: The
Thousand Transistor
Limit

Rubylith, the Step-and-Repeat Mask

Machine and Contact Printing

CMOS VLSI Design

 MOS Integrated Circuits
 1970’s processes usually had only nMOS transistors
– Inexpensive, but consume power while idle

Intel 1101 Intel 4004 Intel 1103

256-bit SRAM 4-bit µProc 1K bit DRAM

Introduction CMOS VLSI Design Slide 17

 Intel 4004

• Transistors 2300
• Process 10 µ
• Area 83 mm2
• Clock 100 kHz
Introduction CMOS VLSI Design Slide 18
 4004 Schematic

http://www.4004.com/assets/4004-lajos-schematics.gif
Introduction CMOS VLSI Design Slide 19
 The 8-bit RCA 1802 circa 1975:
The First CMOS Microprocessor
(which went to Jupiter!)

Introduction CMOS VLSI Design Slide 20

 CMOS Chips In Cross Section

http://www.engr.sjsu.edu/WofMatE/images/intercon.gif

http://www.hitequest.com/Kiss/photolithography.gif

Introduction CMOS VLSI Design Slide 21

 Rubylith, the Step-and-Repeat Mask
Machine and Contact Printing

http://s7.computerhistory.org/is/image/CHM/500003094-03-01?$re-inline-artifact$

Introduction CMOS VLSI Design Slide 22

The Large Scale Integrated Circuit
Era 1975-1985

 The Scanning Projection Photolithography - the PEP Tool

 EBES - The Electron Beam Exposure System for Mask
Making
 CAD
– SPICE used for circuit design
– Logic Analysis tools developed

 Technology driven by the DRAM

 The big Microprocessor and the PC

Introduction CMOS VLSI Design Slide 23

 The Beginnings of the PC Era

Intel 8088 Motorola 68000

IBM PC Apple Macintosh

Introduction CMOS VLSI Design Slide 24

 The VLSI Era
1986-?
 The Stepper
 32-64 Bit Microprocessors
 Signal Processing
– Switched Capacitor
• e.g. ISDN U-Interface
– Sigma-Delta A/D Converter
– Digital Signal Processing
 CAD
– Logic Analyzers
• Verilog
• VHDL
– Logic Synthesis
– Static Timing Analyzers
– Mixed Signal Analyzers
– Standard Cell & Routers

Introduction CMOS VLSI Design Slide 25

 Intel 80386
32 bit Microprocessor

Transistors 275 K
Process 1µ
Clock 16-33 MHz

Introduction CMOS VLSI Design Slide 26

Transition to Automation and Regular Structures

Intel 4004 (‘71)

Intel 8080 Intel 8085

Intel 8286 Intel 8486

Courtesy Intel
Introduction CMOS VLSI Design Slide 27
2008: Intel Nehalem Quad
731 M Transistors Core i7 32 nm CMOS

Introduction CMOS VLSI Design Slide 28

 2008: Intel Nehalem Quad: 731 M Transistors

32 nm Technology Node

Transistor CANNOT be seen

under highest power
optical microscope

Why?
Wavelengths of Visible Light
370-750 nm
Dimensions are < 370 nm
Introduction CMOS VLSI Slide 29
Design
 Intel 7500 Xeon

http://download.intel.com/pressroom/kits/xeon/7500series/images/NHM-EX-Die-
Shot-2.jpg
Introduction CMOS VLSI Design Slide 30
 Memory Chips

1k bit DRAM

256M bit DRAM 4Gb bit DRAM

http://sammyhub.com/wp-content/uploads/2012/02/ddr3.jpg

http://www.eeherald.com/images/nand_cell_array.jpg

32Gb bit Flash

http://news.cnet.com/i/bto/20080529/intel-32gb-nand-flash-small.jpg

Introduction CMOS VLSI Design Slide 31

 Active Memory

Terasys 1993 EXECUBE 1993 Micron Yukon 2003

SRAM + 64 1b ALUs 8-cores on 4 Mb DRAM
http://www.nitrd.gov/pubs/bluebooks/1994/nsa.1.3.gif

Introduction CMOS VLSI Design Slide 32

 The Era of Tiled Microprocessors

IBM Cell Tilera

NVIDIA Fermi Intel Phi

Introduction CMOS VLSI Design Slide 33
 The Era of Accelerators
First Generation Google Tensor Processing Unit Chip:
• H/W Dense Matrix-Vector Product (low precision)
• Peak 92,000 G flops/s (8 bit floats)
• Peak H/W Intensity (8-bit) = 2,700 8b flops per byte

https://images.anandtech.com/doci/11749/hc29.22.730-tensorpu-young-google-page-015.jpg

http://3s81si1s5ygj3mzby34dq6qf-wpengine.netdna-ssl.com/wp-content/uploads/2017/05/image004.jpg

4 TPU2’s per card

http://3s81si1s5ygj3mzby34dq6qf-wpengine.netdna-ssl.com/wp-
content/uploads/2017/05/image003.jpg

Introduction CMOS VLSI Design Slide 34

 And Now to 3D Chip Stacks

https://upload.wikimedia.org/wikipedia/commons/thumb/c/c1/Through-
Silicon_Via_Flavours.svg/300px-Through-Silicon_Via_Flavours.svg.png

Introduction CMOS VLSI Design Slide 35

 Scaling and Moore’s Law

Introduction CMOS VLSI Design Slide 36

http://https://upload.wikimedia.org/wikipedia/en/thumb/9/9d/Moore%27s_Law_Transistor_Count_1971-2016.png/1200px-Moore%27s_Law_Transistor_Count_1971-2016.png

Introduction CMOS VLSI Design Slide 37

 Clock Speeds

https://upload.wikimedia.org/wikipedia/en/c/ce/Clock_CPU_Scaling.jpg

Introduction CMOS VLSI Design Slide 38

 Feature Size
 Minimum feature size shrinking 30% every 2-3 years

Today 103

1: Introduction CMOS VLSI Design 4th Ed.

 Corollaries
 Many other factors grow exponentially
– Ex: clock frequency, processor performance

1: Introduction CMOS VLSI Design 4th Ed.

 MOS Transistor Scaling: 1970s- mid 2000s
1974 R. H. Dennard, et. al.

Dimensions 1/K
Channel Width 1/K
Channel Length 1/K
Gate Oxide Thickness 1/K
Green: Diffusion Gate Capacitance 1/K
Red: Oxide Blue:
Metal Power Voltage 1/K
Substrate Doping K
K = “Scale Factor” from one
Circuit Area } 1/K2
generation to next
Speed
Big Win
K
Moore’s Law Current 1/K
Power
K = √ 2 / 2.5 years Power per Unit Area
1/K2
1

Introduction CMOS VLSI Design Slide 40

 MOS Generations
About every 2.5 Years
Dimensions 0.7 X
Channel Length Channel 0.7 X
Width 0.7 X
Gate Oxide Thickness 0.7 X
Gate Capacitance 0.7 X
Stopped
Voltage 0.7 X In ~2005
Substrate Doping 1.4 X
Circuit Area
Peak Speed
0.5 X
1.4 X
} Big Win
Current 0.7 X
Power
Power per Unit Area
X
1/2 X
1
No Longer True
Now Dominates Design Process

Introduction CMOS VLSI Design Slide 41

 Moore’s Law
 Circuit Density - 32% per year
 Circuit Speed
– Scaling - 15% / year
– Architecture and Circuit Design - 10%/year
– Overall - 26%/year
 Chip Size - 15%/year
 Architecture/Parallelism - 35%/year

66% performance improvement per year

Before hitting the Power Wall of 2005

Now Just Architecture/Parallelism

Introduction CMOS VLSI Design Slide 42

 Moore’s Law
 1965: Gordon Moore plotted transistor on each chip
– Fit straight line on semilog scale
– Transistor counts have doubled every 26 months

10,000

1,000 Integration Levels

Transistor Count (Millions)

100
SSI: 10 gates
10

1
MSI: 1000 gates
0 LSI: 10,000 gates
VLSI: > 10k gates
0
1975 1980 1985 1990 1995 2000 2005 2010 2015 2020

Historical Single Core Historical Multi-Core ITRS Projections

Introduction CMOS VLSI Design Slide 43

 Moore’s Design Rule
Scaling Law

10,000
10
Design Rule Generation (nm)

1,000
1
Same circuit is 250 X smaller
20 years later

100
0.1

10
0.01
1970 1980 1990 2000 2010 2020

Year

Introduction CMOS VLSI Design Slide 44

 20 Years of Progress

Introduction CMOS VLSI Design Slide 45

 Today’s Transistor Structure

https://image.slidesharecdn.com/ehudtzuri3dchallanges-new-120529041437-phpapp01/95/the-shift-to-3dic-structures-manufacturing-and-process-control-challenges-12-728.jpg?cb=1338264919

Introduction CMOS VLSI Design Slide 46

 Next Gen Transistors

https://www.researchgate.net/profile/Arvind_Singh64/publication/286439699/figure/fig2/AS:389174046806054@14 69797732007/Fig-2-
CNTFET-Structure-Carbon-nanotube-field-effect-transistors-CNTFETs-utilize.jpg
https://www.blogcdn.com/www.engadget.com/media/2007/06/toshiba-3d-nand.jpg
Carbon Nanotube FET
3D Transistor Array

Introduction CMOS VLSI Design Slide 47

 2. MOS Transistors
 Transistors are built on a silicon substrate
 Silicon is a Group IV material
 Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si

1: Introduction CMOS VLSI Design 4th Ed.

 Dopants
 Silicon is a semiconductor
 Pure silicon has no free carriers and conducts poorly
 Adding dopants increases the conductivity
 Group V: extra electron (n-type)
 Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

1: Introduction CMOS VLSI Design 4th Ed.

 p-n Junctions
 A junction between p-type and n-type semiconductor
forms a diode.
 Current flows only in one direction

p-type n-type

anode cathode

1: Introduction CMOS VLSI Design 4th Ed.

1: Introduction CMOS VLSI Design 4th Ed.
 nMOS Transistor
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor Source Gate Drain
Polysilicon
– Even though gate is SiO2
no longer made of metal
n+ n+
Body
p bulk Si

1: Introduction CMOS VLSI Design 4th Ed.

 nMOS Operation
 Body is usually tied to ground (0 V)
 When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

1: Introduction CMOS VLSI Design 4th Ed.

 nMOS Operation Cont.
 When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

1: Introduction CMOS VLSI Design 4th Ed.

 pMOS Transistor
 Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

1: Introduction CMOS VLSI Design 4th Ed.

 Power Supply Voltage
 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
– Lower V -> increase f
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

1: Introduction CMOS VLSI Design 4th Ed.

 Transistors as Switches
 We can view MOS transistors as electrically
controlled switches
 Voltage at gate controls path from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

1: Introduction CMOS VLSI Design 4th Ed.

 How Does a Transistor Work?
Wall Switch

Power Supply

– In order for the lamp to glow, electrons must flow

– In order for electrons to flow, there must be a closed circuit from
the power supply to the lamp and back to the power supply
– The lamp can be turned on and off by simply manipulating the wall
switch to make or break the closed circuit

CMOS VLSI Design 4th Ed. 61

How Does a Transistor Work?
 Instead of the wall switch, we could use an n-type or a p-type
MOS transistor to make or break the closed circuit
If the gate of an n-type transistor is
Drain supplied with a high voltage, the
connection from source to drain acts
Gate
like a piece of wire (i.e., the circuit is
closed)
Depending on the technology,
Source
high voltage can range from 0.3V to
Schematic of an n-type 3V
MOS transistor
If the gate of the n-type transistor is
supplied with zero voltage, the
connection between the source and
drain is broken (i.e., the circuit is open)
CMOS VLSI Design 4th Ed. 62
How Does a Transistor Work?
 The n-type transistor in a circuit with a battery and a bulb

3
0 Volt
Gate

Power Supply
Shorthand notation

 The p-type transistor works in exactly the opposite fashion

from the n-type transistor
Drain Drain
The circuit is closed The circuit is closed
when the gate is when the gate is
supplied with 3V Gate Gate
supplied with 0V
n-type p-type
Source Source
63
Logic Gates

64
One Level Higher in the Abstraction
 Now, we know how a MOS transistor works
 How do we build logic structures out of MOS transistors?
Problem
 We construct basic logical units out of Algorithm
individual MOS transistors Program/Language
Runtime System
(VM, OS, MM)
 These logical units are called logic gates ISA (Architecture)
 They implement simple Boolean functions Microarchitecture
Logic
Devices
Electrons

George Boole, “The Mathematical Analysis of Logic,” 1847. 65

Making Logic Blocks Using CMOS Technology
 Modern computers use both n-type and p-type transistors,
i.e. Complementary MOS (CMOS) technology
nMOS + pMOS = CMOS

 The simplest logic structure that exists in a modern

computer 3V

p-type

In (A) Out (Y) What does this circuit do?

n-type

0V
66
Functionality of Our CMOS Circuit
What happens when the input is connected to 0V?

3V 3V
p-type transistor
pulls the output up

0V Out (Y) Y = 3V

0V 0V

p-type transistors are good at pulling up the voltage

67
Functionality of Our CMOS Circuit
What happens when the input is connected to 3V?

3V 3V

A= 3V Out (Y) Y = 0V

n-type transistor pulls

the output down

0V 0V

n-type transistors are good at pulling down the voltage

68
CMOS NOT Gate (Inverter)
3V
 This is actually the CMOS NOT Gate
 Why do we call it NOT? P
 If A = 0V then Y = 3V In (A) Out (Y)
If A = 3V then Y = 0V
N


 Digital circuit: one possible interpretation

 Interpret 0V as logical (binary) 0 value
0V
 Interpret 3V as logical (binary) 1 value

A P N Y
0 ON OFF 1
1 OFF ON 0

69
 3. CMOS logic gates
CMOS Inverter
VDD
A Y
0 1 OFF
ON
0
1
1 0 A Y
ON
OFF

A Y
GND
3: CMOS Technology CMOS VLSI Design 4th Ed.
 CMOS NAND Gate
A B Y
0 0 1 ON
OFF
OFF
ON OFF
ON
0 1 1
1
Y
0
1 0 1
A ON
OFF
1 1 0 0
1
1
0
B OFF
ON
ON
OFF

3: CMOS Technology CMOS VLSI Design 4th Ed.

CMOS AND Gate
 How can we make an AND gate?
A B Y
0 0 0
0 1 0 A
1 0 0 Y
1 1 1 B
3V 3V
We make an AND gate using
one NAND gate and P1 P2 P3
one NOT gate Out (Y)
In (A) N1 N3

In (B) N2
0V

0V

72
CMOS NOT, NAND, AND Gates
A A
A Y Y Y
B B

A Y A B Y A B Y
0 1 0 0 1 0 0 0
1 0 0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1
3V
3V 3V 3V

P1 P2 P1 P2 P3
P Out (Y)
Out (Y)
In (A) Out (Y) In (A) N1 In (A) N1 N3
N
In (B) N2 In (B) N2
0V

0V 0V 0V

73
 CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

3: CMOS Technology CMOS VLSI Design 4th Ed.

 3-input NAND Gate
 Y pulls low if ALL inputs are 1
 Y pulls high if ANY input is 0

Y
A
B
C

3: CMOS Technology CMOS VLSI Design 4th Ed.

 4. IC Design Flow

1: Introduction CMOS VLSI Design 4th Ed.

 Logic Design
 Define the top-level chip interface and block diagram
 Specify the logic with a Hardware Description Language (HDL),
which provides a higher level of abstraction than schematics or
layout.
 This code is called the Register Transfer Level (RTL) description.

module adder(
input logic [7:0] a, b,
input logic c,
output logic [7:0] s,
output logic cout);

1: Introduction CMOS VLSI Design 4th Ed.

 Circuit Design
 Circuit design is to arrange transistors to perform a
particular logic function.
 A particular logic function can be implemented in
many ways
 Circuit designers often draw schematics at the
transistor and/or gate level.

1: Introduction CMOS VLSI Design 4th Ed.

 Physical Design
 Physical design is to map the RTL into actual geometric representations
of all electronics devices, such as capacitors, resistors, logic gates, and
transistors
 Physical design step:
– Floorplanning: The RTL of the chip is assigned to gross regions of
the chip, input/output (I/O) pins are assigned and large objects
(arrays, cores, etc.) are placed.
– Placement: The gates in the netlist are assigned to non-overlapping
locations on the die area.
– Clock insertion: Clock signal wiring is (commonly, clock trees)
introduced into the design.
– Routing: The wires that connect the gates in the netlist are added.
– Final checking
– Tapeout: and mask generation: the design data is turned into
photomasks

1: Introduction CMOS VLSI Design 4th Ed.

 Design Verification
 Design verification is essential to catching the
errors before manufacturing
 A testbench is used to verify that the logic is
correct
 Formal verification tools are to check that a
circuit performs the same Boolean function as
the associated logic.
 Layout vs. Schematic tools (LVS) check that
transistors in a layout are connected in the
same way as in the circuit schematic.
 Design rule checkers (DRC) verify that the
layout satisfies design rules.
 Electrical rule checkers (ERC) scan for other
potential problems such as noise or premature
wearout;

1: Introduction CMOS VLSI Design 4th Ed.

Fabrication, Packaging, and Testing

 The mask descriptions are sent to the

manufacturer electronically for fabrication.
 Two common formats for mask descriptions:
– Caltech Interchange Format (CIF) (mainly
used in academia)
– Calma GDS II Stream Format (GDS:
Graphic Database System) (used in
industry).
 A set of masks for a nanometer process can be very expensive.
– In a 65 nm process, the mask set costs about $3 million
– With a university discount, the cost for a run of 40 small chips
on a multi-project wafer can run about $10,000 in a 130 nm
process down to $2000 in a 0.6 µm process.
1: Introduction CMOS VLSI Design 4th Ed.
 Review
1. What do they mean?
1. IC, VLSI, HDL, RTL, LVS, DRC, ERC, CIF, GDSII, BJT,
MOSFET, CMOS
2. Describe brief history of transistors
3. How to make a MOS transistor?
4. What are differences between nMOS and pMOS?
5. What is IC design flow?
6. Describe logic design
7. Describe circuit design
8. Describe physical design
9. What are CMOS logic gates?
10. Sketch a transistor-level schematic for a CMOS 4-input NOR
11. Sketch a transistor-level schematic for a CMOS 4-input NAND
1: Introduction CMOS VLSI Design 4th Ed.