Digital Circuit Design

Prof. MacDonald
Course Overview
!  Intro to CMOS circuit design
–  standard cell libraries
!  combinational
!  sequential
!  dynamic

–  semiconductor memories
!  DRAM
!  SRAM
!  ROMs

–  IOs
–  Clock trees
–  Power Grids
–  Phase-Lock Loops (Introduction to)
Course Overview
Flip-Flop
Flip-Flop Layout
Chip with circuit rows
Silicon Art – Slide 2 – UTEP Art
CMOS – Historical Perspective
!  the 70’s: NMOS primary technology
–  CMOS becomes usable in late 70’s
!  CMOS doesn’t consume power when idle – battery applications
!  calculators – slide rules disappear
!  digital wrist watches
!  the 80’s: CMOS dominates and the PC is born
!  1985: accusations of Japanese chip-dumping
–  Japanese extend existing photolithographic technology
–  US migrates to next generation tools and can’t get it working
!  the 90’s: CMOS gets smaller, faster, more integrated
!  the 00’s: CMOS scaling continues but leakage
emerges
CMOS – Moore’s Law
!  Gordon Moore – co-founder of Intel
!  Empirical observation
–  advances in semiconductors double every 18 months
–  transistors get smaller
–  speed increases
–  transistor count increases
–  self-fulfilling prophecy
–  doesn’t hold true for memories – thus caching important
–  every year since, the end CMOS scaling 5 years off
–  current challenge is gate oxide leakage with Tox below 15 A
!  static power set to overtake dynamic power consumption
!  lack of static power was original advantage of CMOS over Bipolar
!  gate oxides so thin (10 atomic layers) tunneling occurs
CMOS – Moore’s Law – channel length
100

First MOS 4 bit processor - Intel's 4044

10
Japanese DRAM crisis
Leffective(microns)

DEC Alpha 500 MHz processor

CMOS comes on-line
1

my career started
0.1
working on 0.8u DSPs
at Motorola

0.01
1960 1970 1980 1990 2000 2010 2020
Year
CMOS – Moore’s Law - transistors
100,000,000

10,000,000

1,000,000

100,000

10,000

1,000
1965 1970 1975 1980 1985 1990 1995 2000 2005
CMOS – Moore’s Law - speed
35000

30000

25000

20000

15000

10000

5000

0
1990 1995 2000 2005 2010 2015 2020
CMOS – Moore’s Law – DRAMs
100000

10000

1000
DRAM Mbits

1 Gbit DRAM

256 Mbit DRAM

100

16 Mbit DRAM
10

1
1990 1995 2000 2005 2010 2015 2020
PPC405LP
Full Custom CMOS design
!  Only done when performance is king
!  Unit cost is medium - $50 a chip
!  Performance is best – 3 GHz processor
!  Development cost (one time cost) is very high
–  1000 engineers working for 2 years and costed at $200k/year
–  $400 million dollar development cost – wow!
–  turn around and sell 100 million chips for $150 each
–  $15 billion income – wow! development cost insignificant
–  moral of the story:
!  get a lot of engineers to hand tweak design for max performance
!  but you better sell a lot of them…
ASIC Chips (AKA Semi-custom)
!  Mostly logic design in Verilog and VHDL
!  Little transistor-level work
!  Synthesis/Place/Route cells from logic library - tools
!  Library includes
–  standard cells (i.e. ANDs, OR’s, Flip Flops)
–  memories
–  IO blocks (input and output of chip)
–  Phase-Lock Loops
–  probably developed in another company (i.e. ARM-Artisan)
!  Fabricate in a foundry (i.e. TSMC, IBM, AMI, TI)
!  10 to 50 engineers in one year to design chip
ASIC Chips
!  Good trade-off between performance / price
!  Unit Cost low - $5 to $10
!  Performance medium – 400 MHz
!  Development cost medium
–  50 engineers for one year at $200k/year = $10 million
–  sell 10 million graphics cards - chip adds $10 of value
–  $100 million income (minus cost of fabrication)
!  Good approach for system level manufacturers
–  Cisco, NVidia, Nokia
–  Let someone else fabricate it – Fab is $5B capital expense
–  need chip to differentiate product
!  router, cell phone, graphics card
FPGA Chips
!  Greatest Flexibility – update chips in customer’s hands
!  Performance low – 100 MHz
!  Unit cost High - $50 to $200 per chip
–  good for low volumes only – say less than 10,000
–  can start with FPGAs and migrate to ASIC later
!  Development cost low
–  2 engineers for 6 months at $200k/year = $200,000
–  no mask charges which are now approaching $1M for ASICs
!  Unit cost are getting better
–  some say FPGAs will soon take over the world