Semiconductor

Manufacturing Processes

Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda
October 2001 by Prentice Hall
Chapter 9 - IC Fabrication Process Overview
Stages of Integrated Circuit Fabrication
From Sand to Silicon

1. Collection of Sand
2. Drying and Screening
3. Cleaning and Dehydration
4. Drying and Packaging
From Sand to Silicon
1. Collection of Sand 2. Drying and Screening 3. Cleaning and Dehydration 4.Drying and Packaging
Single Crystal Silicon Wafer Production

1. Czocharlski Growth 2. Grinding and Slicing 3. Lapping and Etching 4. Polishing and Cleaning
Single Crystal Silicon Wafer Production

1. Czocharlski Growth 2. Grinding and Slicing 3. Lapping and Etching 4. Polishing and Cleaning
From Unpatterned Wafer to Completed Wafer
 Simplified Schematic of High-Temperature Furnace
Thermocouple
Temperature measurements Gas flow
Process gas
controller controller

Quartz tube

Heater 1
Temperature-
setting voltages
Heater 2
Three-zone
Heating
Heater 3 Elements

Processes : oxidation, diffusion, deposition,

anneals, and alloy
Exhaust
Pressure
controller
Simplified Schematic of Photolithography Processing Module
Simplified Schematic of Photolithography Processing Module
Simplified Schematic of (dry) Plasma Etcher
Simplified Schematic of Ion Implanter
Simplified Schematic of Chemical Vapor Deposition Processing System
Why yellow light?
Classifications of Clean rooms.
Schematic of Complementary Metal-Oxide Silicon (CMOS) Manufacturing Steps
n-well formation

(1) Epitaxial layer - improved quality and fewer defect

(2) Initial oxide - protects epi layer from contamination,
(3) Photoresist - prevents excessive damage to ion implantation
(4) Ion implantation - control the depth of the dopant
(5) Annealing - (a) drive-in, (b) repair damage, (c) activation
p-well formation

(1) Photoresist
(2) Ion implantation
(3) Annealing
Shallow Trench Isolation (STI) Etching

(1) Barrier Oxide

(2) Nitride (a) protect active region, (b) stop layer during CMP
(3) Photoresist - 3rd mask
(4) STI etching
(5) Annealing
STI Oxide Fill

(1) Liner oxide - improve the interface between the Si and

trench CVD oxide
(2) CVD oxide deposition
STI Formation

(1) Trench oxide polish (CMP) - nitride as the CMP stop layer since nitride is harder than oxide
(2) Nitride strip: hot phosphoric acid
Poly gate Structure Process

(1) Oxide - thickness 1.5 ~ 5.0 nm is thermal grown

(2) Poly-Si ~ 300 nm is doped and deposited in LPCVD using SiH4
(3) Antireflective coating (ARC) - very critical
(4) Dry etching - the most critical etching step
n- Lightly Doped Drain (LDD) Implant

(1) Photoresist
(2) Implantation – LDD using large mass implant (BF2, instead of B)
p- LDD Implant

(1) Photoresist LDD: lightly doped drain to reduce S/D leakage

(2) Implantation – lightly doping the drain to reduce S/D leakage using large mass implant (As instead of P)
Side Wall Spacer Formation

(1) Thin film – thin oxide spacer to prevent higher S/D implant from penetrating too close to the channel
(2) Etching – by plasma etcher
n+ Source/Drain Implant

(1) Photoresist
(2) Ion implantation
p+ Source/Drain Implant

(1) Photoresist
(2) Ion implantation
(3) Diffusion - rapid thermal anneal (RTA) to control diffusion of dopant
Contact Formation

(1) Thin Films – deposition of Ti with low resistivity and good adhesion against metal. No mask needed (self-align).
(2) Annealing - to form TiSi2, tisilicide
(3) Chemical etching - to remove unreact Ti, leaving TiSi2, called selective etching.
Local Interconnect (LI) Oxide Dielectric Formation

(1) Thin Films – Nitride CVD

(2) Thin Film – Doped Oxide CVD
(3) Polish – Oxide
(4) Etching – LI Oxide etch
LI Metal Formation

(1) Thin Film – Ti deposition

(2) Thin Film – Ti/TiN deposition
(3) Thin Film –Tungsten deposition
(4) Polishing – LI tungsten polish
Via-1 Formation

(1) Thin Film – interlayer dielectric (ILD) for insulation between metals
(2) Polishing – oxide polish
(3) Etching – ILD-1 oxide etch, i.e. via-1 formation
Plug-1 Formation

(1) Thin Film – Ti deposition

(2) Thin Film – Ti/TiN deposition
(3) Thin Film – Tungsten deposition
(4) Polishing – tungsten polishing (Plug-1)
SEM Micrographs of Polysilicon, Tungsten LI and Tungsten Plugs
Metal-1 Interconnect Formation

(1) Thin Film – Ti deposition

(2) Thin Film – Al + Cu(1%) deposition
(3) Thin Film – TiN deposition
(4) Photolithography
(5) Etching – Metal-1 etch
SEM Micrographs of First Metal Layer over First Set of Tungsten Vias
Full 0.18 m CMOS Cross Section SEM Micrograph of Cross-section of AMD Microprocessor

Mag. 18,250 X
Integrated Circuit Engineering
Wafer Electrical Test using a Micromanipulator Prober (Parametric Testing)

1. After metal-1 etch, wafer is

tested.
2. After passivation test again.
3. Sort good die.
4. Before packaging, wafer is
backgrind to a thinner
thickness for easier slice and
heat dissipation.
Stages of Integrated Circuit Fabrication
The Chip War