Bilal Shaikh

559-718-8141 • San Diego, CA. 92130 • bshaikh0712@gmail.com

IC Mask Layout Designer

Summary
A driven individual with knowledge of team-based support, written, & CAD skills to meet the prerequisites of the
semiconductor industry. Genuinely dedicated personality who’s eager to learn & follow a workflow on a timed schedule.
Recognizes the significance of regular communication with team members & customers when putting efforts towards
task(s) completion.
Skills Summary
CAD Skills- Cadence Virtuoso IC 6.1.8, Klayout, Siemens Calibre DRC, soft ERC, LVS, & Skill Code intro course
Data Analysis- Forecasting estimates, Floor planning, Research of design, & Database management
Soft skills- Excel, Pivot charts, Microsoft word, PowerPoint, Linux vi(m), Linux gvim editor, synchronicity, cliosoft, & ic
manage.
Technology Process Nodes- 14nm intel, 22nm intel, 22FDX GF, 64nm Sky water, 65nm intel, 130 nm GF, & 180 nm jazz
Professional
Macom  
Newport Beach, CA
Principal Layout Engineer - Data Center & Telecommunication applications November 2022 –
March 2023
• Specialized in floor planning complex sub blocks consisting of ddmi, ADC’s, level shifters, & various
mixed signal blocks
• Utilized technologies for projects using 22fdx global foundry and 180 nm jazz semiconductor.
• Primary utilized as a resource in readjusting cell level & mid hierarchy blocks for top level routing.
• Fixed basic verification issues related to DRC, soft ERC, & LVS for all levels of layouts.
• Submitted weekly reports and excel sheet charts of updated layout hierarchy for auditing purposes.
Epirus, Inc.  
Torrance, CA
Analog Layout Engineer - RF Smart Power May 2022 –
October 2022
• Specialized in floor planning complex sub blocks consisting of DAC’s, ADTC, opamps, level shifters, and
various RF-based blocks for full chip level.
• Utilized technology node of 130 nm global foundry for project work
• Developed various custom standard cells both substrate & sub diode-based cells used within the circuitry.
• Edited schematics for custom lower hierarchy blocks that were helpful for top level schematic creation and
verifying layout sub blocks.
• Created daily excel sheet reports related to updates of layout for daily scrum meetings
• Fixed several verification issues related to EM, Antenna, HV to LV device connections, matching, basic
spacing issues for DRC, & various parasitic problems.
• Completed several top-level DRC & LVS debugging prior to tape out schedule.
• Developed custom guard ring surround for isolating deep nwell devices.
HRL Laboratories  
Malibu, CA
IC Layout Engineer - Sensors & Electronics September 2019 –
May 2022
• Focused on floor planning complex sub blocks consisting of DAC’s, bias, opamps, bandgaps, pad frames,
and various sensor-based blocks for full chip level.
• Utilized various technology nodes ranging mainly from 22fdx global foundry, 130 nm global foundry, 64
nm Sky water, & limited work in 14 nm ffl intel foundary.
• Assisted in creating schematics for custom sub blocks that were helpful for top level schematic creation
and layout sub blocks.
• Prepared thorough floor planning of packaging layout for various custom dies.
• Developed custom multipart path (taps) in cadence virtuoso for our team which had no guard ring
structures for isolating substrates in layout.
• Assisted with documenting fab based documentation for test chips & prepared monthly PowerPoint slides
for wafer probe maps to evaluate further chip improvement.
 • Trained new layout hires in preparation for projected layout assignments, comprehending complex design
rules, and following HRL specific design methodologically for floor planning layouts.

Intel  
Folsom, CA
Mask Layout Designer - Non-Volatile Memory April 2017 –
April 2019
• Participated & Improved functionality of multiple regression test cases for design rule checks for CAD
team.
• Utilized technology using nodes 22nm & 65 nm intel foundry.
• Created various standard cell, sub & mid-block level digital devices that were utilized on assigned
projects.
• Specialized in creating sub blocks such as irom, mrom, periphery edge cells, y-mux’s & various IO
devices for pockets based at full chip level
Education
Cadence Design Systems Inc , San Jose, CA December 2020 – October
2021
-SKILL Language Programming Introduction Certification

Silicon Drafting Institute, San Jose, CA January 2016 – January

2017
-Advanced BiCMOS IC Layout Certification

University of California, Santa Cruz

Bachelor of Arts | History September 2007 – June
2012