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  • DFT Test 1-1

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    Anonymous VASS3z0wTH
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    This document contains a DFT test with 26 multiple choice questions covering various topics related to design-for-test (DFT) such as: 1) the relation between defects, faults, and errors, 2) scan chain operation, 3) compression ratio, 4) controllability and observability, 5) scan insertion, 6) edge mixing and lock-up latches, 7) scan flow, 8) compressor logic, 9) the need for compression, 10) full scan vs partial scan and top-down vs bottom-up approaches. The test has a maximum of 100 marks over a 3 hour time period.

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    DFT_Test_1-1

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    This document contains a DFT test with 26 multiple choice questions covering various topics related to design-for-test (DFT) such as: 1) the relation between defects, faults, and errors, 2) scan chain operation, 3) compression ratio, 4) controllability and observability, 5) scan insertion, 6) edge mixing and lock-up latches, 7) scan flow, 8) compressor logic, 9) the need for compression, 10) full scan vs partial scan and top-down vs bottom-up approaches. The test has a maximum of 100 marks over a 3 hour time period.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    4 views2 pages

    DFT Test 1-1

    Uploaded by

    Anonymous VASS3z0wTH
    This document contains a DFT test with 26 multiple choice questions covering various topics related to design-for-test (DFT) such as: 1) the relation between defects, faults, and errors, 2) scan chain operation, 3) compression ratio, 4) controllability and observability, 5) scan insertion, 6) edge mixing and lock-up latches, 7) scan flow, 8) compressor logic, 9) the need for compression, 10) full scan vs partial scan and top-down vs bottom-up approaches. The test has a maximum of 100 marks over a 3 hour time period.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 2

    DFT TEST – 01

    Maximum marks : 100


    Maximum time : 3hrs

    Note : All the questions are compulsory.

    Q.NO QUESTION MARKS

    1. What is the relation between defect, fault and error ? 2 marks


    2. What is compression ratio ? 2 marks
    3. What are the input and output files required for scan ? 2 marks
    4. What is controllability and observability? 2 marks
    5. What is DFT? What is scan insertion? 2 marks
    6. What is edge mixing ? Why should you add a lock-up latch in 2+3
    between +ve flop and -ve flop? 5 marks
    7. Explain scan flow. 5 marks
    8. Explain compressor logic in EDT. 5 marks
    9. Explain the need of compression with an example. 5 marks
    10. Explain scan chain operation with an example. 5 marks
    11. Differentiate between full scan and partial scan. 2.5 + 2.5
    Differentiate between top down and bottom up approach. 5 marks
    12. What is lockup latch ? How will you take care when there are 2+3
    multiple clock domains in your design ? 5 marks
    13. What is scan chain balancing? What will happen if we don’t 2+2
    balance scan chains ? 4 marks
    14. What does TCD file contain? 1 mark
    15. What is DRC ? What is bus contention ? 1+1+3
    What logic will the tool insert to correct bus contention violation? 5 marks
    16. Explain the mechanism to bypass EDT logic along with a 5 marks
    diagram.
    17. Which of the 2 approaches is suitable when there are sub-blocks 1+4
    in the design? 5 marks
    Justify your answer.
    18. How will you deal with pre-existing scan chains in the design ? 5 marks

    19. What are the advantages of scan ? 5 marks


    20. Explain the need and working of integrated clock gating cell. 5 marks
    21. Explain the difference between pin, port and pad. 5 marks

    22. How will you decide the no. of scan chains ? 5 marks
    23. What is the difference between combinational and sequential 2 marks
    ATPG ?
    24. Given a 2 input AND gate. What a verification engineer and DFT 2 marks
    engineer do?
    25. What is the use of EDT update signal? 2 marks
    26. How will you correct the following DRCs? 2+2
    i. 4 marks

    ii.

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