UP-DOWN COUNTER VIP V-Plan

AIonsi
Author:Avinash Singh
Date: 12/04/2022

Table of Contents:

1
Sl. No Page
No
1. Stimulus. 3
1.1.Direct Stimulus. 3
1.2.Random Stimulus. 3
1.3.Constrain random stimulus. 3
2. Interface. 3
2.1 intf_interface 3
3. Features. 4
3.1Reset Features. 4
3.2 Up or down counter 5
3.3 Up counting 5
3.4 Down counting 5

4. TB Architecture 5
4.1 Architecture components 6
5. Checker 7
5.1 Direct Check 7
5.2 Reference logic check 7
6. Coverage 7

2
1. Stimulus
 Stimulus are the input data which we need to pass through sequence or
transaction class, to the driver class to drive it to DUT.

 VIP can pass either stimulus directly through sequence or it can generate
random stimulus through transaction class or it can have constraint to
generate random stimulus.

 So, based on all the above conditions we have three types of stimulus.

1.1 Direct stimulus

1.2 Random stimulus
1.3 Constraint Random stimulus

1.1 Direct stimulus

 Yes Required
 Here start,stop and counter_value signals are direct stimulus.
 Signal Declaration:-
◦ bit start
◦ bit stop
◦ Logic [7:0] counter_value

1.2 Random stimuls

 Yes Required
 Here stepup_down is random stimulus.
 Signal Declaration:-
◦ Rand bit stepup_down

1.3 Constraint Random stimuls

 Not Required

2.Interface
These are the Interface Siginals:

logic stepup_down;
logic stop;
logic [7:0] counter_value;

3
  Here we required only one inteface i.e intf_counter interface.
 Inside the interface we need clocking block and modport for driver, write
monitor and read monitor.

2.1 INTF_interface
Siginals to DUT

 Inputs to DUT
◦ Stepup_down;
◦ stop;

 Outputs from DUT

◦ Stepup_down;
◦ stop;
◦ Counter_value;

Siginals to TB

 Output from TB
◦ Stepup_down;
◦ stop;

 Input to TB
◦ Stepup_down;
◦ stop;
◦ Counter_value;

3. Features
3.1. Reset.
3.2. Up or Down counting.
3.3 Up counting.
3.4 Down counting.

3.1 Reset
 stop is an active high signal, when stop=1 all signal goes zero.

4
3.2 Up or Down counting
 After reset we have to check for up or down condition. For that we
have used stepup_down signal.
 If stepup_down = 1, then it will work as an up counter and if
stepup_down = 0 it will work as a down counter.

3.3 Up counting
 After getting signal stepup_down as 1 it have two features.
 If signal counter_value = 100, then assign 1 to counter_value.
 If counter_value signal is less than 100 then increment it by 1.

3.4 Down counting

 After getting signal stepup_down as 0 it have two features.
 If signal counter_value = 1, then assign 100 to counter_value.
 If counter_value signal is greater than 1 then decrement it by 1.

4. TB Architecture
Tb architecture provides all the information about components.

5
4.1 Architecture Components
 Generator
 Driver
 Write monitor
 Read monitor
 Reference model
 Scoreboard
 Environment
 Test
 Top

4.2.1 Generator
 Generator drives the packet containing all the signals to the driver by
using a mailbox.

4.2.2 Driver
 Driver is used to drive all the signals to dut and to the write monitor
by interface.

4.2.3 Write monitor

 Write monitor will drive the signals to reference model.

4.2.4 Read monitor

 Read monitor will get the output of DUT by interface.

4.2.5 Reference model

 Reference model will get the signals from write monitor and by using
them it will generate desired output.

4.2.6 Scoreboard
 Scoreboard will compare the data from reference model and read
monitor.

4.2.7 Environment
 Environment contains all these components.

4.2.8 Test

6
  It contains all the required test cases.

4.2.9 Top
 Top module have interface and test files.

5.Checker
 Checkers are used to cross check the functionality of the dut and
automate the check.
 There are two types of checker.
5.1. Direct Check
5.2. Reference logic Check

5.1 Direct Check

 Not Required.

5.2 Reference logic check

 Yes required.
 In reference logic check, scoreboard will compare expected output
with actual output with reference logic.
 Reference model will generate the expected output.

7. Coverage
 Functional Coverage is the determination of how much functionality of a
design has been exercised by a verification environment.
 To track the Counter IP we need only one covergroup.
 Covergroups is
6.1. covergroup counter_cov

6.1 covergroup counter_cov

 Covergroup contains all the coverpoints
 coverpoints are
6.1.1.coverpoint stop
6.1.2. coverpoint stepup_down
6.1.3 coverpoint counter_value

7
8