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1OUT
4OUT
1IN –
4IN –
I-Suffix Types)
NC
D Ultra-Low Power . . . Typically 195 µW
at 25°C, VDD = 5 V 3 2 1 20 19
D Output Voltage Range includes Negative
1IN + 4 18 4IN +
NC
NC 5 17
Rail
GND
D High Input Impedance . . . 1012 Ω Typ
VDD
NC
6
7
16
15 NC
D ESD-Protection Circuitry 2IN + 8 14 3IN +
D Small-Outline Package Option Also
9 10 11 12 13
2IN –
3IN –
2OUT
NC
3OUT
D Designed-In Latch-Up Immunity
N Package
LinCMOS technology, which provides offset
voltage stability far exceeding the stability 25
available with conventional metal-gate pro-
cesses. 20
description (continued)
In general, many features associated with bipolar technology are available on LinCMOS operational
amplifiers, without the power penalties of bipolar technology. General applications such as transducer
interfacing, analog calculations, amplifier blocks, active filters, and signal buffering are easily designed with the
TLC27L4 and TLC27L9. The devices also exhibit low voltage single-supply operation and ultra-low power
consumption, making them ideally suited for remote and inaccessible battery-powered applications. The
common-mode input voltage range includes the negative rail.
A wide range of packaging options is available, including small-outline and chip-carrier versions for high-density
system applications.
The device inputs and outputs are designed to withstand –100-mA surge currents without sustaining latch-up.
The TLC27L4 and TLC27L9 incorporate internal ESD-protection circuits that prevent functional failures at
voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in
handling these devices, as exposure to ESD may result in the degradation of the device parametric
performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from – 40°C to 85°C. The M-suffix devices are characterized for operation from – 55°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
VIOmax SMALL CHIP CERAMIC PLASTIC
TA TSSOP FORM
AT 25°C OUTLINE CARRIER DIP DIP
(PW) (Y)
(D) (FK) (J) (N)
900 µV TLC27L9CD — — TLC27L9CN — —
2 mV TLC27L4BCD — — TLC27L4BCN — —
0°C to 70°C
5 mV TLC27L4ACD — — TLC27L4ACN — —
10 mV TLC27L4CD — — TLC27L4CN TLC27L4CPW TLC27L4Y
900 µV TLC27L9ID — — TLC27L9IN — —
2 mV TLC27L4BID — — TLC27L4BIN — —
– 40°C to 85°C
5 mV TLC27L4AID — — TLC27L4AIN — —
10 mV TLC27L4ID — — TLC27L4IN — —
900 µV TLC27L9MD TLC27L9MFK TLC27L9MJ TLC27L9MN — —
– 55°C to 125°C
10 mV TLC27L4MD TLC27L4MFK TLC27L4MJ TLC27L4MN — —
The D package is available taped and reeled. Add R suffix to the device type (e.g., TLC27L9CDR).
P3 P4
R6
R1 R2 N5
IN –
P5 P6
P1 P2
IN + C1
R5
OUT
N3
N1 N2 N4 N6 N7
R3 D1 R4 D2 R7
GND
108
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
PIN (11) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA
Total current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or PW package . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN –.
3. The output may be shorted to either supply. Temperature and /or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application section).
φm VI = 10 mV, f = B1,
Phase margin 34°
CL = 20 pF, See Figure 3
φm VI = 10 mV, f = B1,
Phase margin 38°
CL = 20 pF, See Figure 3
VDD VDD +
– –
VO VO
+ +
VI VI
CL RL CL RL
VDD –
(a) SINGLE SUPPLY (b) SPLIT SUPPLY
2 kΩ 2 kΩ
VDD VDD +
20 Ω – –
1/2 VDD VO VO
+ +
20 Ω
20 Ω 20 Ω
VDD –
10 kΩ 10 kΩ
VDD VDD +
100 Ω 100 Ω
VI – VI –
VO VO
+ +
1/2 VDD
CL CL
VDD –
V = VIC
8 14
full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal
input signal until the maximum frequency is found above which the output contains significant distortion. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 1. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained
(Figure 5). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(a) f = 100 Hz (b) BOM > f > 100 Hz (c) f = BOM (d) f > BOM
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices and require longer test times than their bipolar and BiFET counterparts. The problem becomes more
pronounced with reduced supply levels and lower temperatures.
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage Distribution 6, 7
αVIO Temperature coefficient Distribution 8, 9
vs High-level
g output current 10,, 11
VOH High-level
g output voltage
g vs Supply voltage
g 12
vs Free-air temperature 13
vs Common-mode
Common mode input in ut voltage 14, 15
vs Differential input voltage
g 16
VOL Low level output voltage
Low-level
vs Free-air temperature 17
vs Low-level output current 18, 19
vs Supply
y voltage
g 20
AVD Differential voltage
g amplification vs Free-air temperature 21
vs Frequency 32, 33
IIB / IIO Input bias and input offset current vs Free-air temperature 22
VIC Common-mode input voltage vs Supply voltage 23
vs Supply
y voltage
g 24
IDD Supply current
vs Free-air temperature 25
vs Supply
y voltage
g 26
SR Slew rate
vs Free-air temperature 27
Normalized slew rate vs Free-air temperature 28
VO(PP) Maximum peak-to-peak output voltage vs Frequency 29
vs Free-air temperature 30
B1 Unity gain bandwidth
Unity-gain
vs Supply voltage 31
vs Supply
y voltage
g 34
φm Phase margin
g vs Free-air temperature 35
vs Capacitive loads 36
Vn Equivalent input noise voltage vs Frequency 37
φ Phase shift vs Frequency 32, 33
TYPICAL CHARACTERISTICS
Percentage of Units – %
50 50
40 40
30 30
20 20
10 10
0 0
–5 –4 –3 –2 –1 0 1 2 3 4 5 –5 –4 –3 –2 –1 0 1 2 3 4 5
VIO – Input Offset Voltage – mV VIO – Input Offset Voltage – mV
Figure 6 Figure 7
50 Outliers: 50 Outliers:
(1) 19.2 µV/°C (1) 18.7 µV/°C
(1) 12.1 µV/°C 40 (1) 11.6 µV/°C
40
30 30
20 20
10 10
0 0
– 10 – 8 – 6 – 4 – 2 0 2 4 6 8 10 – 10 – 8 – 6 – 4 – 2 0 2 4 6 8 10
αVIO – Temperature Coefficient – µV/°C αVIO – Temperature Coefficient – µV/°C
Figure 8 Figure 9
TYPICAL CHARACTERISTICS†
VDD = 5 V
3 10
VDD = 4 V
8
VDD = 10 V
2 VDD = 3 V
6
4
1
2
0 0
0 –2 –4 –6 –8 – 10 0 – 5 – 10 – 15 – 20 – 25 – 30 – 35 – 40
IOH – High-Level Output Current – mA IOH – High-Level Output Current – mA
Figure 10 Figure 11
RL = 1 MΩ VID = 100 mV
VOH – High-Level Output Voltage – V
TA = 25°C VDD = 5 V
12 VDD – 1.8
10 VDD – 1.9
8 VDD – 2
VDD = 10 V
6 VDD – 2.1
4 VDD – 2.2
2 VDD – 2.3
0 VDD – 2.4
0 2 4 6 8 10 12 14 16 – 75 – 50 – 25 0 25 50 75 100 125
VDD – Supply Voltage – V TA – Free-Air Temperature – °C
Figure 12 Figure 13
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TYPICAL CHARACTERISTICS†
VDD = 5 V VDD = 10 V
650
IOL = 5 mA
TA = 25°C 450
TA = 25°C
600
550
400
VID = – 100 mV
500 VID = – 100 mV
VID = – 1 V
350
450 VID = – 2.5 V
400
300
VID = – 1 V
350
300 250
0 0.5 1 1.5 2 2.5 3 3.5 4 0 1 2 3 4 5 6 7 8 9 10
VIC – Common-Mode Input Voltage – V VIC – Common-Mode Input Voltage – V
Figure 14 Figure 15
100 100
0 0
0 –2 –4 –6 –8 – 10 – 75 – 50 – 25 0 25 50 75 100 125
VID – Differential Input Voltage – V TA – Free-Air Temperature – °C
Figure 16 Figure 17
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TYPICAL CHARACTERISTICS†
0.4
1
0.3
0.2
0.5
0.1
0 0
0 1 2 3 4 5 6 7 8 0 5 10 15 20 25 30
IOL – Low-Level Output Current – mA IOL – Low-Level Output Current – mA
Figure 18 Figure 19
LARGE-SIGNAL LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION DIFFERENTIAL VOLTAGE AMPLIFICATION
vs vs
SUPPLY VOLTAGE FREE-AIR TEMPERATURE
2000 2000
TA = – 55°C
1800 RL = 1 MΩ 1800 RL = 1 MΩ
TA = – 40°C
AVD – Large-Signal Differential
AVD – Large-Signal Differential
1600
Voltage Amplification – V/mV
1600
Voltage Amplification – V/mV
1400 1400
TA = 0°C VDD = 10 V
1200 1200
TA = 25°C
1000 1000
TA = 70°C
ÁÁ
800 800
ÁÁ 600 TA = 85°C
ÁÁ 600
AVD
ÁÁ ÁÁ
AVD
VDD = 5 V
400 400
TA = 125°C
200 200
0 0
0 2 4 6 8 10 12 14 16 – 75 – 50 – 25 0 25 50 75 100 125
VDD – Supply Voltage – V TA – Free-Air Temperature – °C
Figure 20 Figure 21
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TYPICAL CHARACTERISTICS†
VDD = 10 V 16
VIC = 5 V
TA = 25°C
See Note A
14
IIB 12
100
10
IIO
8
10
6
1 4
2
0.1
45 65 85 105 125 25 0
TA – Free-Air Temperature – °C 0 2 4 6 8 10 12 14 16
NOTE A: The typical values of input bias current and input offset VDD – Supply Voltage – V
current below 5 pA were determined mathematically.
Figure 22 Figure 23
ÌÌÌÌ
180 120
ÌÌÌÌ
VO = VDD/2 TA = – 55°C VO = VDD/2
160
ÌÌÌÌ
No Load No Load
100
ÌÌÌÌ
ÌÌÌÌ
140
I DD – Supply Current – µ A
I DD – Supply Current – µ A
TA = – 40°C
120
ÌÌÌÌ TA = 0°C 80
ÌÌÌÌ
TA = 25°C VDD = 10 V
ÌÌÌÌ
100 TA = 70°C
TA = 125°C 60
80
60 40
VDD = 5 V
40
20
20
0 0
0 2 4 6 8 10 12 14 16 – 75 – 50 – 25 0 25 50 75 100 125
VDD – Supply Voltage – V TA – Free-Air Temperature – °C
Figure 24 Figure 25
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TYPICAL CHARACTERISTICS†
SLEW RATE
SLEW RATE
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
0.07
0.07
AV = 1 VDD = 10 V RL = 1 MΩ
VIPP = 1 V CL = 20 pF
0.06 VIPP = 5.5 V
0.06 RL = 1 mΩ AV = 1
CL = 20 pF See Figure 1
TA = 25°C 0.05
SR – Slew Rate – V/ µs
0.05
SR – Slew Rate – V/ µs
0.03
0.03
VDD = 5 V
0.02
0.02 VIPP = 1 V
0.01 VDD = 5 V
0.01 VIPP = 2.5 V
0.00
0.00 – 75 – 50 – 25 0 25 50 75 100 125
0 2 4 6 8 10 12 14 16
TA – Free-Air Temperature – °C
VDD – Supply Voltage – V
Figure 26 Figure 27
1.4 10
AV = 1
1.3 9
VIPP = 1 V
VDD = 10 V RL = 1 MΩ 8
1.2 TA = 125°C
CL = 20 pF VDD = 10 V
VDD = 5 V TA = 25°C
Normalized Slew Rate
7
1.1 TA = – 55°C
6
1
5 VDD = 5 V
0.9
4
0.8
3
0.7 RL = 1 MΩ
2
See Figure 1
0.6 1
0.5 0
– 75 – 50 – 25 0 25 50 75 100 125 0.1 1 10 100
TA – Free-Air Temperature – °C f – Frequency – kHz
Figure 28 Figure 29
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TYPICAL CHARACTERISTICS†
VDD = 5 V VI = 10 mV
130
VI = 10 mV CL = 20 pF
130
B1 – Unity-Gain Bandwidth – kHz
100
90
90
70 80
70
50
60
30 50
– 75 – 50 – 25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16
TA – Free-Air Temperature – °C VDD – Supply Voltage – V
Figure 30 Figure 31
105 0°
Voltage Amplification
104 30°
Phase Shift
AVD
103 60°
ÁÁ 102 90°
ÁÁ
Phase Shift
AVD
ÁÁ
101 120°
A
1 150°
0.1 180°
1 10 100 1k 10 k 100 k 1M
f – Frequency – Hz
Figure 32
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TYPICAL CHARACTERISTICS†
10 5 0°
Voltage Amplification
10 4 30°
Phase Shift
AVD
10 3 60°
Á
10 2 90°
Á
Phase Shift
AVD
10 1 120°
Á
A
1 150°
0.1 180°
1 10 100 1k 10 k 100 k 1M
f – Frequency – Hz
Figure 33
34°
φ m – Phase Margin
38°
32°
36° 30°
28°
34°
26°
24°
32°
22°
30° 20°
0 2 4 6 8 10 12 14 16 – 75 – 50 – 25 0 25 50 75 100 125
VDD – Supply Voltage – V TA – Free-Air Temperature – °C
Figure 34 Figure 35
† Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
TYPICAL CHARACTERISTICS
33°
φ m – Phase Margin
125
31° 100
75
29°
50
27°
25
25° 0
0 20 40 60 80 100 1 10 100 1000
CL – Capacitive Load – pF f – Frequency – Hz
Figure 36 Figure 37
APPLICATION INFORMATION
single-supply operation
While the TLC27L4 and TLC27L9 perform well using dual power supplies (also called balanced or split
supplies), the design is optimized for single-supply operation. This design includes an input common-mode
voltage range that encompasses ground as well as an output voltage range that pulls down to ground. The
supply voltage range extends down to 3 V (C-suffix types), thus allowing operation with supply levels commonly
available for TTL and HCMOS; however, for maximum dynamic range, 16-V single-supply operation is
recommended.
Many single-supply applications require that a voltage be applied to one input to establish a reference level that
is above ground. A resistive voltage divider is usually sufficient to establish this reference level (see Figure 38).
The low input bias current of the TLC27L4 and TLC27L9 permits the use of very large resistive values to
implement the voltage divider, thus minimizing power consumption.
The TLC27L4 and TLC27L9 work well in conjunction with digital logic; however, when powering both linear
devices and digital logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 39); otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital
logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate; however, high-frequency applications may require RC decoupling.
VDD
R4
R1
R2 R3
VI – VREF = VDD
R1 + R3
+ VO
R4 + V
VO = (VREF – VI ) REF
VREF R2
R3 C
0.01 µF
APPLICATION INFORMATION
–
Power
Output + Logic Logic Logic Supply
–
Power
Output + Logic Logic Logic Supply
input characteristics
The TLC27L4 and TLC27L9 are specified with a minimum and a maximum input voltage that, if exceeded at
either input, could cause the device to malfunction. Exceeding this specified range is a common problem,
especially in single-supply operation. Note that the lower range limit includes the negative rail, while the upper
range limit is specified at VDD – 1 V at TA = 25°C and at VDD – 1.5 V at all other temperatures.
The use of the polysilicon-gate process and the careful input circuit design gives the TLC27L4 and TLC27L9
very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage
drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus
dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate)
alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude.
The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of
operation.
Because of the extremely high input impedance and resulting low bias current requirements, the TLC27L4 and
TLC27L9 are well suited for low-level signal processing; however, leakage currents on printed circuit boards
and sockets can easily exceed bias current requirements and cause a degradation in device performance. It
is good practice to include guard rings around inputs (similar to those of Figure 4 in the Parameter Measurement
Information section). These guards should be driven from a low-impedance source at the same voltage level
as the common-mode input (see Figure 40).
The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation.
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC27L4 and TLC27L9 result in a very low
noise current, which is insignificant in most applications. This feature makes the devices especially favorable
over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit
greater noise currents.
APPLICATION INFORMATION
– –
VI –
VO VO VO
VI + + VI +
output characteristics
The output stage of the TLC27L4 and TLC27L9 is designed to sink and source relatively high amounts of current
(see typical characteristics). If the output is subjected to a short-circuit condition, this high current capability can
cause device damage under certain conditions. Output current capability increases with supply voltage.
All operating characteristics of the TLC27L4 and TLC27L9 were measured using a 20-pF load. The devices
drive higher capacitive loads; however, as output load capacitance increases, the resulting response pole
occurs at lower frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 41). In many
cases, adding a small amount of resistance in series with the load capacitance alleviates the problem.
2.5 V
–
VO
+
VI
CL TA = 25°C
f = 1 kHz
VIPP = 1 V
– 2.5 V
APPLICATION INFORMATION
VDD C
VI + IP RP
VDD – VO –
Rp =
– VO IF + IL + IP
VO
IF IP = Pullup current +
required by the
operational amplifier
R2 (typically 500 µA)
R1 IL RL
feedback
Operational amplifier circuits nearly always employ feedback, and since feedback is the first prerequisite for
oscillation, some caution is appropriate. Most oscillation problems result from driving capacitive loads
(discussed previously) and ignoring stray input capacitance. A small-value capacitor connected in parallel with
the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC27L4 and
TLC27L9 inputs and outputs were designed to withstand – 100-mA surge currents without sustaining latch-up;
however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection
diodes should not, by design, be forward biased. Applied input and output voltage should not exceed the supply
voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators.
Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the
supply rails as close to the device as possible.
APPLICATION INFORMATION
latch-up (continued)
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
1/4
+ TLC27L4
500 kΩ VO1
–
5V
500 kΩ
–
VO2
+ 1/4
TLC27L4
0.1 µF 500 kΩ
500 kΩ
100 kΩ
VDD
100 kΩ
Set +
VO
100 kΩ
– 1/4
Reset
TLC27L4
33 kΩ
NOTE: VDD = 5 V to 16 V
APPLICATION INFORMATION
VDD
1/4
VI + TLC27L9
VO
–
VDD 90 kΩ
C
S1 X1
B
SELECT S1 S2 A TLC4066 1
1
AV 10 100 9 kΩ
C
S2 X2
Analog B
2
A Switch
2
1 kΩ
NOTE: VDD = 5 V to 12 V
10 kΩ
VDD
20 kΩ
VI –
VO
+
1/4
TLC27L4 100 kΩ
NOTE: VDD = 5 V to 16 V
APPLICATION INFORMATION
0.016 µF
5V
10 kΩ 10 kΩ
VI +
VO
0.016 µF
– 1/4
TLC27L4
R2
100 kΩ
VDD
R1
10 kΩ
VIA +
VO
VIB – 1/4
R1 TLC27L9
10 kΩ
R2
100 kΩ
ǒ Ǔ
NOTE: VDD = 5 V to 16 V
V
O
+
R2 V
R1 IB
V *
IA
www.ti.com 14-Oct-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TLC27L4ACD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 27L4AC Samples
TLC27L4ACDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 27L4AC Samples
TLC27L4ACN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC27L4ACN Samples
TLC27L4ACNE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC27L4ACN Samples
TLC27L4AID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 27L4AI Samples
TLC27L4AIDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 27L4AI Samples
TLC27L4AIN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TLC27L4AIN Samples
TLC27L4BCD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 27L4BC Samples
TLC27L4BCDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 27L4BC Samples
TLC27L4BCN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC27L4BCN Samples
TLC27L4BID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 27L4BI Samples
TLC27L4BIDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 27L4BI Samples
TLC27L4BIDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 27L4BI Samples
TLC27L4BIDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 27L4BI Samples
TLC27L4BIN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TLC27L4BIN Samples
TLC27L4CD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC27L4C Samples
TLC27L4CDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC27L4C Samples
TLC27L4CN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC27L4CN Samples
TLC27L4CNSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC27L4 Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TLC27L4CPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P27L4C Samples
TLC27L4CPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P27L4C Samples
TLC27L4CPWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 P27L4C Samples
TLC27L4ID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC27L4I Samples
TLC27L4IDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC27L4I Samples
TLC27L4IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC27L4I Samples
TLC27L4IN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TLC27L4IN Samples
TLC27L4INE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TLC27L4IN Samples
TLC27L4IPW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 P27L4I Samples
TLC27L4IPWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 P27L4I Samples
TLC27L9CD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC27L9C Samples
TLC27L9CDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC27L9C Samples
TLC27L9CN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 TLC27L9CN Samples
TLC27L9CNSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC27L9 Samples
TLC27L9ID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC27L9I Samples
TLC27L9IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC27L9I Samples
TLC27L9IN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 TLC27L9IN Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Apr-2023
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Apr-2023
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Apr-2023
TUBE
T - Tube
height L - Tube length
W - Tube
width
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Apr-2023
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TLC27L9CD D SOIC 14 50 505.46 6.76 3810 4
TLC27L9CN N PDIP 14 25 506 13.97 11230 4.32
TLC27L9ID D SOIC 14 50 505.46 6.76 3810 4
TLC27L9IN N PDIP 14 25 506 13.97 11230 4.32
Pack Materials-Page 4
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