Original Version
Storage Class Memory (SCM) is
Storage Class Memory (SCM) is
an emerging technology that aims
to provide a high-speed and
persistent storage solution that
overcomes the limits of traditional
volatile and non-volatile memory
technologies, especially in
computing-intensive applications
such as AI, 5G, and autopilot.
However, current SCM solutions
have limitations on high power
consumption, high variability, and
low storage density issues[1, 2].
To address these limitations,
researchers are exploring new
memory technologies such as
voltage-controlled magnetic
anisotropy (VCMA) magnetic
random-access memory (MRAM).
VCMA-MRAM is a non-volatile
memory technology that provides
fast read/write speed and low
power consumption by utilizing
voltage to modulate the energy
barrier and control the orientation
of magnetic domains[3].
Compared to Spin-Transfer-
Torque (STT) [4] and Spin-Orbit-
Torque (SOT) MRAMs [5],
VCMA-MRAM has different
advantages: (1) VCMA-MRAM
data writing is voltage-driven,
which reduces power
consumption [3]; (2) as a unipolar
device, only one polarity of the
voltage signal is required in
operation, which helps to reduce
the complexity of peripheral
Improved Version (Hemingway App)
Storage Class Memory (SCM) is an
an emerging technology that aims
to provide a high-speed and
persistent storage solution. SCM
overcomes the limits of traditional
volatile and non-volatile memory
technologies, especially in
computing-intensive applications
such as AI, 5G, and autopilot. Yet,
current SCM has limitations on
high power, high variability, and
low storage density [1, 2]. To
address these limitations,
researchers are exploring new
memory technologies such as
voltage-controlled magnetic
anisotropy (VCMA) magnetic
random-access memory (MRAM).
VCMA-MRAM is a non-volatile
memory technology that provides
fast read/write speed and low
power consumption. By utilizing
voltage, VCMA-MRAM can
modulate the energy barrier and
control the orientation of magnetic
domains[3]. Compared to Spin-
Transfer-Torque [4] and Spin-
Orbit-Torque MRAMs [5],
VCMA-MRAM has two
advantages. First, VCMA-MRAM
data writing is voltage-driven,
which reduces power consumption
[3]. Besides, as a unipolar device,
the operation only requires one
polarity of the voltage signal,
which helps to reduce the
complexity of peripheral circuit
design.
Third Version (Live Session)
emerging technology that aims to
provide a high-speed and persistent
storage solution. It overcomes the
limits of traditional memory
technologies, especially in
computing-intensive applications
such as AI, 5G, and autopilot.
However, current SCM has
limitations with respect to energy
efficiency, variability, and storage
density [1, 2]. To address these
limitations, researchers are
exploring new memory
technologies such as voltage-
controlled magnetic anisotropy
(VCMA) magnetic random-access
memory (MRAM). VCMA-
MRAM is a non-volatile memory
technology that provides fast
read/write speed and low power
consumption. By using voltage,
VCMA-MRAM can modulate the
energy barrier and control the
orientation of magnetic
domains[3]. Compared to Spin-
Transfer-Torque [4] and Spin-
Orbit-Torque MRAMs [5],
VCMA-MRAM has two
advantages: (1) VCMA-MRAM
has a reduced power consumption
due to it being voltage-driven [3];
(2) as a unipolar device, only one
polarity of the voltage signal is
required, which helps reduce the
complexity of peripheral circuit
designs.
circuit design.
Nevertheless, the design space of
VCMA-MRAM is constrained by
stochasticity and variability.
Intrinsic variability factors, such
as the precession stochasticity
during the data writing and the
tunneling probability while the
data reading, must be taken into
account when designing the
circuit [3]. Moreover,
manufacturing process variation,
as well as the memory array wires'
parasitic R/C and corresponding
IR drop also affect the design
space. In a VCMA-MRAM
matrix, the array size and
operating voltage pulse affect
power consumption, storage
density, and design performance.
Therefore, the viability of a
sufficient design space for
VCMA-MRAM is being studied.
This paper investigates the
sensitivity of the design space of
VCMA-MRAM by considering
both intrinsic and process-related
variability factors. To achieve this variability factors. To achieve
goal, we utilize a Verilog-A
model calibrated on our sample of calibrated on our manufactured
manufactured devices. Our study
focuses on array-level evaluations
with data writing and reading
considered separately at initial
relaxed write/read specifications:
error rate <5%. It provides
insights into voltage pulse
characteristics and array size
impact on operability, preparing
the ground for further research
Still, stochasticity and variability
constrain the design space of
VCMA-MRAM. VCMA has two
intrinsic variability factors: the
precession stochasticity during
data writing and the tunneling
probability while data reading.
These two factors must be taken
into account when designing the
circuit [3]. Moreover, process
variations, and IR drop caused by
memory array wires' parasitic R/C
also affect the design space. In a
VCMA-MRAM matrix, the array
size and voltage pulse affect
power, storage density, and design
performance. Thus, the viability of
enough design space for VCMA-
MRAM is being studied.
This paper investigates the
sensitivity of the design space of
VCMA-MRAM by considering
both intrinsic and process-related
this devices. Our study focuses on
goal, we use a Verilog-A model
devices. Our study focuses on
array-level evaluations with data
writing/reading at initial relaxed
specifications: error rate <5%. It
provides insights into voltage pulse operability. This sets the ground for
characteristics and array size
impact on operability. Which
prepares the ground for further
research toward product-grade
operation. The paper's structure is
Nevertheless, the design space of
VCMA-MRAM is constrained by
stochasticity and variability.
VCMA has two intrinsic variability
factors: precession stochasticity
during data writing and tunneling
probability while data reading.
These two factors must be taken
into account when designing
circuits [3]. Moreover, the design
space is also affected by process
variations and IR drops caused by
memory array wires' parasitic R/C.
In a VCMA-MRAM matrix, the
array size and voltage pulse affect
power, storage density, and design
performance. Thus, the viability of
enough design space for VCMA-
MRAM is being studied.
This paper investigates the
sensitivity of the design space of
VCMA-MRAM by considering
both intrinsic and process-related
variability factors. To achieve this
goal, we use a Verilog-A model
calibrated on our manufactured
array-level evaluations with data
writing/reading, initially with
relaxed specifications: error rate
<5%. It provides insights into
voltage pulse characteristics and
the impact of array size on
further research toward product-
grade operation.

toward product-grade operation.
The paper is structured as follows:
Section II provides the
motivation. After that, the
write/read design space analyses
are described in Sections III and
IV respectively. Finally, Section
V gathers the key conclusions.
In this study, we investigate the
sensitivity of the design space for
SCM applications utilizing
1Diode-1VCMA bit cells. Initial
statistical analyses of writing
PSW and reading BER are
performed to identify key
characteristics that impact the
design space for reliable designs.
Our sensitivity analyses
demonstrate how voltage pulse
amplitude, width, and slope
should be constrained under safe
boundaries, as well as explore the
maximum array size for robust
operation. Furthermore, we
analyze the impact of stochasticity
and process variations on the
device operation to explore the
array operation design space. Our
findings pave the way for the
development of robust 1Diode-
1VCMA-based SCM and other
large-scale memory scenarios.
like the below: Section II provides
the motivation. Sections III and IV
describe the write-and-read design
space analyses. Finally, Section V
gathers the key conclusions.
We investigate the sensitivity of
the design space for SCM utilizing
1Diode-1VCMA bit cells. Initial
statistical analyses of writing and
reading are performed to identify
key characteristics that impact the
design space for reliable designs.
We prove how voltage pulse
amplitude, width, and slope should
be constrained under safe
boundaries. Based on that, we also
explore the largest array size for
robust operation. Furthermore, we
analyze the impact of stochasticity
and process variations on the array
design space. Our findings pave
the way for the development of
robust 1Diode-1VCMA-based
SCM and other large-scale
memory scenarios.