IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 31, NO.

3, AUGUST 2018 371

Wafer Level Variability Improvement by Spatial

Source/Drain Activation and Ion Implantation
Super Scan for FinFET Technology
Yanzhen Wang , Yoong Hooi Yong, Bingwu Liu, Dibao Zhou, Mitsuhiro Togo, Dongil Choi, Jae Gon Lee,
Hsien-Ching Lo, Xinyuan Dou, Sipeng Gu, Shashidhar Shintri, Weihua Tong,
Vidmantas Sargunas, and Jorge Argandona

Abstract—In this paper, CMOS wafer level ring oscillator

frequency variability improvement >40% is demonstrated by
either spatial source/drain activation or ion implantation super
scan in FinFET technology. Yield improvement (up to 17%) is
verified with better within wafer uniformity and with no intrinsic
device performance degradation. Furthermore, the combination
of super scan and spatial source/drain activation is suggested
for optimized variability improvement benefits from individual
device type uniformity tuning (super scan) and all device type
uniformity tuning (from spatial S/D activation).
Index Terms—FinFET, CMOS integrated circuits, rapid ther-
mal annealing, semiconductor device ion implantation, electric
variables control.

I. I NTRODUCTION
S SEMICONDUCTOR technology approaches the lim- Fig. 1. Intrinsic (a) and systematic (b) variation in FinFET technology.
A its of Moore’s law, FinFET technology are used from
22nm node by Intel and it has been the main stream of
16/14/10nm nodes in order to maintain the ITRS trend. The
challenges remain for achieving controllable device charac-
teristics without performance degradation. The wafer level
variability has increased dramatically due to process flow
complexity over the past decade with new sources from pro-
cessing steps in lithography, etch, epi growth and strains or
stress in thin film [1]–[5]. Variability could be divided into
two categories, systematic and random (intrinsic) variation
as shown in Fig. 1. Random variation in Fig. 1a usually is
an uncertain component and is not predictive for electrical
variation, whereas systematic variation in Fig. 1b can cause
spatial dependency or correlation between process and elec- Fig. 2. Typical process variation in finfet technology (a) Fin CD variation
trical parameters. Physical and electrical variability can result and (b) gate CD variation.
in yield loss or degraded circuit performance. So improve-
ment in wafer level variability is critical for overall circuit
stability and manufacturing cost reduction. In this paper, the or N-type field effect transistor (NFET) Source/Drain) super
feasibility of variability improvement by spatial source drain scan approaches are explored for the first time in FinFET
rapid thermal anneal (RTA) activation, ion implantation (halo technology to compensate for upstream/downstream system-
atic process variations. The impact on device performance and
Manuscript received May 31, 2018; accepted June 7, 2018. Date of publi- wafer level yield improvement are also demonstrated.
cation June 13, 2018; date of current version August 2, 2018. (Corresponding
author: Yanzhen Wang.)
The authors are with Advanced Technology Development Group,
Globalfoundries, Malta, NY 12020-4400 USA (e-mail: yanzhen.wang@ II. D EVICE FABRICATION AND E XPERIMENTS
globalfoundries.com). FinFET devices were fabricated on Si substrates with 14nm
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. FinFET process technology. Silicon fins were formed using
Digital Object Identifier 10.1109/TSM.2018.2847040 dual patterning process with the challenge to form uniform
0894-6507 c 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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 372 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 31, NO. 3, AUGUST 2018
Fig. 3. Process variability contributors for NFET and PFET Vtsat variation
in FinFET technology.
Fig. 4. (a) RO frequency uniformity improvement from wafer center to edge;
(b) Schematic diagram of spatial S/D RTA by zone.
and straight silicon fins. Experimental and simulation results
show better device performance can be achieved with both uni-
form silicon fin pitch and profile [6]. Both fin bottom critical
dimension (BCD) and top critical dimension (TCD) varia-
tion within wafer contribute to electrical variation as seen
in Fig. 2, which is a new variation source compared to pla-
nar CMOS technologies. Junction related processes are other
important contributors. The NFET junction cavity, proximity
(also impacted from upstream spacer and etch process) and
epi growth SiP lateral width impact NFET electrical variation.
Similarly, P-type field transistor field (PFET) junction cavity,
proximity, spacer thickness and SiGe lateral width contribute
to PFET electrical variation. Fig. 3 shows both NFET and
PFET Vtsat variation components from each module: gate,
fin, junction and RMG. Fin CD variation contributes up to
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Fig. 5. N/P LVT Cov variability improvement by spatial S/D RTA.
Fig. 6. Wafer level yield improvement in each zone (each zone has equal
dice, Z1 is center zone and Z5 is edge zone).
∼65% for low Vt flavor (LVT) NFET Vtsat and up to ∼21%
in super low Vt flavor (SLVT) PFET Vtsat over total pro-
cess variation. Junction related processing usually results in
a zonal electrical variation signature within wafer. If a pro-
cess results in a left/right or bottom/top wafer signature, it
could be resolved by a two-step or multi-step process to reduce
or eliminate the signature. For zonal electrical variation, spa-
tial RTA (also called zonal RTA) at source/drain after gate,
fin and junction module is applied to compensate and then
improve wafer level electrical uniformity. Spatial RTA serves
as downstream process makeup to upstream process (includ-
ing Fin, gate, junction etc.) variations for electrical uniformity
improvement. First, electrical parameters to RTA temperature
sensitivity are collected at wafer level and a zone to zone elec-
trical delta is calculated. Then, the temperature delta from zone
to zone can be defined from the electrical delta and sensitivity.
Halo or S/D implantation super scan is another effective way to
improve wafer level electrical variability. The benefit of using
S/D implantation super scan is to adjust variability for differ-
ent device types (N or PFET). Halo implantation super scan
can also adjust variability for different Vt flavor devices. Those
benefits are not available by spatial S/D RTA since same tem-
perature delta applies to all device types. Similarly, sensitivity
of electrical parameters versus implantation dose is collected
and then zone to zone implantation dose delta is defined for
implantation super scan recipe generation. In this experiment,
the core device variation improvement is main focus since
spatial RTA has less impact on EG (I/O devices) and SRAM
device due to larger gate length than core devices.
 WANG et al.: WAFER LEVEL VARIABILITY IMPROVEMENT BY SPATIAL SOURCE/DRAIN ACTIVATION AND ION IMPLANTATION SUPER SCAN
Fig. 7. Chip circuit SIDD/frequency uniformity improvements across wafer.
TABLE I
K EY ET PARAMETERS VARIABILITY I MPROVEMENT (W ITHIN WAFER )
W ITH S PATIAL S/D RTA VS THE C ONTROL . N UMBERS IN
TABLE IS AVERAGE OF 2/4/40 FIN D EVICES
III. R ESULTS AND D ISCUSSIONS
A. Spatial S/D RTA Activation
To compare electrical variability within different splits, full
map device electrical data were collected after final metal
layer. Electrical variability improvement is a global effect
and more representative in ring oscillator (RO) structures
than single FETs. Fig. 4 and Fig. 5 show RO frequency
and N/P overlap capacitance (Cov) uniformity improvement.
Fig. 4 (b) shows a schematic diagram of a typical five-zone
spatial S/D RTA activation with temperature delta defined from
electrical zone to zone delta. In the control (black curve),
the wafer center has a low frequency compared to the donut
region. With higher S/D RTA temperature at the wafer cen-
ter, frequency is increased by an overall total Ieff (NFET
Ieff + PFET Ieff) boost. By lowering S/D RTA temperature
in the donut (zone of radius ∼120mm), a lower frequency
is achieved and overall wafer level frequency distribution by
radius is smoother and within wafer uniformity is improved.
Fig. 5 also shows the impact of RTA on both NFET and
PFET Cov. It shows that spatial RTA has a more signifi-
cant impact on NFET Cov than PFET because NFET dopant
As is relatively easier to diffuse in NFET epi (eSiP) than
PFET dopant B in PFET epi (eSiGe). Table I shows unifor-
mity improvement in key electrical parameters with spatial S/D
RTA compared to the control including RO direct drain quies-
cent current (IDDQ) . N/PFET Idsat uniformity is defined as
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373
IDU = deviation/median. And frequency uniformity is defined
in the same way. RO Iddq (in log scale) is compared by stan-
dard deviation reduction. By spatial S/D RTA with zone to
zone compensation, better wafer level electrical uniformity is
achieved. Table I lists the average uniformity improvement
of devices with different fin numbers. It demonstrates that
NFET /PFET Idsat uniformity is improved (average of all
three Vt flavors) by 21%/13% compared to the control and
a best improvement of over 30% is achieved for both NFET
and PFET in 40 fin devices. For RO frequency, uniformity is
improved by ∼24% on average with the best improvement of
∼40% in regular Vt flavor (RVT). Electrical uniformity could
be further improved by optimizing the spatial S/D RTA recipe
from zone to zone temperature delta tuning.
Wafer level yield improvement is demonstrated and com-
pared as shown in Fig. 6. All five zones have equal number of
dice and with zone 1 as wafer center and zone 5 as wafer edge.
Yield improvement (up to 17%) is shown in all zones, and is
especially significant for zones 1, 2 and 3 from electrical vari-
ability improvement. Chip circuit frequency and static leakage
at circuit level (SIDD) by radius is compared in Fig. 7. The
red curve with spatial S/D RTA shows variability improvement
with flatter distribution from wafer center to edge compared to
the control, which is the same improvement trend as seen in
single FET and RO. Intrinsic performance is compared to the
control as in Fig. 8. Analysis shows PFET performance is com-
parable between the control and spatial S/D RTA split. NFET
performance is ∼ −1% lower in spatial S/D RTA split com-
pared to the control, which is within the variation range. One
can conclude that spatial S/D RTA has no significant impact
on device intrinsic performance for both NFET and PFET.
B. Halo and S/D Implantation Super Scan
Another methodology for within wafer variability improve-
ment is use of an ion implantation super scan. In general, the
super scan changes ion beam scan rate to achieve different
ion doses at different zones. Compared to spatial S/D RTA,
which is applied to all devices types on wafer, halo super scan
could be used to tune the electrical uniformity of specific Vt
flavor and S/D implantation super scan is for either NFET or
PFET. In this experiment, NFET S/D implantation (apply to
 374 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 31, NO. 3, AUGUST 2018
Fig. 8. Wafer level LVT N/PFET performance probability distribution.
Fig. 9. LVT NFET halo super scan ion implantation simulation (different
color for dose difference by zone).
Fig. 10. RVT and LVT RO frequency uniformity improvement from wafer
center to wafer edge from halo super scan.
all NFET devices) and halo implantation super scan (RVT or
LVT for both NFET and PFET) are explored.
Electrical sensitivity versus implantation dose are collected
and each zone (here 5 zones) implantation dose is proposed
based on electrical offsets between different zones. Simulation
work is done to verify if the implantation tool can achieve the
desired dose for each zone as in proposed super scan recipes.
Fig. 9 shows typical LVT NFET dose distribution for a five
zone implantation super scan with smooth transition from zone
to zone and dose in each zone is close to expectation.
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Fig. 11. RVT NFET Ieff trend by zone with halo implant super scan vs
the control (halo dose overcompensation and RVT NFET Ieff center to edge
trend reversed).
Fig. 12. LVT NFET Ieff trend by zone with NFET S/D implantation super
scan vs the control (flatter center to edge LVT NFET Ieff trend from NFET
S/D implantation super scan).
1) Halo Super Scan for RVT/LVT NFET and PFET:
Fig. 10 shows RVT/LVT frequency improvement from RVT
and LVT halo super scan for both N/PFET. For LVT, overall
frequency variability is improved and within wafer frequency
variation shows ∼50% reduction. While for RVT, frequency
uniformity is also improved but the trend from wafer center to
edge is reversed with halo super scan compared to the control.
This is because RVT NFET halo dose overcompensation from
super scan as shown in Fig. 11 in the initial experiment design.
To further improve RO frequency uniformity, RVT NFET halo
 WANG et al.: WAFER LEVEL VARIABILITY IMPROVEMENT BY SPATIAL SOURCE/DRAIN ACTIVATION AND ION IMPLANTATION SUPER SCAN
Fig. 13. LVT NFET Cov trend by zone with NFET S/D implantation
super scan vs the control (flatter center to edge LVT NCov from NFET S/D
implantation super scan).
implantation super scan recipe need to be further improved.
We recalculated based on this experiment learning for opti-
mized halo dose but did not conduct the experiment yet due
to resource limitation. Halo super scan does not change the
Cov profile significantly. Uniformity improvement is mainly
driven by Vtsat uniformity improvement across wafer from
halo implantation tuning.
2) NFET S/D Implantation Halo Super Scan: NFET S/D
implantation super scan can be used for only NFET uni-
formity improvement in the case where NFET and PFET
have a significant uniformity difference. Fig. 12 shows LVT
NFET Ieff uniformity improvement results from NFET S/D
implantation super scan. NFET Ieff zone to zone median pro-
file is much flatter compared to the control. The table in
Fig. 13 shows the average RVT/LVT NFET Ieff uniformity
improvement is ∼ 21%/33% (Ieff uniformity is calculated by
deviation/median) and improvement of up to 31% and 40%
for RVT/LVT NFET Ieff with 40fin. S/D implantation super
scan has an impact on dose diffusion and the NFET Cov dis-
tribution profile is changed as shown in the comparison of
Fig. 13 (a) and (b). With an optimized NFET S/D implanta-
tion super scan recipe, NFET Cov uniformity is significantly
improved and NFET electrical uniformity benefits from NFET
Cov variability improvement.
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375
Another benefit from ion implantation super scan is that it’s
not limited to zonal wafer signature by radius. Current super
scan tool can have more flexible zone definition besides zone
by radius. Combination of spatial S/D RTA and ion implan-
tation super scan could be used to achieve optimized within
wafer uniformity by combining all device type uniformity tun-
ing (from spatial S/D RTA) and specific device type uniformity
tuning (from ion implantation super scan).
IV. C ONCLUSION
Methodologies using spatial source/drain activation or ion
implantation super scan to improve within wafer electri-
cal variation are demonstrated in FinFET technology. Wafer
level uniformity improvement is verified using either spa-
tial S/D RTA or ion implantation super scan. Wafer level
yield is improved with better electrical uniformity and no
performance degradtion, which is important for manufacturing
cost reduction.
ACKNOWLEDGEMENT
The authors would like to thank support from fab 8 team at
Malta, NY and also Steve Morley, Wei Zou, Michael Ward,
Scott Falk and David Edwards in Applied Materials for super
scan experiment support. Especially they would like to thank
Scott Falk for super scan implantation dose simulation work.
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Authors’ photographs and biographies not available at the time of publication.