Electronic Devices and Circuit Theory 11th

Edition by Boylestad Nashelsky ISBN

0132622262 9780132622264
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MULTIPLE CHOICE. Choose the one alternative that best completes the statement or answers the question.
1) A JFET can be biased in several different ways. The common method(s) of biasing an n- 1)
channel
JFET is(are) ________.
A) fixed-bias configuration B) self-bias configuration
C) voltage-divider bias configuration D) All of the above

2) In a self-bias circuit for an n-channel JFET transistor the se1f-bias line 2)

________.
A) is slanted and passes through origin
B) is slanted and passing through the ID and the V GS axis on the positive
side
C) is straight left and right parallel to the V GS axis
D) is straight up and down parallel to the ID axis

3) In a fixed-bias circuit for an n-channel JFET transistor the bias line ________. 3)
A) is slanted and passing through the ID and the V GS axis on the positive
side
B) is straight left and right parallel to the V GS axis
C) is slanted and passes through origin
D) is straight up and down parallel to the ID axis

4) Calculate the quiescent gate-to-source voltage for this circuit if IDQ = 2.8
mA.

1
 4)

A) V GSQ = -3.6 V B) V GSQ = 3.6

V C) V GSQ = -1.38 V D) V GSQ =
1.8 V

2
5) Calculate the drain-gate voltage for this voltage-divider bias circuit if IDQ = 2.8 5)
mA .

A) V DG = 8.42 V B) V DG = 6.42 V C) V DG = 7.42 V D) V DG = 5.42 V

6) Calculate IDQ for this self-bias depletion mode MOSFET transistor amplifier if V GSQ = - 6)
4.625 V.

A) IDQ = 1.9 mA B) IDQ = 1.85 mA C) IDQ = 1.3 mA D) IDQ = 1.5

mA

7) In the enhancement type of MOSFET the channel is formed when the gate-to-source 7)
voltage
________.
A) is less than the threshold voltage B) exceeds the pinch-off
voltage
C) is less than the pinch-off voltage D) exceeds the threshold
voltage

3
8) Calculate the quiescent drain current for this circuit if V DS = 7.07 8)
V.

A) IDQ = 3.3 mA B) IDQ = 2.97

mA C) IDQ = 2.5 mA D) IDQ =
3.37 mA
9) Calculate the quiescent collector current for this circuit. 9)

A) ICQ = 1.9 mA B) ICQ = 2.1 mA C) ICQ = 2.3 mA D) ICQ = 1.63

mA

4
10) Calculate the quiescent collector-to-emitter voltage for the BJT in this circuit if V GSQ = - 10)
3.65 V.

A) V CE = 5.11 V B) V CE = -4.14 V C) V CE = 7.78 V D) V CE = 4.34 V

11) Calculate the voltage at the drain of the JFET in this combination network. 11)

A) V D = 3.5 V B) V D = 4.14 V C) V D = 8.22 V D) V D = 12.58

V

12) Generally, it is a good design practice for linear amplifiers to choose the operating point 12)
that is
approximately ________.
A) near the origin B) near the cut-off region
C) in the center of the active region D) near the saturation region

13) The analysis that we mostly work with is that of the n-channel device. For p-channel devices C)
the transfer curve employed is the ________ image and the defined current directions are identi
________. cal;
A) mirror; reversed B) identical; the same rever
sed
5
 D) mirror;
10) Calculate the the same collector-to-emitter voltage for the BJT in this circuit if V GSQ = -
quiescent 10)
13)
3.65 V.

6
14) It is important to remember that when the JFET is used as a voltage variable resistor, which is 14)
one of its practical applications, the voltage V DS is ________ V DS(max) and |V GS| is
________ |V P|.
A) very much less than; very much less than
B) very much greater than; very much less than
C) very much greater than; very much greater than
D) very much less than; very much greater than

15) The simplest biasing arrangement for the n-channel JFET is ________. 15)
A) variable bias B) fixed bias
C) drain-feedback bias D) voltage-divider
bias

16) The fixed-bias technique requires ________ power supplies. 16)

A) 4 B) 1 C) 3 D)
2

17) A JFET has the following ratings: V P = -2 V to -5 V and an IDSS = 4 mA. The device is being 17)
used in a fixed-bias circuit with a gate supply voltage of V GG = 1 V. What is the difference
between the minimum and maximum values of ID values for the circuit?
A) 1.56 mA B) 1.65 mA C) 3.6 mA D) 2.6 mA

18) The self-bias configuration develops the controlling gate-to-source voltage across a 18)
resistor introduced in the ________.
A) gate leg B) source leg
C) drain leg D) None of the above

19) A characteristic of voltage divider-bias in FET circuits is ________. 19)

A) the gate current is zero B) the voltage drop across R2 is
V GS
C) the current in both R 1 and R2 is the same D) A and C only

20) When using voltage divider-bias in FETamplifiers, increasing the size of the source resistor 20)
results in ________.
A) more positive of V GS B) a larger value of drain current
C) lower quiescent IDvalues D) All of the above

21) The primary difference between JFETs and depletion-type MOSFETs is ________. 21)
A) depletion-type MOSFETs can have positive values of V GS and levels of ID that exceed
IDSS B) depletion-type MOSFETs can have only positive of V GS
C) JFETs can have only positive values of V GS
D) JFETs can have positive values of V GS and levels of drain current that exceed IDSS

22) ________ biasing may be used with D-MOSFETs but not with JFETs. 22)
A) Gate-cutoff B) Zero C) Current-source D) Gate-
drain

23) A popular arrangement for enhancement type MOSFET biasing is

________.
7
A) fixed bias B) source-resistor 23)
bias
C) drain-feedback biasing D) All of the above

8
24) An E-MOSFET has values of V GSth = 2 V and ID(on) = 8 mA when V GS = 10 V. What is the 24)
value of k for the device?
A) 0.0001
B) 80
C) 0.000125
D) Cannot be determined from the information given

25) An E-MOSFET has values of V DD = 14 V and RD = 2 kΩ. . The device is being used in a 25)
circuit that has a value of V GS = 6 V. What is the value of ID for the circuit?
A) 0 mA B) 1 mA C) 4 mA D) 13.33 mA

26) Which of the following biasing circuits can be used with E-MOSFETs? 26)
A) drain-feedback bias B) current-source
bias
C) self bias D) zero bias

27) Generally, it is good design practice for linear amplifiers to have operating points that 27)
close to
________.
A) the midpoint of the load line B) are close to saturation level
C) the cut-off region D) None of the above

28) This graphical solution represents ________. 28)

A) voltage-divider bias for an n-channel JFET

B) fixed-bias configuration for an n-channel
JFET.
C) self bias for an n-channel
JFET D) None of the above

6
29) This graphical solution represents 29)
________.

A) voltage-divider bias for an n-channel

JFET B) self bias for an n-channel JFET
C) fixed bias for an n-channel
JFET D) None of the above
30) Which of the following is true for this circuit? 30)

A) V G is measured between the gate and

common. B) V G is always close to +0.7 V.
C) V G is measured between the gate and source
terminals.
D) V G is equal to the voltage across R S.

7
31) Which one of the following statements about this circuit is 31)
true?

A) V GS is measured between the gate and source

terminals. B) V GS is always close to +0.7 V.
C) V GS is equal to the voltage across R S.
D) V GS is measured across R 2.

32) Which of the following equations properly characterize the value of V DS for this 32)
circuit?

A) V DS = V DD - ID R D + R S B) V DS = V R1 + V R2 - ID R D +
RS C) V DS = V D - V S D) All of the above

8
33) Which of the following expressions is correct for this 33)
circuit?

A) V GS = V G - IS RS B) V GS = V G -
V S C) V GS = V G - ID RS D) All of the
above

9
Answer Key
Testname: UNTITLED111

1) D
2) A
3) D
4) C
5) A
6) B
7) D
8) A
9) D
10) D
11) D
12) C
13) A
14) A
15) B
16) D
17) A
18) B
19) D
20) C
21) A
22) B
23) C
24) C
25) C
26) A
27) A
28) B
29) B
30) A
31) A
32) D
33) D

10