EXCEL REVIEW CENTER ECE REVIEW COURSELogic circuits- ELECTRONICS I
Sample Problems Boolean Algebra
Simplify the following
1. x(x+y)
2. x + xy
3. xy + xz +yz
4. (x + y ) (x + z ) ( y + z )
5. Find the complement of the function F =
X YZ + X Y Z
K – Map
Simplify the following
6. F ( x, y, z) = ∑ (3,4,6,7)
7. F (w,x,y,z) = ∑
( 0,1,2,4,5,6,8,9,12,13,14)
Simplify the Boolean function
8. F (w,x,y,z) ∑ (1, 3, 7, 11, 15) with D
(w,x,y,z) = ∑ (0,2,5)
Sample Problems Logic Circuits
Problem 1
A standard TTL gates have the following
values for the currents: =400 µA, IIH = 40 µA,
IOL = 16 mA, IIL = 3.2mA. What is the
maximum fan-out of the logic gate?
Problem 2 1. The mother flip-flop since most of the
A certain TTL NAND gate has a noise margin flip-flops is constructed from it.
of 0.5 V. what is the voltage transition width A. RS C. T
of the gate if the voltage logic swing is 2.5V, B. JK D. D
VOH = 3.5 V, VIL = 1.5 V.
2. The states of the flip-flop before the
Problem 3 occurrence of a clock pulse.
A standard TTL NAND has VOH = 2.5 VOL = A. Present state C. current input
VIH = 1.8 V and VIL = 0.8 V. what is the noise B. Next state D. present input
margin of the gate?
3. A flip-flop that ignores the pulse while
Problem 4 it is at constant level but triggers only
The delays of a standard TTL gate with a load during the negative transition of the
resistance of 400ohms and a load capacitance clock signal.
of 15 pF are tPHL = 11ns. What is the average A. Edge-triggered
propagation delay of the system if 3 gates are B. Negative edge-triggered
connected in cascade? C. Positive edge triggered
D. T-flip-flop
Problem 5
A standard TTL NAND gates uses a supply 4. A system that is added to CLC for form
voltage of 5 V and has current drains ICCH = a sequel logic circuit.
1mA. What is the average power dissipation of A. ROM C. counter
an IC that has four NAND gates? B. Storage D. RAM
Problem 6 5. A combinational logic circuit that
Shifting the binary number to the left by two accepts in unique input lines and 2n
places is equal to increasing the magnitude of unique output lines.
a number by how much in decimal? A. Decoder C. SLC
B. Encoder D. CLC
Take Home Exam
EXCEL REVIEW CENTER ECE REVIEW COURSELogic circuits- ELECTRONICS I
6. Which of the following logic gates can
be built using a single transistor?
A. NAND gates C. AND gates
B. OR gates D. NOT gates
7. What input conditions will result in a
low output for an OR gate?
A. At least one input is low
B. All input are high
C. No inputs are high
D. One or more inputs are high
8. What input values will cause an AND
logic gate to produce a high output?
A. All inputs are high
B. At least one input is low
C. All inputs are low
D. At least one input is high
9. Exclusive OR logic gates can be
constructed from what other logic
gates?
A. OR gates only
B. OR and NOT gates
C. AND NOT gates
D. AND, OR and NOT gates
10. How many NAND circuits are
contained in a 7400 QUAD two input
NAND IC?
A. Two C. four
B. Eight D. one 16. The L series of TTL gates dissipates
less power because their internal
11.For what condition is the output of the resistors have___value of resistance
OR logic function different from the than other TTL series gates.
output of an XOR logic function? A. Larger C. the same
A. When both inputs are high B. Smaller D. none of the above
B. When one input is low and the other
input is HIGH 17. A digital logic device used as buffer
C. When both inputs are low should have what input / output
D. Never, there is no difference in characteristics?
outputs A. High input impedance and low
output impedance.
12. Which of the following digital logic B. Low input impedance and low output
technologies has the highest speed? impedance
A. IIL C. ECL C. High input impedance and high
B. NMOS D. CMOS output impedance
D. Low input impedance and high input
13. Which digital logic technology impedance.
dissipates the least power?
A. PMOS C. CMOS 18. What are the symptoms of an internal
B. NMOS D. ECl IC short circuit?
A. The circuit input or output is stuck at
14. Which digital IC package types make either a low or high logic level
the most efficient use of PCB space? B. The circuit input is stuck at a low
A. Flat pack C. DIP logic level
B. SMT D. PLC C. Either the circuit input is stuck a
high logic level.
15. Which of the following utilizes non- D. Either the circuit input or output is
saturated transistors to increase speed? stuck at low logic level.
A. IIL C. NMOS
B. PMOS D. ECL 19. What is required when interfacing two
different logic families?
EXCEL REVIEW CENTER ECE REVIEW COURSELogic circuits- ELECTRONICS I
A. An inverter C. a level-shifter
B. A buffer D. a phase splitter 24.A truth table for a digital logic circuit
20. What two quantities must be
compatible when interfacing two
different logic families?
A. Only the current
B. Only the voltage
C. Both current and voltage
D. Both power and impedance
21. LS TTL logic gates exhibit lower __
and higher ____than the standard TTL
devices.
A. Supply voltage and cost
B. Power, speed
C. Cost, speed
D. None of the above
22.TTL, ECL, and IIL are all examples of
____ digital logic devices.
A. MOS C. bipolar
B. NMOS D. PMOS
23. Where does most internal digital IC
logic gate failure occur?
A. At the circuit input
B. At the circuit output
C. At either the input or output of the
circuit
D. Somewhere between the input and
output of the circuit
with three inputs will have how many
input combinations?
A. Ten C. eight
B. Four D. two
25.What combination of test equipment is
most effective at isolating an external
short circuit on a printed circuit board
containing digital IC’s?
A. An oscilloscope and a logic clip
B. A logic pulser and ac current tracer
C. A logic pulser and a multimeter
D. An oscilloscope and multimeter
26. Which places of digital IC test
equipment are used to isolate a clock
signal problem?
A. A logic pulser and a logic clip
B. A logic probe and an oscilloscope
C. A logic pulser and a logic probe
D. A current tracer and an oscilloscope
27. What combination of digital IC test
equipment is most efficient for isolating
internal IC open circuit problems?
A. A logic pulser and a logic clip
B. A logic probe and an oscilloscope
C. A logic pulser and a logic probe
D. A current tracer and an oscilloscope
28. Which of the following is not a good
technique to use when desoldering or
soldering a component into a PCB?
A. Using solder wick
B. Using a grounding strap
C. Applying as much heat as possible
D. Double checking the components
orientation
29. Why is grounding strap required when
handling digital Ics?
A. To protect the circuit from high
temperature
B. To protect the technician from high
voltages
C. To protect the technician from high
currents
D. To protect the circuit from high
voltage
30. A (n) ____is the most efficient piece of
test equipment to use when examining
digital waveforms.
A. Logic pulser C. oscilloscope
B. Current tracer D. logic clip
31. The master timing signal in a digital IC
system is called ____signal.
A. Dynamic C.frequency
B. Clock D. period
EXCEL REVIEW CENTER ECE REVIEW COURSELogic circuits- ELECTRONICS I
32. A (n) is the most effective piece of
equipment for detecting short circuit 38.A memory element that temporarily 44. A decimal digit is called
problems store the information A. Decimal C. bit
A. Logic pulser C. current tracer A. ROM C. RAM B. Byte D. dit
B. Oscilloscope D. logic probe B. PROM D. EPROM
45.An n bit binary parallel adder requires
33. A logic pulser generates a ____ 39. A T flip-flop can be constructed by in the design.
A. High logic level connecting the inputs of a ____flip-flop. A. n full adders
B. A single pulse A. JK C. RS B. n half adders
C. Pulse train B. SR D. D C. n half subtractor
D. A single pulse or a pulse train D. n half adder and n full adder
34. A circuit that stores a fixed set of 40. A process in which a flip-flop states 46.A magnitude comparator has 22n entries
information. stays indefinitely until directed by an in the truth table where n =
A. Flip-flop C. ROM input signal to change states. A. no. of inputs
B. RAM D. DRAM A. Clocking C. timing B. no. comparator bits
B. Delaying D. latching C. no. of outputs
35. There are_____flip-flops for a 3 bit D. no. inputs and outputs
binary counter. 41. A flip-flop which follows it input state
A. 5 C. 4 in the next state. 47.An address bus that is 2n or 216 wide
B. 3 D. 6 A. D C. T allows for a maximum number of
B. JK D. RS memory locations of:
36.A graphical representation of a state A. 16,384 locations
table 42. A____is an arithmetic circuit that B. 65,536 locations
A. Transition table generates the binary sum of three C. 32,768 locations
B. State equations binary digits. D. That depends on the memory size
C. State assignment A. Full adder C. full subtractor
D. State diagram B. Half subtractor D. half adder 48.n designing an 8 x 2 ROM how many
input lines are needed?
37. A SLC that goes through a binary 43. Digital multiplexer conventional size A. 3 C. 2
sequence of states specification is B. 8 D. 4
A. Counter C. BCD counter A. N x 2n C. 2n x n
B. Binary counter D. registers B. 2n x 1 D. 1 x 2n
EXCEL REVIEW CENTER ECE REVIEW COURSELogic circuits- ELECTRONICS I
49.The term used to describe the input of
decoders in MSI circuits
A. word C. keying
B. address D. logic
50.In designing a 16 x 1 multiplexer, how
many selection lines are needed?
A. 2 C. 4
B. 16 D. 1
51.A memory register allows access to
specific memory locations and its
number of bits (width) is determined by:
A. number of specific locations
B. addresses for input and output ports
C. number of bits in the address bus
D. all of these
52.A program counter register is part of a
microprocessor that:
A. stores the address of the instruction
being fetched from memory
B. contains the program being read
from the memory
C. produces the program based on the
memory count
D. all of these
53.A mnemonic designation is one which
is:
A. an alphabetical abbreviation
B. easy to understand
C. related to certain key words
D. all of these
54.Arithmetic instructions are classified as
instructions which:
A. add, subtract, multiply or divide data
B. add, subtract, increment or
decrement data
C. arithmetically move data into the
accumulator
D. accumulate data in the accumulator
55.What is the purpose of the decoder’s
inputs?
A. To allow the decoder to respond to
the inputs to activate the correct
output gate
B. To disable the decoder outputs so
that all outputs will be inactive
C. To disable the inputs and activate all
outputs
D. Both a and c.
56.The program counter and address
register work together so that:
A. the program counter addresses the
next instruction
B. the program counter counts the next
instructions and stores it in the
address register
C. the program counter steps to the next
instruction using the address register
to keep track
D. all of these
57.Input/output instructions are classified
as instructions which:
A. compare input and output device
data
B. control input and output devices
C. process input and output device data
D. change input and output devices
58.Encoders are combinational logic
circuits that accept one or more inputs
and:
A. produce a coded output signal
B. develop an encoder priority
C. generate an ACSII coded output
D. all of these
59.the popular 4-line-to-10-line decoder
actually performs what function?
A. converts 4 lines of code into 10 lines
B. converts 4 lines of binary into
decimal
C. converts 4 bit-binary into decimal
number
D. all of these
EXCEL REVIEW CENTER ECE REVIEW COURSELogic circuits- ELECTRONICS I