CCB 1223/ X4 (1-3)

DIGITAL LOGIC
CCB1223
ASSIGNMENT 2
Total Marks: 10%
Full Marks: 40

Q1. Sketch the complete timing diagram for the 5-stage synchronous binary counter in
Figure 1.

Figure 1

(5 marks)

Q2. The waveforms in Figure 2 are applied to the counter CTEN, CLR, and CLK inputs as
indicated. Draw the counter output waveforms, Q0, Q1, Q2 and Q3 in proper relation to
these inputs. The CLR input is asynchronous.

Figure 2
(5 marks)

1
Q3. You apply a 5 MHz clock to the cascaded counter in Figure 3 and measure a frequency
of 76.2939 Hz at the last RCO output. State whether this correct or not. If not, state the
problem.

Figure 3
(7 marks)
Q4. Modify the design of the counter in Figure 4 to achieve a modulus of 30,000.

Figure 4
(7 marks)

Q5. Use 74HC195 4-bit shift registers as shown in Figure 5 to implement a 16-bit ring
counter. Show all the connections.

Figure 5
(3 marks)

2
Q6. Based on the waveforms in Figure 6(a), determine the most likely problem with the
register in part (b) of the figure.

Figure 6

(3 marks)

Q7. For the ring counter in Figure 7, sketch the waveforms for each flip-flop output with
respect to the clock. Assume that FF0 is initially SET and that the rest are RESET.
Show at least ten clock pulses.

Figure 7

(5 marks / markah)

Q8. Determine the state of the register in Figure 8 after each clock pulse if it starts in the
101001111000 state.

Figure 8
(5 marks)