Registers & Counters

Md. Zubair Alam Emon

 Registers
• A register is a group of flip-flops, each of which stores 1-
bit of information
 4-bit Simple Register

A0 A1 A2 A3

D Q D Q D Q D Q

C R QN C R QN C R QN C R QN

Clr ● ● ●
● ● ●
Clk

I0 I1 I2 I3
• Works at positive edge.
• Stores 4 bit information.
• Parallel output
When Clr=0 ; A0=A1=A2=A3=0
For normal operation, Clr must be equal to 1.
 4-bit Register w/ Parallel Load
A0 A1 A2 A3

D Q ● D Q ● D Q ● D Q ●

C R QN C R QN C R QN C R QN

Clr ● ● ●
● ● ●
Clk

● ● ●● Load
● ● ●

I0 I1 I2 I3
When load = 0, A is unchanged; When load =1, A=I
 4-bit Shift Registers
• Serial Input Serial Output (SISO)
SI SO
D Q D Q D Q D Q
Serial Serial
Input Output
C R QN C R QN C R QN C R QN

Clr ● ● ●
● ● ●
Clk

SI SO ● SI SO
Shift Registers Shift Registers

Serial Transfer from

Reg A to Reg B
Clock
●
Shift Control CLK

Clock

Shift Control

CLK
T1 T2 T3 T4
 Serial Transfer

Timing Pulse Shift Register A Shift Register B

Initial value 1 0 1 1 0 0 1 0

After T1 1 1 0 1 1 0 0 1

After T2 1 1 1 0 1 1 0 0

After T3 0 1 1 1 0 1 1 0

After T4 1 0 1 1 1 0 1 1
• Shift Register B looses it’s initial content/ information. To avoid this a
3rd register maybe placed
 Serial Addition
SI
Shift Control SO
● Shift Register A
● x S
CLK
y FA
SI z C
Serial input SO
● Shift Register B
●

Q D

QN R C

Clear

• New values/numbers in Shift Register B are accumulated and stored in Shift Register A.
 State Table for Serial Addition
Present Next Flip-Flop
State Inputs State Output Inputs
Q x y Q S JQ KQ
0 0 0 0 0 0 X
0 0 1 0 1 0 X
0 1 0 0 1 0 X
0 1 1 1 0 1 X
1 0 0 0 1 X 1
1 0 1 1 0 X 0
1 1 0 1 0 X 0
1 1 1 1 1 X 0

JQ = xy KQ = x’y’ = (x + y)’ S = x y  Q
 Another form of Serial Adder
SI
Shift Control SO = x
● Shift Register A ●
●
CLK ●
●
SI
Serial input SO = y
● Shift Register B ●
●
Clear
 Serial Addition
SI
Shift Control ● Shift Register A
SO = x ●
CLK ●
●
●
SI
Serial input SO = y ●
● Shift Register B
●
Clear

Present State Inputs Next State Output Flip-Flop Inputs

Q x y Q S JQ KQ
0 0 0 0 0 0 X
0 0 1 0 1 0 X
0 1 0 0 1 0 X
0 1 1 1 0 1 X
1 0 0 0 1 X 1
1 0 1 1 0 X 0
1 1 0 1 0 X 0
1 1 1 1 1 X 0
 General Shift Register
• A clear control to clear the register to 0
• A clock input to synchronize the operations
• A shift-right control to enable the shift right operation and the serial input and
output lines associated with the shift right.
• A shift-left control to enable the shift left operation and the serial input and
output lines associated with the shift left.
• A parallel-load control to enable a parallel transfer and the n input lines
associated with the parallel transfer.
• n parallel output lines
• A control state that leaves the information in the register unchanged in the
presence of the clock.
 Universal Shift Register
• A register capable of shifting in one direction only is a
unidirectional shift register.
• A register capable of shifting in both direction is a
bidirectional shift register.
• If a register has both shifts and parallel load capabilities,
it is referred to as a universal shift register.
 4-bit Universal Shift Register
A3 A2 A1 A0
● ● ● ●

C R QN
C R QN

C R QN

C R QN
Q

Q
D

D
Clear ● ● ●
● ● ●
CLK

s1 4X1 4X1 4X1 4X1

s0 MUX MUX MUX MUX
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

Serial ● ● ● ●
input for
shift-right
Serial
input for
shift-left
I3 I2 I1 I0
4-bit Universal Shift Register
Function Table for the Universal Shift Register

Mode Control Register

S1 S0 Operation
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load

• Select pins S1, S0 are common to all MUX

• Clear=0, sets the output to 0000
 Practice
• 6-3~6-8,
 Ripple Counters
• A register that goes through a prescribed
sequence of states upon the application of
clock pulses is called a counter.
• Counters are available in two categories:
– Ripple counters
• Flip-flop output transition serves as a source for
triggering other flip-flop
– Synchronous counters
• All flip-flops are triggered by the common clock.
 Binary Ripple Counter
• 4-bit Binary Ripple Counter with T flip-
flops A A A2 A3
0 1
Logic-1 ● ●
● T Q T Q T Q ● T Q

Count C R QN C R QN C R QN C R QN

Reset ● ● ●
● ●

• 4-bit Binary Ripple Counter with D flip-

flops A A A2 A3
0 1

● ● ●
D Q D Q D Q D Q

C R QN C R QN C R QN C R QN
Count

Reset ● ● ●
What will happen if positive edged Flip-flop is taken instead of negative edged?
The answer is, the functionality will be reversed as it is an asynchronous counter.
 4-bit Binary Count Sequence
A3 A2 A1 A0
0 0 0 0 0000 1111 1110 1101
0 0 0 1
0 0 1 0
0001 1100
0 0 1 1
0 1 0 0
0 1 0 1
0010 1011
0 1 1 0
0 1 1 1
1 0 0 0 0011 1010
1 0 0 1
1 0 1 0
1 0 1 1 0100 1001
1 1 0 0
1 1 0 1
0101 0110 0111 1000
1 1 1 0
1 1 1 1
 BCD Ripple Counter
Q1 Q2 Q4 Q8
Logic-1
● ● ● ●
J Q J Q J Q J Q

C ● C ● C C
Count
● K QN K QN ● K QN K QN
● ●

0000 0001 0010 0011 0100

1001 1000 0111 0110 0101

 BCD Ripple Counter

Q8 Q4 Q2 Q8 Q4 Q2 Q8 Q4 Q2
Q1 Q1 Q1

● ●

BCD BCD BCD Count

Counter Counter Counter pulses

102 digit 101 digit 100 digit

Block diagram of a 3-Decade Decimal BCD Counter

7490 is a decade counter IC.
 Synchronous Counters

Count Q0 Q1 Q2 Q3
enable
● ● ● ● ●
J Q J Q J Q J Q
Clk
● C C C C

● K QN ● K QN ● K QN ● K QN
● ●
RCO
● ● ●

4-bit Synchronous Binary Counter

What will happen if positive edged Flip-flop is taken instead of negative edged?
The answer is, there will be no change as it a synchronous sequential circuit.
Up-Down Binary Counter
A0 A1 A2 A3
● ● ● T ●
T Q T Q T Q
Q

C QN C QN C QN
CLK ● ● ● C QN ●
● ●

●
●
●
● ● ●

● Up Down Operation
0 0 No Change
Up Down 0 1 Down Count
1 0 Up Count
1 1 Up Count
 BCD Counter
Present State Next State Output Flip-Flop Inputs
Q8 Q4 Q2 Q1 Q8* Q4* Q2* Q1* y TQ8 TQ4 TQ2 TQ1
0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 1 0 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 0 1
0 0 1 1 0 1 0 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 0 1
0 1 0 1 0 1 1 0 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 0 1
0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 0 1
1 0 0 1 0 0 0 0 1 1 0 0 1

TQ1 = 1 TQ4 = Q2Q1 y = Q8Q1

TQ2 = Q’8Q1 TQ8 = Q8Q1 + Q4Q2Q1 You may or may not use
the don’t cares.
 Binary Counter w/ Parallel Load
● J ● Q0
I0
C
●
● K

●
I1 ●
● J ● Q1
● ● ● C
EN ●
● K

●
● ● ●

Load ● J ● Q2
I2 ●
● ● ● C
●
● K

●
●
●
● J ● Q3
I3 ●
● ● C

K
RCO
Clear ●
Clk
 Binary Counter w/ Parallel Load
CLK
Clr
LD
Clear CLK Load EN Function

Counter
4-bit
EN
0 X X X Clear to 0

I0 Q0 1 1 X Load inputs
I1 Q1
I2 Q2 1 0 1 Count to next state
I3 Q3
1 0 0 No change
RCO

CLK

Q0

Q1

Q2

Q3

RCO
Binary Counter to BCD Counter
Vcc Vcc

Clock CLK Clock CLK

● Clr Clr
LD LD

Counter
4-bit

Counter
4-bit
EN EN

I0 Q0 I0 Q0
I1 Q1 ● Q0 I1 Q1 Q0
● Q1 ● Q1
I2 Q2 I2 Q2
● I3 Q3 Q2 I3 Q3 Q2
● ● Q3 ● Q3
RCO RCO

• Loads 0000 after 1001 • Clears at 1010

( Synchronous Load, loads at CLK ) ( Asynchronous Clear )
 Counter w/ Unused State
Present
000 111 Next State Flip-Flop Inputs
State
ABC A* B* C* JAKA JBKB JCKC
001 110
000 001 0X 0X 1X
001 010 0X 1X X1
010 100 1X X1 0X
010 101
100 101 X0 0X 1X
100 011 101 110 X0 1X X1
110 000 X1 X1 0X

A B C
● J Q
● ● ● You may or may not use
J Q J Q
CLK● C C C the don’t cares.
K QN K QN K QN
●
●

Logic-1 ●
 Ring Counter
T0 T1 T2 T3

● 2X4
decoder
Shift
right T0 T1 T2 T3
Count
enable 2-bit counter

CLK

T0
Only one register will
T1 have logic-1 at a given
time.
T2 Think of a simple
T3 Traffic Control System
as an application.
 Johnson Counter
A B C
D Q D Q D Q D Q
E

Clk ●
C R QN C R QN C R QN C R QN E’

Reset ● ● ●
● ●

switch-tail ring counter

Sequence Flip-flop outputs AND gate required
number A B C E for output
1 0 0 0 0 A’ E’
2 1 0 0 0 A B’
3 1 1 0 0 B C’
4 1 1 1 0 C E’
5 1 1 1 1 AE
6 0 1 1 1 A’ B
7 0 0 1 1 B’ C
8 0 0 0 1 C’ E
Johnson Counter
HDL 4 Registers & Counters
// Behavioral description of Universal shift register
module shiftreg (s1, s0, Pin, lfin, rtin, A, CLK, Clr);
input s1, s0; // Select inputs
input lfin, rtin; // Serial inputs
input CLK, Clr; // Clock and Clear
input [3:0] Pin; // Parallel input
output reg [3:0] A; // Register output

always @ (posedge CLK or negedge Clr)

if ( ~Clr) A = 4’b0000;
else
case ( {s1,s0} )
2’b00 : A = A; // No change
2’b01 : A = { rtin, A[3:1] }; // Shift right
2’b10 : A = { A[2:0], lfin }; // Shift left
2’b11 : A = Pin; // Parallel load input A3 A2 A1 A0
endcase rtin A3 A2 A1
endmodule
A2 A1 A0 lfin
 HDL - Counter
// Complementing FF with delay
// Input to D flip-flop = Q’
module CF ( Q, CLK, Reset );
output reg Q;
input CLK, Reset;
always @ (negedge CLK or posedge Reset) // Ripple counter test bench
if ( Reset ) Q = 1’b0; module ripplecounter_tb;
else Q = #2 ( ~Q ); // 2 unit delay wire A0, A1, A2, A3;
endmodule reg Count, Reset;
// instantiate ripple counter
// Ripple counter rcntr RC ( A0, A1, A2, A3, Count, Reset );
module rcntr ( A0, A1, A2, A3, Count, Reset ); always
output A0, A1, A2, A3; #5 Count = ~Count;
input Count, Reset; initial
// instantiate complementing FF begin
CF F0 ( A0, Count, Reset ); Count = 1’b0; Reset = 1’b1;
CF F1 ( A1, A0, Reset ); #4 Reset = 1’b0;
CF F2 ( A2, A1, Reset ); #165 $finish;
CF F3 ( A3, A2, Reset ); end
endmodule endmodule
 Verilog – Ripple Counter
module dff (input d, module ripple ( input clk, .q (q1),
input clk, input rstn, .qn (qn1));
input rstn, output [3:0] out); dff dff2 ( .d (qn2),
output reg q, wire q0; .clk (q1),
output qn); wire qn0; .rstn (rstn),
always @ (posedge clk or negedge rstn) wire q1; .q (q2),
if (!rstn) wire qn1; .qn (qn2));
q <= 0; wire q2; dff dff3 ( .d (qn3),
else wire qn2; .clk (q2),
q <= d; wire q3; .rstn (rstn),
wire qn3; .q (q3),
assign qn = ~q; .qn (qn3));
endmodule dff dff0 ( .d (qn0), assign out = {qn3, qn2, qn1, qn0};
.clk (clk), endmodule
.rstn (rstn),
.q (q0),
.qn (qn0));

dff dff1 ( .d (qn1),

.clk (q0),
.rstn (rstn),
 HW
• 6-3~6-8, 6-11~6-18, 6-20~6-28, 6-31~6-34,
6-36, 6-37, 6-38(a), 6-39, 6-40, 6-41, 6-42,
6-47, 6-48(a), 6-50(a)