BIPOLAR JUNCTION

TRANSISTOR

EVANGELINE P. LUBAO, PCpE

Computer Engineering Department CEng-PLM
 LEARNING
OBJECTIVES
• Be able to determine the dc levels for the
variety of important BJT configurations.
• Become aware of the saturation and cutoff
conditions of a BJT network and the expected
voltage and current levels established by each
condition.
• Be able to perform a load-line analysis of the
most common BJT configurations.
• Become acquainted with the design process for
BJT amplifiers.
• Understand the basic operation of transistor
switching networks.
• Develop a sense for the stability factors of a BJT
configuration and how they affect its operation
due to changes in specific characteristics and
environmental changes.
2
DC BIASING BJT
• Operating Point
• Fixed-Bias Configuration
• Emitter-Bias Configuration
• Voltage-Divider Bias
Configuration
• Collector Feedback
Configuration
• Emitter Follower
Configuration
• Common-Base Configuration
• Design Operations
• Bias Stabilization
3
 BIPOLAR JUNCTION TRANSISTOR
Voltage-Divider Bias
Configuration

2 Methods in the analysis:

1. Exact method - which can be
applied to any voltage-
divider configuration
2. Approximate method - can
be applied only if specific
conditions are satisfied. It
permits a more direct
analysis with a savings in Figure 1. Voltage-divider bias configuration
4

time and energy

BIPOLAR JUNCTION TRANSISTOR
EXACT ANALYSIS

Figure 1b. Inserting the Thévenin

Figure 1a. Redrawing the input side equivalent circuit
of the network of Figure 1.

5
6
 BIPOLAR JUNCTION TRANSISTOR
Example 1. Determine the dc
bias voltage VCE and the
current IC for the voltage-
divider configuration of
Figure 2.

Figure 2. Example 1.
 BIPOLAR JUNCTION TRANSISTOR
APPROXIMATE ANALYSIS

The condition that will

define whether the
approximate approach
can be applied is

In other words, if β times Figure 3. Partial-bias circuit for calculating the

the value of RE is at least approximate base voltage V B
10 times the value of R2 ,
the approximate approach
can be applied with a high
degree of accuracy. 8
 BIPOLAR JUNCTION TRANSISTOR
Example 2. Repeat the analysis of
Figure2 using the approximate
technique and compare solutions
for ICQ and VCEQ.

9
Figure 2. Example 2.
BIPOLAR JUNCTION TRANSISTOR
Transistor Saturation

Load-line Analysis

10
 BIPOLAR JUNCTION TRANSISTOR
Collector-Feedback Configuration

Figure 4. DC bias circuit with

voltage feedback.

Figure 4a. Base–emitter loop Figure 4b. Collector–emitter

loop
11
12
 BIPOLAR JUNCTION TRANSISTOR
Example 3. Determine
the quiescent levels of
ICQ and VCEQ for the
network of Figure 5.

Figure 5. Example 3. 13
 BIPOLAR JUNCTION TRANSISTOR
Emitter-Follower Configuration

Figure 6. Common-collector
(emitter-follower) configuration

Figure 6a. dc equivalent

14
 BIPOLAR JUNCTION TRANSISTOR
Example 4. Determine
VCEQ and IEQ for the
network of Figure 7.

Figure 7. Example 4.

15
16
REFERENCES:

• Electronic Devices and Circuit Theory, 9e & 10e

Robert L. Boylestad and Louis Nashelsky

17