Plasma Dicing of Si Wafers with Panasonic

APX300
James Weber
Panasonic Industry Europe GmbH
Agenda

1.Features of Plasma dicing process

2.Panasonic process strategy
3.Plasma dicing demonstration center
1. Features of Plasma Dicing
Technology
Introduction of new process “Plasma dicing”

Blade dicing Plasma dicing

Mechanical Gas Etching

✓ Damage ✓ Damage Free

Chipping
Comparison of Dicing Processes
Blade Dicing Laser Dicing Plasma Dicing

Figure

Dicing Process Mechanical process Laser + expand process Plasma etching process

Depend on
Dicing Speed 10～50mm/s 300mm/s wafer thickness
（Si: >20μm/min）

Lower Lower Higher

Chip Strength
（Chipping・Crack） （Crack・Laser damage） （Stress free）

Low-k Unsuited (delamination,

Suited Suited
Applicability Wafer usage process)
Damage Free Process

TEM images of chip side wall

Non
0.5 damage
μm

Blade Dicing Plasma Dicing

Dicing Width of Plasma Dicing
Increase
number
of chips
60μm

Blade Dicing Plasma Dicing

Number of chips in wafer （8inch wafer,□0.5mm）
Blade Plasma
Yield
Dicing width 60µm 20µm improvement
Number of chips 97,000 116,000 +20%
Variant Chip Shape by Plasma Dicing
Variant
chip shape

Shift of
chip placement
Round chip Hexagonal chip
High Etching Rate
Etching rate ＞25μm/min
(30μm/min is achieved in caseEtching
of thin wafer)
Time 5min

Experiment conditions
•Etching time: 5 min
•Dicing width: 15 μm
•Si dummy wafer
Damage free process
Plasma dicing can prevent chip damage.

Blade dicing Plasma dicing

Optical Front side Front side
(Device surface) (Device surface)
Chipping Chipping
Free
Backside Backside

Chipping
Backside Chipping Backside Free

TEM

Damage Damage
TEM
Layer free
Chip strength test
Mapping data
3 point bending test result 2536 1280

Integrated frequency（ー） Blade Dicing 941 2536

1329 2534

1776
2054

Plasma Dicing

1415 2482 1162

831 1427 2016 1319 712
1598 916

910
1069

1529 670
1867 1102

1939 1432

3 point bending
[Note] Si wafer size : 8 inch
chip size : 5x15mm
Bending strength（MPa） Thickness : 150um

Higher bending strength with narrow distribution

Breaking mode of Si chip
Blade dicing Plasma dicing
(cleavage mode) （Crushing mode）

Before

Crack/Chipping Damage less

broken-out section

After Cleavage separation Material crush out

Plasma source ~Multi Spiral ICP(MSC-ICP)~
Chamber configuration Patented

ICP coil
Matching unit
Magnetic
磁界 RF
field

Quartz
Plate

Wafer
- - ダイシングリング
ダイシングリング
Dicing ring
トレイ
Branch number
Chamber vessel

Electric
電子
Bias Ion Multi
RF

I-sat current
Low inductance coil → High efficiency
・High density plasma Single

・Wide range of discharge window

・Uniform large scale plasma Wafer Position
How to etch a wafer with tape by plasma?
◆ Wafer with dicing tape Tape melt
Standard dry etcher gives
tape melt due to heat from
plasma
(Heat resisting property ~100℃)

◆ Panasonic’s solution Standard Dry Etcher Panasonic Plasma Dicer

① Original ESC Original

plasma plasma cover
improves cooling efficiency Ring
Wafer
between wafer/tape/chuck Original
② Original cover ESC
prevents exposure of tape Cooling ESC Cooling Prevent
water water
from plasma heat damage

Controlled tape temperature enables high etch rate

Patent Strategy for Plasma Dicing
Patent Comparison between Panasonic and others

JP⇒ 25 16 5 5 14 8
US⇒(7) (9) (2) (4) (9) (6)

Others 11 2 2 1

Ｅｑｕｉｐｍｅｎｔ Ｐｒｏｃｅｓｓ
Ｐｌａｓｍａ Chamber Transfer Process Quality Mask
Source flow
〇 Panasonic has not only many equipment patents, but also process patents.
〇 Examples of Panasonic’s fundamental patents
USP8,513,097 Fundamental equipment patent for wafer with dicing frame
USP6,897,128 Process patent for process flow of plasma dicing
USP7,964,449 Process patent for Laser scribe + Plasma dicing
2. Panasonic Process Strategy
Dimensional/mechanical trend in IC chip
Thin Thin Brittle

Source)
http://www.aset.or.jp/kenkyu/kenkyu_seika_com
p_7.html
Source)
http://www.aset.or.jp/kenkyu/ke Image Sensor Source) http://panasonic-
denko.co.jp/ac/j/tech/pimites/exp
nkyu_seika_comp_7.html lan_tech/what_tech_001/index.js
3D/TSV MEMS p

Brittle Memory Small

Low-k Chip RF-ID

Source)
http://pr.fujitsu.com/jp/news/20
Wafer Source)
http://www.hitachi.co.jp/inspire/hakken
03/06/25-2.html /blue/04_mu_chip.html

Chip goes “Thin・Brittle・Small”

Plasma dicing target area
Thin and Small chips are target area of plasma dicing
700 Point
Thickness（μm） Commodity IC etc. Thick

400 Blade Dicing

Driver IC etc.
300
Logic Middle

Discreet Laser Dicing

200 Chip
・ Sensor
RFID ・MEMS Thin
（Number） （Number）
100 （Particle） Plasma Dicing
Memory
Plasma dicing target area（Chipping)
1 3 7
Chip Size（mm□）
Benefits of Plasma dicing
Target
Blade issue Benefit by plasma
Application
0.1
mm Narrower lane Blade Plasma
Wider
0.2mm
（W 20μm）
dicing lane 60μm 20μm
 More chips
（W 60μm）
from a wafer
IoT Line-by-line Whole wafer
Small chip Longer process Shorter process
・RF-ID tag
time in smaller time
・Chip component dies lower COO
・MEMS etc..

Particle from Mechanical

Particle free
blading, base
improve yield ↓
less yield
Image Sensor Source）Panasonic HP Gas base
Blade Plasma
25μm Damage free chip
Memoryー Chipping/die
obtained
breakage
CPU
new value for
due to damage
Memory end user Damage No damage
Process scenarios
Two processes cover target applications
Appli- Chip Process
Wafer Structure
cation size Mask formation Dicing
Mask Photolithography Plasma
Si Liquid
IoT
Small
Plasma Dicing
Chip Small
(~3mm) Si
Coat/Expo. Develop. Dicing
Laser
Mask Patterning Mask tape Laser Plasma
Image Or coating
Metal/
sensor Low-k
Si

Plasma Dicing
Memory Large
/Logic (3mm~) Cut mask &
Dicing
Si Lamination
Metal layer
Alliance between Panasonic & partners
[Coater] [Developer]
EVG SUSS Microtec

ターゲット チップ ウエハーの 工法１：フォトリソ＋プラズマ ウエハー反転

カテゴリ サイズ 断面構造 ウエハー薄化 フォトリソによるマスクパターン形成 ダイシング
0.1 保護テープ レジスト ダイシング プラズマ
裏面研削 露光 現像 ベーク
0.2mm
mm
マスク 貼付 塗布 シート貼付 ダイシング
Si

プラズマダイシング
小チップ
• チップ部品
• RF-ID
小さい Si

• MEMS 等

工法２：レーザー＋プラズマ
マスク
レーザー
パターンニング
ウエハー薄化 レーザー加工によるマスクパターン形成 ダイシング
イメージ 保護テープ ダイシングシート貼付
メタル 裏面研削 レーザースクライブ プラズマダイシング
センサー* 配線 貼付 (保護テープの一部を残す)
Si
基材
接着層
メモリー マスク
50μm プラズマダイシング ウエハ

CPU
大きい Si

メモリー
* 出所) パナソニックHP プレスリリース

[Mask tape] [Laser] [Gas related]

Furukawa Accretech Taiyo-Nippon Sanso
2-1 Photolitho ＋ Plasma Dicing
Photolitho + Plasma Dicing from device surface

BG tape De-lamination Plasma dicing ( Si etching )

725µm SF6

BG Tape

BG Spin Coat

Plasma dicing ( Ashing )

O2 Plasma
Damage layer Photo Litho

Die pick up
Stress Relief Dicing tape lamination
Photolitho + Plasma Dicing from back surface
Plasma dicing ( Si etching )
Spin Coat
725µm TEG SF6

BG Tape

BG
Photo Litho

Plasma dicing ( Ashing )

BG Tape
O2 Plasma
Damage layer
BG tape De-lamination

Die pick up
Stress Relief Dicing tape lamination
2-2 Laser Patterning ＋ Plasma
Dicing
Process scenarios
Two main processes cover our target applications
Appli- Chip Process Flow
Wafer Structure
cation size Mask Patterning Dicing
Mask Photolithography Plasma
Si Liquid
IoT
Small
Plasma Dicing
Chip Small
(< 2mm) Si
Coat/Expo. Develop. Dicing
Laser
Mask Patterning Coating Laser Plasma
Image
Metal/
sensor Low-k
Si

Plasma Dicing

Memory Large
(> 3mm) Patterning Dicing
Si
Two mask methods of plasma dicing
BG mask tape and water-soluble mask are available
①BG tape
②Coating ③laser grove ④Plasma dicing ⑤Removing
delamination
Remained
mask film
Base film
of BG tape

BG mask tape Non

（Furukawa） （Low cost）
Furukawa Ashing
BG mask tape
（special tape）

Water-soluble
mask
Spin or Spray Water rinse
(water-soluble)
Two mask methods of plasma dicing
BG mask tape and water-soluble mask are available
①BG tape
②Coating ③laser grove ④Plasma dicing ⑤Removing
delamination
Remained
mask film
Base film
of BG tape

BG mask tape Non

（Furukawa） （Low cost）
Furukawa Ashing
BG mask tape
（special tape）

Water-soluble
mask
Spin or Spray Water rinse
(water-soluble)
Key Technology of Laser + Plasma Process
Laser Patterning Plasma Cleaning Panasonic Process Patent
Thin Wafer Dicing by Laser + Plasma process
Plasma dicing can etch not only thin Si wafer but also DAF tape

Si (50um) Si
Center

DAF (20um) DAF

Edge Si Si

DAF DAF
Chip Strength of Laser + Plasma Process
Furukawa Chip strength of laser +
BG mask plasma process is same as
Blade + plasma
one of photo process

Photolith
+ plasma
Typical structure of wafer with bumps

Dicing Dicing
street street
Solder bump /
Cu-pillar + solder cap
30~250μmH
50~100μmW

RDL
SiO2

Si 725/775μm  200～25μm etc..

 Many semiconductor wafers have some bumps/pads

 How to handle such bumps in plasma dicing process?
Pre-test sample structure / target

Covers Mask (PR)

whole ball -Thick: 10μm 5x5mm chip
Open Width
-Laser: 30μm
-Litho: 10μm
Solder ball
Φ250μm
SiO

Original dicing street : ~100μm

Φ8” Si-sub
[key 1] ~Conformal coating of solder ball~
initial After coating

Solder ball
Φ250μm

Conformal coating achieved !

[key 2a] ~Street opening by Lithography~

10μm

Covers
Gap whole ball
>200μm
Open by Aligner

Solder ball
Φ250μm
SiO

100μm
5x5mm chip

Alignment & Exposure with a big gap executed !

[key 2b] ~Street opening by Laser~

30μm

Laser Patterning successfully done !

3. Plasma Dicing Demonstration
Center
What makes difficult when exploring plasma
◆Requests from customer

 Rapid demonstration with

different products BG tape BG
Photolithography

Vendor A Vendor B Vendor C

 Total solution incl. material
and equipment

 Secure highly confidential

wafer when hand over
many different venders
Laser Plasma dicer

Vendor D Panasonic (Japan)

Preparing demonstration site is essential !

“Plasma dicing demonstration center”
Founded Oct. 12 nd, 2016

Location Osaka, Japan

Floor Space 230m²

-Class : 1,000(φ0.5μm)
Spec
-Temperature : 23±3℃
(Clean room)
-Relative & humidity : 50±20％

Plasma dicer APX300 X 2 machines

Wafer Φ300mm・φ200mm min 25umt

Polish grinder Thinning wafer. Min. 25μm thickness（coming early 2017）

Lithography Open mask street by photolithography technique. Min. few μm width
Process Laser patterning Open metal/low-k layer. Min 15μm width
Plasma dicer Full cut bulk-Si layer by deep-Si etching. High speed > 25μm/min.
Measurement Surface profile, thickness and optical analysis
“Plasma dicing demonstration center”

Laser patterning SEM Profiler thickness Coater Developer

Yellow
room
Class 1000 Laser Measure
cleanroom

BG/Tape Plasma Litho

Polish grinder Mask aligner

HMDS
Vacuum laminator BG tape laminator Φ8”Plasma dicer Φ12”Plasma dicer Bake plate Vapor primer

● Equipment line-up（φ8 & φ12inch applicable)

Conclusion
Panasonic provides and support customer
by “one-stop solution” for plasma dicing

Equipment

Laser

Litho
Laminator

BG
Plasma
Material dicer Process
Tape
Measurement
 Thank you for your attention.

Please contact James Weber for more information.

Visit us at the Panasonic Booth in Hall A4, Nr 474.

james.weber@eu.panasonic.com