IET Power Electronics

Research Article

Analysis and controller design for stand- ISSN 1755-4535

Received on 28th October 2016
Revised 16th March 2017
alone VSIs in synchronous reference frame Accepted on 18th March 2017
E-First on 11th April 2017
doi: 10.1049/iet-pel.2016.0883
www.ietdl.org

Malek Ramezani1 , Shuhui Li1, Saeed Golestan2

1Department of Electrical and Computer, University of Alabama, Tuscaloosa, AL, USA
2Department of Energy Technology, Aalborg University, Aalborg DK-9220, Denmark
E-mail: mramezani@crimson.ua.edu

Abstract: The common practice for controlling the stand-alone voltage source inverters (VSIs) is to transform abc voltage and
current signals to DC signals using the dq transformation, which makes it possible to control the new DC voltage and current
signals just using simple proportional-integral controllers with a zero steady-state tracking error. However, the transformation
causes coupling terms between d- and q-axis components in both current control loops and voltage control loops, which
deteriorate the dynamic and steady-state performance of the control system. This study presents a step-by-step graphical
analysis and design approach for a three-phase stand-alone VSI system in the dq reference frame, which provides a clear
systematic decoupling process to design the inner- and outer-loop current and voltage controllers, respectively. The closed-loop
d- and q-axis output impedances of the stand-alone VSI system by considering the coupling effects between axes are also
formulated, modelled, and evaluated. The study investigates how the decoupling and compensating terms added in the current
and voltage controllers affect the dynamic performance and output dq impedances of the VSI system. Simulation and hardware
results verify the effectiveness of the graphic design and analysis strategy.

1 Introduction reference frame is conventionally carried out by proportional-

Voltage source inverters (VSIs) are now widely used as a power
electronics interface for connecting the renewable energy-based
distributed generation systems to the utility grid and microgrids.
They are also highly popular in applications such as uninterruptible
power supplies (UPS), active power filters, dynamic voltage
restorers [1–4].
Depending on the application in hand and operating conditions,
VSIs may operate in grid-connected or islanded mode. In the grid-
connected mode, the voltage and frequency are dictated by a stiff
grid; therefore, in this operating condition the VSIs are controlled
to behave as current-controlled inverters [5, 6]. It means, in their
nested control loops systems, the inner loops are current loops;
however, the outer loops are active and reactive power controllers
or DC link voltage controllers [7, 8]. On the other side, in the
stand-alone mode, there is no stiff grid and VSIs are responsible for
adjusting the voltage and frequency for local loads. Meaning that,
although, like grid-connected VSIs, the inner control loops for their
nested control loops system are current controllers, the outer loops
are the output AC voltage controller. Another difference is that a
cross-coupling exists not only in the inner current control loops
(CCLs) but also in the outer control loops. Therefore, controlling
the output AC voltage of the stand-alone VSI and at the same time
providing a high-quality power to the consumers with a fast
dynamic response faces serious obstacles because of the cross-
coupling effects and the variable nature of the loads.
So far, several control strategies for the stand-alone and grid-
connected three-phase VSIs have been presented in the literature.
The repetitive-based control technique [9, 10] offers a satisfactory
performance in suppressing the output voltage and current
harmonic distortion caused by non-linear loads; however, this
technique suffers from a tracking inexactitude, poor dynamic
performance, and requirement for faster memory than the other
techniques [11]. Another proposed technique for controlling VSIs
is the sliding-mode control [12–14], which offers advantages such
as fast dynamic response and high robustness to inverter and output
filter parameters variations. This technique, however, suffers from
a high sensitivity to the load variations. Besides, using this strategy
results in a steady-state tracking error. The VSIs control in the abc
integral (PI) regulators which results in a low-power quality, and a
steady-state tracking error. To improve the VSI control
performance, model predictive controllers (MPCs) have been
proposed [15, 16]. The MPC predicts the system operation by
employing a model of the system; therefore, the system parameters
variations degrade the effectiveness of the control system. The
intelligent-based control methods, such as neural network and
fuzzy controllers [17, 18] try to deal with the variation in system
parameters without having an accurate mathematical model of the
system; however, the training process of these approaches is not a
facile task, particularly when nested control loops are employed for
controlling the VSIs. To solve the tracking inexactitude inherent in
some of the aforementioned control techniques and to provide an
autonomous voltage control for stand-alone VSIs, the proportional-
resonant (PR) controller has been proposed [19, 20]. The PR
controller also provides a selective harmonic rejection, which
considerably reduces the total harmonic distortion (THD) in the
presence of non-linear loads. However, the sensitivity to the phase
shift and frequency deviation of the sampled signals is the main
drawback of this controller [21].
Most popular reference frame for controlling grid-connected
VSIs is probably the dq reference frame, in which the three-phase
AC signals are transformed to DC or quasi-DC signals by applying
the Park's transformation [22]. In the dq reference frame, simple PI
controllers are employed as the regulators, which ensure a zero
steady-state tracking error and a fast dynamic response [23].
Nevertheless, the dq transformation will introduce a cross-coupling
between d- and q- axis, which deteriorates the control system
performance. For a grid-tied VSI, the decoupling technique in d-
and q-axis CCLs is needed, which helps to suppress the sensitivity
to the load change, increases the disturbance rejection capability,
and improves the output current THD in the case of non-linear
loads [24].
However, for a stand-alone VSI, a cross-coupling exists in both
current and voltage control loops (CCLs and VCLs), which makes
it more important to analyse the impact of the cross-coupling
between d- and q-axis loops in details. This knowledge can be very
useful for developing more efficient decoupling technique for both
CCLs and VCLs. Besides, in UPS and microgrid applications, the

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© The Institution of Engineering and Technology 2017
nature of the VSI output impedance has a direct effect on the power 2π 4π
cos θ cos θ − cos θ −
sharing and control [25]. Although the dq closed-loop output 3 3
impedance is investigated in [26], the output impedance analysis in 2 2π 4π
this reference is true when the CCL is ideal and the decoupling in T= −sin θ −sin θ − −sin θ −
3 3 3
VCL is perfect. It is shown in this paper that the decoupling in
VCL is not perfect. Therefore, by considering the non-ideal 1 1 1
decoupling effects, the self- and mutual impedances for d- and q- 2 2 2
axis are formulated and analysed in this paper. It is worth noting,
since the VSI controllers are usually designed in the dq reference By assuming that the three-phase system is symmetrical,
frame, understanding the dq output impedance is critical for the transforming (1) to the dq-reference frame results in
proper power control design of a stand-alone VSI system.
The main contributions of this paper are (i) providing a step-by- d I Ld −r ωL I Ld V id − V Cd
step graphical approach for the detailed decoupled and L = + (2a)
dt I Lq −ωL −r I Lq V iq − V Cq
compensated dq voltage and CCLs, (ii) investigating benefits and
impacts of the decoupling technique on the VSI system, (iii)
analysing and formulating the output impedance of the VSI system d V Cd (Cω)V Cq I Ld I od
C = + − (2b)
in the dq reference frame as well as how it is affected by the dt V Cq −(Cω)V Cd I Lq I oq
controller and decoupling process, and (iv) simulation and
hardware experiment evaluation. Rearranging (2) and applying the Laplace transformation to (2)
This paper is organised as follows: In Section 2, the mathematic gives
modelling of a stand-alone VSI in the dq rotating reference frame
is studied. The inner d- and q-axis CCLs and outer d- and q-axis I Ld 1 V id − V Cd 1 (ωL)I Lq
VCLs design and analysis are presented in Sections 3 and 4, = + (3a)
I Lq LS + r V iq − V Cq LS + r −(ωL)I Ld
respectively. Section 5 analyses the VSI output impedance,
including both self- and cross-coupling impedances, in the dq
reference frame. Section 6 investigates the decoupled control of V Cd 1 (Cω)V Cq 1 I Ld − I od
both the current and voltage loops as well as the impact of the = + (3b)
V Cq CS −(Cω)V Cd CS I Lq − I oq
compensation terms through the simulation and experimental
verification. Finally, Section 7 concludes this study.
Using (3), the block diagram for the linearised model of the VSI
system can be obtained as shown in Fig. 1b. As it can be seen, Lω
2 DQ reference frame modelling of a three-phase couples the d-axis inductor current to the q-axis voltage and the q-
stand-alone VSI axis inductor current to the d-axis voltage, Cω couples the d-axis
A stand-alone three-phase VSI system based on n-channel capacitor voltage to the q-axis current and the q-axis capacitor
MOSFET including the dq reference frame nested control loops is voltage to the d-axis current; therefore, in designing current and
shown in Fig. 1a, in which L and r are the LC filter inductor and its voltage controllers, coupling terms between d- and q-axis loops
equivalent series resistance (ESR), respectively, C is the capacitor need to be handled and analysed properly to enhance the
of the LC filter, V dc denotes the regulated DC power source at the performance of the VSI system.
input of the VSI, and the regulated capacitor voltage is supplied to
the three-phase loads. The switching method is based on the pulse- 3 Analyse and design of the inner-loop current
width modulation (PWM) mechanism. The values of L and C need controllers
to be designed based on the VSI rated power and the maximum To ensure a satisfactory dynamic and steady-state performance for
allowable ripples in its output current and voltage. For clarification, the VSI, a special care should be paid in designing its control
the three-phase output voltage after the filter bank can be applied to system [27]. As it was mentioned in Section 2, the current signals
the load through transmission lines in long distances or applied turn to DC components in the dq reference frame; therefore, they
directly to the load locally; therefore, the transmission line effects can be easily and effectively controlled by using PI controllers. The
should be considered in the power control. The system parameters problem is that the coupling links between d and q axes, as shown
are summarised in Table 1. Using Fig. 1a and applying KVL and in Fig. 2a, act as disturbances and deteriorate the current controller
KCL rules, the differential equations describing dynamics of the performance. To be more exact, ( + LωI Lq) and ( − V Cd) are the
VSI can be derived as
disturbances for the d-axis CCL, and ( − LωI Ld) and ( − V Cq) are
diL_abc the disturbances for the q-axis CCL. To cancel out these
vi_abc = riL_abc + L + vC_abc (1a) disturbances, each disturbance is added to the corresponding
dt
controllers in the d- and q-axis CCLs with an opposite sign, which
dvC_abc modifies the d- and q-axis current controllers from Figs. 2a to Fig.
iL_abc = C + io_abc (1b) 2b. Then, Fig. 2b can be simplified as Fig. 2c. According to
dt
Fig. 2c, the closed-loop transfer functions Gid(s) = (I Ld(s)/I ∗d) and
where vi_abc = uV dc is the three-phase inverter output voltage right Giq(s) = (I Lq(s)/I ∗q) for the d- and q-axis CCLs can be derived as
after the MOSFET bridge (u is the three-phase control signals),
iL_abc is the three-phase inductor current, vC abc is the three-phase K piS + K ii
_ Gid(S) = Giq(S) = Gi(S) = (4)
capacitor voltage, and io_abc is the three-phase load current. Notice LS2 + (r + K pi)S + K ii
that the above equations are derived based on the VSI average
model. where K pi and K ii are the proportional and integral gains of PI
The transformation from the stationary (abc) reference frame to controller, respectively.
the dq0-rotating reference frame can be implemented using the In designing the current controller, the speed of response,
following transformation matrix T, where θ = ∫ ω dt is the output disturbance rejection capability, and stability issues need to be
voltage phase angle reference, and ω is the angular velocity of the considered. Besides, the harmonic control is very important in
rotating reference frame. It is worth noting that the 0 component stand-alone applications. Meaning that the current regulator
does not exist in a balanced three-phase system. bandwidth should be designed to reach a satisfactory compromise
between desired characteristics. To achieve a fast dynamic
response, the current controller bandwidth needs to be high [28],
which means the proportional gain needs to be high. A high

1004 IET Power Electron., 2017, Vol. 10 Iss. 9, pp. 1003-1012

© The Institution of Engineering and Technology 2017
Fig. 1 Stand-alone voltage source inverter structure
(a) VSI including the dq reference frame controller, (b) Block diagram for linearised model of the VSI and its output filter in dq-reference frame

Table 1 Parameters of three-phase VSI desired bandwidth. The proportional gain relationship with the
Parameters Values CCL bandwidth, using (4), can be expressed by
DC link voltage (V) 1200
L–L rms voltage (V) 690 K pi = r + r2 + (Lωbi)2
nominal frequency (Hz) 60
filter inductor ESR (Ω) 0.12 Therefore, the proportional gain for ωbi = (ωsw /10) = 6.283 krad/s
filter inductor (mH) 1.5 is 16.072, where ωbi and ωsw are the current controller desired
filter capacitor (μF) 50 bandwidth and switching frequency, respectively. Although, in
switching frequency (kHz) 10
some literature it is mentioned that there is no need for an
integrator controller in the CCL [29, 30], in overload or fault
conditions the existence of integrator part of controller can be very
helpful [31, 32]. The current controller integrator is aimed to
bandwidth, nevertheless, deteriorates the disturbance rejection minimise the tracking error (ideally zero) in the inner CCL while
capability; therefore, selecting the proportional gain involves a maintaining a fast dynamic response for it. Based on the closed-
trade-off between the dynamic response and the disturbance loop transfer function for the CCL in (4), the transfer function can
rejection capability. A criterion to choose the CCL bandwidth is the be shown in the pole-zero format as follows:
switching frequency of the power converter; often, the current
controller bandwidth is chosen between 1/10 and 1/20 of switching K piS + K ii S−z
frequency to reject switching disturbances from the power Gi(S) = =
converter [21, 28]. To set the proportional gain, the integral gain is
2
LS + (r + K pi)S + K ii (S − p1)(S − p2)
first set to zero and the proportional gain is selected based on the

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Fig. 2 Current and VCLs for d- and q-axis
(a) CCLs without decoupling and compensation, (b) CCLs with decoupling and compensation, (c) Simplified CCLs, (d) Voltage control loops block diagram

∗ ∗
Then, by equating the denominator of two sides of equality, the Gvd− ideal(s) = (V Cd(s)/V Cd (s)) and Gvq− ideal(s) = (V Cq(s)/V Cq(s)) for
closed-loop poles can be derived as d- and q-axis VCLs with K z = 1 are

−(r + K pi) + (r + K pi)2 − 4LK ii K pvS + K iv

p1 = , Gvd− ideal(S) = Gvq− ideal(S) = Gv − ideal(S) =
2L 2
CS + K pvS + K iv
(5)
2
−(r + K pi) − (r + K pi) − 4LK ii
p2 = where K pv and K iv are the proportional and integral gains for VCL
2L
PI controllers, respectively. Note that with an ideal CCL, the output
Fig. 3a illustrates the trajectory of current loop closed-loop poles. impedance for the VSI is zero and the VSI would be an ideal
Based on this trajectory and above expressions for the closed-loop voltage source. However, the CCL is actually not ideal; therefore,
poles, the following conclusions can be made: the exact d-axis VCL transfer function with K z = 1 is (see (6))
With the same mathematic manipulation, the q-axis VCL
(i) When 0 < K ii < (r + K pi)2 /(4L), the closed-loop poles are real transfer function is
∗
and negative. In this range, the system has a well-damped dynamic V Cq = Gvq(S)V Cq − GDq(S)((Cω)V Cd) − GZq(S)I od.
response. Roughly speaking, increasing K ii in this range, According to (6), the d-axis voltage transfer function is
particularly when K ii has rather a small value makes the dynamic ∗
Gvd(s) = (V Cd(s)/V Cd (s)) V = 0, I = 0, and the other transfer
Cq od
response fast but reduces the system noise immunity.
functions in (6) are related to the disturbance
(ii) When K ii > (r + K pi)2 /(4L), the closed-loop poles become (GDd(s) = (V Cd(s)/CωV Cq(s)) V ∗ = 0, I = 0) and the output
complex-conjugate, which implies the system has an oscillatory Cd od

dynamic behaviour. impedance (GZd(s) = (V Cd(s)/I od(s)) V ∗ ). Note that

(iii) For all values of K ii, the closed-loop poles have a negative real
part; therefore, the system is stable.
Here as a compromise between the dynamic behaviour and
noise immunity of the system, the integrator gain (K ii) is chosen
equal to 40, which results in zero tracking error and a bandwidth of
6.207 krad/s (988 Hz) that is close enough to the desired bandwidth
6.283 krad/s (1000 Hz).
4 Design of the outer-loop voltage controllers
Having a reliable and regulated voltage at the AC side of the stand-
alone VSI is necessary from the power quality point of view. The
VCL is shown in Fig. 2d, in which ( + CωV Cq) and ( − I od) are the
disturbances for the d-axis VCL, and ( − CωV Cd) and ( − I oq) are
the disturbances for the q-axis VCL. Therefore, the compensation
and decoupling terms with opposite sign of disturbances are also
included in the d- and q-axis controllers of the VCL in Fig. 2d,
which lightens the wrecking effects of the disturbances. Note that
with ideal performance of the CCL (i.e. |Gi(jω) | ∠Gi(jω) = 1∠0 for
0 < ω < ωbi), the compensation and decoupling effects would be
perfect. Then, the closed-loop transfer functions
Cd = 0, V Cq = 0
Gvq(s) = Gvd(s) ≜ Gv(s), GDq(S) = GDd(S) ≜ GD(S), and
GZq(S) = GZd(S) ≜ GZ(S).
In designing the nested control loops system, the first
consideration is that the CCLs need to be much faster than the
VCLs. Therefore, the VCL bandwidth (ωbv) is normally chosen
between 0.25 and 0.75 of ωbi. Also, ωbv should be larger than the
LC filter cut-off frequency and >10 times of the fundamental
frequency, meanwhile considering the disturbance rejection
properly [33]. Note that in designing both current and VCLs, there
is a compromise between the control loop speed and disturbance
rejection capability. Here, again we set the integrator gain to zero
and after determining K pv, K iv will be designed based on the
stability and steady-state error requirements. The proportional gain
of the VCL PI regulators is designed according to the desired
bandwidth criterion. Using the voltage transfer function in (6),
which is defined as Gv(s), the VCL controller proportional gain can
be derived as

1006 IET Power Electron., 2017, Vol. 10 Iss. 9, pp. 1003-1012

© The Institution of Engineering and Technology 2017
Fig. 3 Bode plot for VCL transfer function and VSI output impedance
(a) Trajectories of CCL closed-loop poles, (b) Trajectories of VCL closed-loop poles when integrator gain changes between 1 and 1000, (c) VCL Bode plot with real CCL, (d) d-axis
self- and mutual impedance characteristics

K piK pvS2 + (K piK iv + K pvK ii)S + K iiK iv ∗

V Cd = V Cd
LCS + C(r + K pi)S3 + (K piK pv + CK ii)S2 + (K piK iv + K pvK ii)S + K iiK iv
4

Gvd(s)

LS3 + rS2
+ ((Cω)V Cq)
LCS + C(r + K pi)S + (K piK pv + CK ii)S2 + (K piK iv + K pvK ii)S + K iiK iv
4 3
(6)
GDd(S)

LS3 + rS2
− I .
LCS + C(r + K pi)S + (K piK pv + CK ii)S2 + (K piK iv + K pvK ii)S + K iiK iv od
4 3

GZd(S)

1 Fig. 3c shows the Bode plot for VCL transfer function. The
Gv(jωbv) = ⇒ K pv
2
(7)
Cωbv 2(Lωbv)2 + (K pi)2 − Lωbv
= .
K pi
By choosing ωbv = 3800 rad/s ≃ 0.6ωbi (605 Hz), the proportional
gain is K pv = 0.1353. Designing the values of PI controller integral
gain (K iv) is a compromise between the steady-state error and
system stability. As it is obvious from VCL transfer function in (6),
there are four closed-loop poles. The closed-loop poles trajectories,
when the integrator gain is changing in the range [1 1000], is
shown in Fig. 3b, in which arrows show the direction of increasing
in K iv values. By increasing K iv, p3 and p4 are further moving to the
left side of the imaginary axis and do not affect the system stability,
negatively; however, p1 and p2 move towards imaginary axis. As it
can be seen in Fig. 3b, the maximum acceptable gain before the
controller loses its stability is 887.67 ( p1 and p2 reach the stability
border, i.e. the imaginary axis). To come to a compromise between
the stability, and a fast enough VCL with an acceptable disturbance
rejection capability, K iv is chosen as 565.5.
transfer function gain and phase at fundamental frequency (f = 60
Hz) are 1.009° and −0.025°, respectively, which shows an almost
zero steady-state error and phase shift at this frequency. Fig. 3b
shows the d-axis self- and mutual output impedance of the VSI. It
is worth noting that the mutual impedance represents the coupling
between d and q axes.
5 VSI DQ impedances analysis
Understanding the VSI output impedance is important in
developing and designing the power control for stand-alone or
grid-connected VSI [34]. Particularly, when controlling the parallel
VSIs in UPS and microgrid applications using the droop method is
intended. The VSI output impedance will be affected not only by
its output LC filter but also by the controller configuration and
parameters. As it was mentioned in Section 4, an ideal CCL will
result in the perfect compensation and decoupling in the VCL and a
zero VSI output impedance. However, in real conditions, the output
impedance not only is not zero but also can show the different
quiddity, which will affect the power quality and the performance
of the power sharing control system [34, 35].

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Fig. 4 Effects of output current feedforward on the dq output impedances
(a) d-axis self-impedance characteristics for different values of K z, (b) d-axis mutual impedance characteristics for different values of K z

As it can be seen from (6), the terms of (Cω)V Cq and I od are As it was mentioned earlier, I od and I oq act like disturbance on
disturbances for the d-axis VCL; similarly, the terms of (Cω)V Cd the d- and q-axis VCLs, respectively; therefore, a feedforward of
and I oq are the disturbances for the q-axis VCL. Rewriting (6) these disturbances is added to the d- and q-axis VCLs,
besides considering the q-axis VCL transfer functions, then (8) can correspondingly. The strength of the feedforward branches will
be obtained as directly affect the absolute value and the nature of the self- and
mutual impedance of the dq axes (to be inductive, resistive, or
complex). If in Fig. 2d the dq output currents are passed through
V Cd = Gv(s)V ∗Cd + GD(S)[(Cω)V Cq] + GZ(S)I od (8a) gain K z instead of a unit feedforward gain to the dq voltage
∗ controller, (9) will change to (11).
V Cq = Gv(s)V Cq − GD(S)[(Cω)V Cd] + GZ(S)I oq (8b)
GZnew(S) (Cω)GZ(S)GZnew(S)
Also, it can be seen in (6) that GD(S) = GZ(S). Therefore, the V Cd = − I od − I oq (11a)
1 + [(Cω)GZ(S)]2 1 + [(Cω)GZ(S)]2
impact of I od and I oq on V Cd and V Cq can be solved from (8) by
setting V ∗Cd and V ∗Cq zero, then (8) changes to (9) (Cω)GZ(S)GZnew(S) GZnew(S)
V Cd = I od − I oq (11b)
1 + [(Cω)GZ(S)]2 1 + [(Cω)GZ(S)]2
GZ(S) (Cω)[GZ(S)]2
V Cd = − I od − I oq (9a)
1 + [(Cω)GZ(S)]2 1 + [(Cω)GZ(S)]2 in which (see equation below)
The Bode plot of Z dd transfer function for different values of K z
(Cω)[GZ(S)]2 GZ(S) is shown in Fig. 4a. It can be seen that for K z = 1 the nature of
V Cq = I od − I oq (9b)
1 + [(Cω)GZ(S)]2 1 + [(Cω)GZ(S)]2 impedance is complex, but for K z = 0.75 the impedance absolute
value is purely inductive in effective bandwidth which will help to
Defining the impedance matrix as (10), where design of the active power-frequency control. In addition, the Bode
Z odd = (V Cd /I od) I is the d-axis self-impedance, plot for Z dq transfer function for different values of K z is shown in
oq = 0
Fig. 4b, which shows that an effective decoupling in terms of the
Z odq = (V Cd /I oq) I is the mutual impedance between d- and q- mutual impedance between d- and q-axis loops.
od = 0

axis, Z oqq = (V Cq /I oq) I is the q-axis self-impedance,

od = 0
6 Simulation and experimental results
Z oqd = (V Cq /I od) I is the mutual impedance between q- and d-
oq = 0 6.1 Simulation results
axis. Then, it can be obtained from (9)
To evaluate the controller performance, the VSI with the dq
GZ(S) reference frame controller is simulated in the MATLAB/
Z odd = Z oqq = and SIMULINK environment. The simulations are conducted under
1 + [(Cω)GZ(S)]2 different load scenarios. First, an RL load (R = 19 Ω,
(Cω)[GZ(S)]2 L = 0.2/(120π) H (per phase)) is supplied by the VSI, then at t = 5
Z odq = − Z oqd = . s, the second RL load, with the same value as the first load, is
1 + [(Cω)GZ(S)]2
added.
Figs. 5a and b represent the d- and q-axis voltage transient
Z odd Z odq response, respectively, with and without the voltage decoupling
Z output = (10) process when the load is changed to double. As it can be seen, the
dq Z oqd Z oqq
decoupling process suppresses the voltage overshoot and
Fig. 3d shows the Bode plot of the d-axis self-impedance transfer fluctuation during the transient state of load changing. It is worth
function Z odd, and the mutual impedance between the d and q axes, noting that the overshoot in the non-decoupled case can be reduced
by re-tuning the proportional gain of the voltage controller;
transfer function Z odq. however, a smaller proportional gain results in a lower control loop
bandwidth and reduces the response speed. The speed of response

LS3 + (r + (1 − K z)K pi)S2 + (1 − K z)K ii

GZnew =
LCS4 + C(r + K pi)S3 + (K piK pv + CK ii)S2 + (K piK iv + K pvK ii)S + K iiK iv

1008 IET Power Electron., 2017, Vol. 10 Iss. 9, pp. 1003-1012

© The Institution of Engineering and Technology 2017
Fig. 5 Coupling process effects on transient response
(a) d-axis voltage transient response to load changing with and without decoupling, (b) q-axis voltage transient response to load changing with and without decoupling, (c) d-axis
current reference tracking in transition time with decoupling, (d) q-axis current reference tracking in transition time with decoupling

Fig. 6 Simulation results with decoupling and compensation

(a) Three-phase voltage in transition time, (b) Three-phase current in transition time, (c) Three-phase voltage in the presence of non-linear load, (d) Voltage THD in the presence of
non-linear load

for the VCL of the stand-alone VSI, where the controller should
stabilise the output voltage as fast as possible, is very critical. With
the help of decoupling and compensation technique, it is possible
to choose a larger proportional gain to enhance the response speed
while keeping the overshoot under limit. Figs. 5c and d show the
transient response of d- and q- axis current, respectively, at the
transition time. As it can be seen, the transient response for CCLs
with decoupling process is very fast with a zero steady-state error.
Figs. 6a and b show the three-phase voltage and current at the
transition time as the load changes. As it can be seen, the transient
response is very fast and stable.
To evaluate the performance of the controller in the presence of
non-linear loads, the simulation is conducted again with an RL load
in the presence of an uncontrolled three-phase rectifier. The three-
phase rectifier is followed by an LC filter (L = 50 mH, C = 710 μF)
and loaded with R = 55 Ω, as non-linear load. It is worth noting
that the non-linear load is %39.91 of the total load. Figs. 6c and d
show the three-phase output voltage and the THD for the phase A
of which, as it can be seen the THD is 1.34%, which is way below
the limit (5%) defined by the IEEE standard 519 [36].
6.2 Experimental and simulation results for the same power
level
To evaluate the modelling and controller design performance, the
experimental results for the stand-alone VSI under different load

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© The Institution of Engineering and Technology 2017
conditions are presented. Fig. 7 shows the hardware setup. It
should be noted that the controller is re-tuned according to
Fig. 7 Hardware setup
Table 2 Hardware setup parameters
Parameters
DC-link voltage (V)
L–L rms voltage (V)
nominal frequency (Hz)
filter inductor ESR (Ω)
filter inductor (mH)
filter capacitor (μF)
switching frequency (kHz)
CCL proportional gain (K pi)
CCL integral gain (K ii)
VCL proportional gain (K pv)
VCL integral gain (K iv)
resistive load #1 (Ω)
resistive load #2 (Ω)
non-linear load (rectifier load)
Fig. 8 Simulation results for the same power level as that used in the experiment
(a) Three-phase current in transition from the light resistive load to the heavy load, (b) Three-phase voltage in transition to the non-linear load, (c) Voltage THD for non-linear load,
(d) Current THD for non-linear load
1010
hardware parameters. Table 2 summarises the parameters for the
hardware setup and controller in experiment. However, to provide
a base for the comparison, simulation is conducted again on the
same power level as the hardware test.
In the simulation phase, the VSI initially feeds a light resistive
load of 50 Ω. Then, to test the stand-alone VSI abilities to respond
to heavy loads, the load is tripled at t = 0.5 s (a 25 Ω load is
connected in parallel with the first load), which is a heavy change
in load. The three-phase current transient response, when the load
changes, is shown in Fig. 8b. As it can be seen, the currents
amplitude are tripled and the transition is quite fast and stable. To
examine the stand-alone VSI's ability to maintain the voltage and
power quality in the presence of non-linear loads, a diode-based
rectifier bridge is added to the initial load. The rectifier is followed
by an LC filter and loaded with a resistive load. Values of the LC
filter components and resistive load are mentioned in Table 2.
Fig. 8a shows the three-phase voltage when the non-linear load is
added at t = 1.5 s (notice that the second resistive load is removed
at t = 1 s). The non-linear load is ∼24% of the total load and, as it
can be seen, the voltage waveform maintains a good quality. To
provide a quantitative quality evaluation, the voltage and current
harmonics along with the THD of the voltage and current are
shown in Figs. 8c and d. As it can be seen, the harmonics and THD
level are maintained in an acceptable level.
Values In the experimental stage, the stand-alone VSI first starts with a
resistive load of 50 Ω per phase, similar to the simulation process,
120
then at t = 6.91 s the second resistive load of 25 Ω per phase is
61.24 connected (load is tripled). The transition current for this load
60 change is shown in Fig. 9b, which shows a fast and stable response
0.364 for CCLs, which is similar to simulation results in Fig. 8b. Then,
2.5 the second resistive load is disconnected at t = 22.95 s and the non-
5 linear load is connected at t = 34.525 s, the non-linear load is the
same as that in the simulation. Three-phase voltage when the non-
10
linear load is connected is shown in Fig. 9b, which show the good
20.35 quality of voltage even when supplying non-linear load. Figs. 9c
40 and d show the THD for the phase A of voltage and current,
0.0074 respectively, in the presence of the rectifier load. The THD values
shown in Figs. 9c and d are obtained by using the MATLAB fast
45 Fourier transform (FFT) analysis tool for harmonics up to 25th.
50 Notice that in these figures, vertical axes show the harmonic values
25 as a percentage of the fundamental component, and the
L = 5.6 mH, C = 210 μF, R = 100 Ω fundamental component bar goes to 100%, instead of the truncated
values of 4.5 and 5% shown in Figs. 9c and d, respectively. To
IET Power Electron., 2017, Vol. 10 Iss. 9, pp. 1003-1012
© The Institution of Engineering and Technology 2017
Fig. 9 Experimental results under different load scenarios
(a) Three-phase current in transition from light resistive load to heavy load, (b) Three-phase voltage in transition to non-linear load, (c) Voltage THD for non-linear load, (d) Current
THD for non-linear load

Table 3 Harmonics as a percentage of fundamental

component THD(voltage)
Harmonic order Voltage Current
(0.6h1 /100)2 + (0.5h1 /100)2 + (0.51h1 /100)2 + ⋯
h2 0.6 0.87 =
h1
h3 0.5 0.53
h4 0.51 0.55 = 3.63%
h5 1.65 4.14
h6 0.8 0.63
THD(current)
h7 2.25 1.06
h8 0.32 0.15 (0.87h1 /100)2 + (0.53h1 /100)2 + (0.551h1 /100)2 + ⋯
=
h9 0.35 0.42 h1
h10 0.53 0.49 = 4.6% .
h11 1.33 0.18
h12 0.42 0.26 Notice that these THDs are calculated for harmonics up to 16th,
h13 1.14 0.66 and this is the reason why these values are lower than those shown
h14 0.1 0.08 in Figs. 9c and d (as it was mentioned earlier, they are calculated
for harmonics up to 25th).
h15 0.19 0.1
To provide a performance comparison between dq-current
h16 0.24 0.43 controllers in the simulation and experiment, over the whole load
changing process, addition or shading of load, the d-axis current
for both the experiment and simulation is shown in Fig. 10. The
verify the validity of presented THD values, the THD can be simulation is conducted over a 5 s period of time and the
calculated as [36]. experiment is ran for 60 s (the non-linear load is disconnected at t
= 2 s, and t = 45.5 s for simulation and experiment, respectively).
∑n h2n Since the loads under the test are dominantly resistive, the q-axis
THD = n⩾2 (12) current is almost zero and is not shown here.
h1

where h1 is the fundamental component of a signal and hn is the nth

harmonic. The values of different harmonics for phase A of voltage
and current signals, as a percentage of their corresponding
fundamental components, are provided in Table 3. Therefore, the
voltage and current THDs are
7 Conclusion
This paper presents a detailed analysis and modelling for a stand-
alone VSI in the dq reference frame, and a new perspective through
a graphical analysis approach on the decoupling and compensation
process of the current and VCLs. Besides, the detailed controller
design procedure of the current and voltage loop controllers is
shown. The paper also investigated closed-loop output impedance
of the VSI system in the dq-reference frame and the impact of
decoupling and compensation process on the dq output impedance,
which would give a better insight for the output impedance
characteristics and help the design of an appropriate power

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© The Institution of Engineering and Technology 2017
Fig. 10 d-axis current over the whole simulation and experiment with different load scenarios
(a) Simulation, (b) Experiment
controller for different VSI applications. The simulation and
experimental results for both linear and non-linear loads verify the
analysis presented in this paper and performance of the VSI
current- and voltage-loop controllers.
8 Acknowledgments
This work was supported in part by the U.S. National Science
Foundation under grant no. 1414379.
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IET Power Electron., 2017, Vol. 10 Iss. 9, pp. 1003-1012
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