Date: 17.10.

21

Fall Semester 2021 -2022

ECE5017- Digital Design With FPGA-Lab

MTech – VLSI Design

Amit Verma

21MVD0142(slot-2)
 TASK-2

Designing of a 16-bit ALU in structural modelling using Verilog HDL, which performs the
following functions as shown in table.

VERILOG CODE:

module alu (d, co, a, b, ficin);

output [15:0] d;
output co;
wire [4:0] d;
wire co;
input cin;
input [15: 0] a, b;
input [2: 0] f;
assign {co, d} =(f==3'b000)? (a+b+cin) :((f==3'b001)? (a+1) :(((f==3'b010)? (a-b) :(f==3'b011)?
{1'b1, a-1}: {1'bz, a*b})));
endmodule
module alu1_tb (); //test-bench
reg [15:0] a, b;
reg [2:0] f;
reg cin;
wire [15:0] d;
wire co;
alu m0(d, co, a, b, f, cin);
initial
begin
cin= 1'b0;
f = 3'b000;
a = 16'h0;
b = 16'h0;
end
always
begin
#1cin = 1'b0; f = 3'b000; a = 16'h24; b = 16'h10;
#1cin = 1'b0; f = 3'b001; a = 16'h9; b = 16'h1;
#1cin = 1'b0; f = 3'b010; a = 16'h16; b = 16'h3;
#1cin = 1'b0; f = 3'b011; a = 16'h5; b = 16'h6;
#1cin = 1'b1; f = 3'b10z; a = 16'h5; b = 16'h2;
end
endmodule

Output Waveform:
1. Performs addition of two number in 16-bit when f = 000, a = 16'h24; b = 16'h10.
2. Performs A+1 of two number in 16-bit when f = 001, a = 16'h9; b = 16'h1.

3.Performs A-B of two number in 16-bit when f = 010, a = 16'h16; b = 16'h3.

4.Performs A-1 of two number in 16-bit when f = 011, a = 16'h5; b = 16'h6.

5.Performs A*B of two number in 16-bit when f = 10x, a = 16'h5; b = 16'h2.