UNIVERSITI TEKNOLOGI MARA

FACULTY OF ELECTRICAL ENGINEERING

ELECTRICAL ENGINEERING LABORATORY 4

(EEE535)

PROBLEM BASED LEARNING (PBL) MODULE

EXPERIMENT DDCA 2 (DIGITAL DESIGN AND COMPUTER ARCHITECTURE)

TITLE:

DESIGN OF DAYTIME RUNNING LIGHTS LED

PREPARED BY:

A'ISYAH NADIYAH BINTI HILMI 2021117873 PEE2006C2

NUR ATIQAH BINTI AZMAN 2021102771 PEE2006C2
NUR FAREENA EZANI BINTI AS'AD 2021100755 PEE2006C2

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 LABORATORY ASSESSMENT
FACULTY OF ELECTRICAL ENGINEERING
UNIVERSITI TEKNOLOGI MARA
ELECTRICAL ENGINEERING LABORATORY 4 (EEE535)

Experiment Title: DESIGN OF DAYTIME RUNNING LIGHTS LED Lecturer: DR NOR SHAHANIM MOHAMAD HADIS

Experiment Date: 5/1/2023 Group: PEE2006C2

Submission Date: 26/1/2023

Student Name Student Id
S1.
A'ISYAH NADIYAH BINTI HILMI 2021117873

S2. NUR ATIQAH BINTI AZMAN 2021102771

S3.
NUR FAREENA EZANI BINTI AS'AD 2021100755

D. LONG REPORT ASSESSMENT (55%)

CO Criteria Poor Fair Good Very Good Weight Score (s) Marks(s x w)
(w)
1.0 – 2.0 3.0 – 4.0 5.0 – 7.0 8.0 – 10.0 S1 S2 S3 S1 S2 S3
1 CO1- Report format & Major Some Complete Complete 0.5
PO4 Organization criteria are criteria are report & report &
 General format missing, missing. fully fully
& structure untidy, bad Poor complied complied
 Cover page, presentation presentation with with
title, objectives criteria. criteria.
 Presentation Nicely
presented

2 CO1- Theory & Information Gives very Complied Fully 0.7

PO4 background irrelevant, or little with the complied
 Theory & copied information criteria the criteria
background directly from related to with minor supported
related to the main source the mistakes by figures
experiment experiment or
 Ideas from diagrams
several sources

3 CO1- Methods / Most steps Some of the Most of the Presents 0.7
PO4 procedures are missing steps are steps are logical,
 Steps & or are clear, most clear, easy to
methodologies confusing or are some lack follow and
are described in just follow confusing of details understand
the passive exactly as and lack of or are
voice given in the details confusing
 Include circuit lab sheet
diagrams,
design
calculations,
flow chart, etc

4 CO1- Results Major data Incomplete Complete Complete 1.2

PO4  Presentation of are missing results, and, neatly and
results in the major presented, accurate
form of table, mistakes minor results,
graphs etc. mistakes neatly
 Accuracy of data presented
measured/
obtained
5 CO1- Discussions Very few Some point Some All point of 1.6
PO4  Ability to points of of point of discussions
present, discussion, discussions discussions on the
interpret, and not properly on the on the results
analyze results elaborated results results obtained
 Compare with obtained obtained covered
theoretical covered but covered and
values for ideal not properly and elaborated
case condition elaborated elaborated
 Application to
industries

(CPS: WP2, WP3)

6 CO1- Conclusion Irrelevant The closing The closing The closing 0.6
PO4  Provides answer conclusion paragraph paragraph paragraph
to objectives attempts to summarize summarize
stated earlier summarizes s & draws s & draws
 Ability to learn but draws a a sufficient a well
something from weak developed developed
the experiment conclusion conclusion conclusion
7 CO1- References Less than Less than Four or Four or 0.2
PO4  Used in the four four more more well-
report appropriate appropriate appropriat chosen
 Documented on sources are sources are e sources sources
the last page documented documented are are
but not used & used documente documente
d & but not d & used
used
TOTAL MARKS=∑(s x w)
TABLE OF CONTENTS

1.0 OBJECTIVES ________________________________________________________ 3

2.0 THEORY ____________________________________________________________ 3

2.1 CLOCK DIVISION _______________________________________________ 3

2.2 TOGGLE ______________________________________________________ 4

2.3 COUNTER 12-BITS _____________________________________________ 5

2.4 FINITE-STATE MACHINE (FSM) ___________________________________ 6

3.0 PROCEDURE ________________________________________________________ 8

4.0 RESULT ____________________________________________________________ 13

4.1 CLOCK DIVISION _______________________________________________ 13

4.2 SPEED _______________________________________________________ 15

4.3 TOGGLE ______________________________________________________ 16

4.4 COUNTER ____________________________________________________ 18

4.5 FSM __________________________________________________________ 19

4.6 TOP MODULE __________________________________________________ 23

5.0 DE2-115 FPGA board __________________________________________________ 24

5.1 Pin Assignment _________________________________________________ 24

5.2 Real-time ______________________________________________________ 24

6.0 DISCUSSION _________________________________________________________ 25

7.0 CONCLUSION ________________________________________________________ 28

REFERENCE ____________________________________________________________ 29

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1.0 OBJECTIVES

1. To design daytime running lights LED using hardware description language (HDL) Verilog
codes
based on the given design problems and architecture using Quartus software.
2. To write test benches using HDL Verilog codes and verify the design functionality via
timing simulation waveform using QuestaSim software.
3. To download the design into DE2-115 FPGA board and demonstrate the design
functionality in real-time

2.0 THEORY

2.1 CLOCK DIVISION

All other signals are referenced to clocks, which are the primary synchronizing events.
The Clock generator is written in Verilog if the RTL is written in Verilog, even if the TestBench is
written in another language such as Vera, Specman, or SystemC. The clock can be generated in
a variety of ways. Some testbench applications require more than one clock generator. So, while
testbench requires a clock with different phases, others require a clock generator with a jitter.
Because the clock has an unknown value before time zero and is assigned a value at time zero,
the very first transition of the clock at time zero may be perceived as a transition. A clock divider,
also known as a frequency divider, divides the frequency of the input clock to produce the output
clock. In our case, we'll take a 50MHz input frequency and divide it by the clock frequency to get
a 1KHz output signal.

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 Figure 2.1.1: The diagram of clock division

2.2 TOGGLE

The feature of a flip-main flop is that it changes its output state in response to a positive
or negative change in the control signal. The letter "T" in "T flip-flop" stands for "toggle," as in
"toggling" a light switch between states. This is what happens when users provide a logic-high
input to a T flip-flop: if the output is currently logic high, it changes to logic low; if the output is now
logic low, it changes to logic high. When a logic-low input is applied to the T flip-flop, it maintains
its current output state. When a clock signal's frequency needs to be reduced, T flip-flops come
in help. The output will change state once each clock period if the T input is kept at logic high and
the original clock signal is used as the flip-flop clock. As a result, the frequency of the output clock
will be half that of the input clock.

Figure 2.2.1: The diagram of toggle

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 Table 2.2.1: Truth Table for Toggle

2.3 COUNTER 12-BITS

A binary counter is an electronic component that counts the number of pulses it receives.
It is called binary because it stores the number in binary form. Counters are extremely common
in electronics, and they can be used to build circuits ranging from memory chips to FM radio
decoders. a 12-bit asynchronous binary counter with the outputs of all stages available externally.
A high level at the clear (CLR) input clears the counter and resets all outputs to zero
asynchronously. A high-to-low transition at the clock (CLK) input advances the count.

Figure 2.3.1: The diagram of Counter 12-bits

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 A counter is used to keep track of how many clock pulses are applied to a flip-flop. It can
also be used as a frequency divider, a timer, a frequency counter, a distance counter, and a
generator of square waveforms. There may be a delay in providing output since the flip-flops are
asynchronous counters and are supplied with distinct clock signals. Depending on the input
control, a counter can be an up counter that counts upwards, a down counter that counts
downwards, or a counter that counts both up and down. After a certain point, the counting the
sequence is frequently repeated. Counters are commonly used to divide clock frequencies, and
their primary applications are in digital clocks and multiplexing.

2.4 FINITE-STATE MACHINE (FSM)

A finite state machine is a computation model that can be implemented using hardware or
software to simulate sequential logic and some computer programmes. Regular languages are
generated by finite state automata. Finite-state machines can be used to model problems in a
wide range of disciplines, including mathematics, artificial intelligence, games, and linguistics.
Finite state machines are classified into two types: deterministic finite state machines, also known
as deterministic finite automata, and nondeterministic finite state machines, also known as
nondeterministic finite automata. There are minor differences in how state machines are visually
represented, but the concepts behind them are the same. Regular languages are recognized or
accepted by deterministic finite automata, and a language is regular if a deterministic finite
automaton accepts it. FSMs are typically taught using languages composed of binary strings that
follow a specific pattern. Binary strings can be used to create both regular and non-regular
languages. The language of all strings with a 0 as the first character is an example of a binary
string language. 001, 010, 0, and 01111 are valid strings in this language (along with many
others), but 111, 10000, 1, and 11001100 (along with many others) are not.

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2.4.1: The figure of Finite State Machine (FSM)

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3.0 PROCEDURE

1. A new project was created by opening a new project wizard in Quartus software.
2. The Cyclone IV E and EP4CE115F29C7 were chosen to suit the specification of DE2
115 FPGA board.

Figure 3.1: Family & Device Settings for DE2 115 FPGA board.

3. The design file and Verilog testbench codes were written for Clock Division module.

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 Figure 3.2: Verilog code for the clock division from 50MHz to 1kHz clock.

Figure 3.3: Verilog Testbench code for the clock division for timing diagram.

4. The testbench module was set as Top-Level Entity and simulated to verify its
functionality using timing simulation waveform.

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 Figure 3.4: Analysis and synthetization of clock division testbench module.

5. The RTL Simulation was run to generate and observe the timing diagram for Clock
Division.

Figure 3.5: Simulation process in Questa to generate clock division wave.

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 Figure 3.6: Timing diagram of the clock division module.

6. The 1st until 5th procedures were repeated to create speed, toggle, counter, Finite State
Machine (FSM) and lastly the top module.
7. The location of the input and output on the DE2-115 board were set by referring to the pin
assignment table and the manual of the board.

Figure 3.7: Pin Planner settings.

8. The program was downloaded after it had been successfully run and compiled.
9. The FPGA board was connected, and the downloaded program was then added to the
board to start the simulation.

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Figure 3.8: Process of connected and downloaded the program to the DE2 115 FPGA board.

10. The program was then tested and observed on the DE2 115 FPGA board.

Figure 3.9: LEDs on the DE2 115 FPGA board.

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4.0 RESULT

4.1 CLOCK DIVISION

Figure 4.1.1 clk_division design file code

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Figure 4.1.2 clk_division test bench file code

Figure 4.1.3 Timing diagram for clk_division

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4.2 SPEED

Figure 4.2.1 Speed design file code

Figure 4.2.2 Speed test bench file code

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 Figure 4.2.3 Timing diagram for Speed

4.3 TOGGLE

Figure 4.3.1 Toggle design file code

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Figure 4.3.2 Toggle test bench file code

Figure 4.3.3 Timing diagram forToggle

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4.4 COUNTER

Figure 4.4.1 counter12 design file code

Figure 4.4.2 counter12 test bench file code

Figure 4.4.3 Timing diagram for counter12

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4.5 FSM

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20
Figure 4.5.1 FSM design file code

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Figure 4.5.2 FSM test bench file code

Figure 4.1.3 Timing diagram for FSM

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4.6 TOP MODULE

Figure 4.6.1 Top_LED design file code

Figure 4.6.2 Top_LED test bench file code

Figure 4.6.3 Timing diagram for Top_LED

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5.0 DE2-115 FPGA board

5.1 PIN ASSIGNMENT

Figure 5.1.1 Pin Assignment

5.2 REAL-TIME

Figure 5.2.1: Real time FPGA board

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6.0 DISCUSSION

6.1 CLOCK DIVISION

For the first sub-module, the Clock Division module was constructed. The clock frequency
used from the DE2-115 FPGA board as master clock input is clk_50Mhz. The frequency needs
to be reduced to 1kHz so it can be used by another sub-module which is FSM and Counter. For
the first if-else statement, for the first condition, the program will reset to 0 if the button reset is
being pressed. Clk_1khz and cnt will equal to zero. If the count is equal to 32’h61A8 in
hexadecimal which equals to 25000 in decimal, the clock_1kHz will change its logic output either
from 0 to 1 or from 1 to 0. If the count is not equal to 32’h000061A8, the count will be added with
the value of 1. As for the waveform of the clock division, the clock will only operate when at positive
edge only and reset will happen at negative edge if the button is being pressed. The 25k value
was gotten from calculation of 50M divided to 1k which will get the value of 50k. The value for 50k
then will be divided by 2 for half cycle which will produce the value of 25k which is equal to
0.0004s. For producing timing diagram, the count was reduced to 32’h00000008 to decrease the
amount of time for the simulation.

6.2 SPEED

The speed sub-module was built with the input declared as I_speed and the output
declared as o_speed. The input was assigned 2 bits, and the output was assigned 12 bits. Case
statements were implemented in these sub-modules in such a way that the output 12bit changes
in response to the 2bit input. This is due to the four different speeds that the user selects based
on the input. In terms of the timing diagram, the input and output were valid using the values given
in the lab manual: 00 = 300 ms, 01 = 200 ms, 10 = 100 ms, and 11 = 50 ms. The output shown
in the timing diagram is in binary code, and it is the same when converted to decimal. As for
output, we use parameter P0 for 2’b00, P1 for 2’b01, P2 for 2’b10 and P3 for 2’b11.

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 6.3 TOGGLE

The 12 LEDs' output conditions will be inverted by the "toggle" input pin's two 6-bit output
signals ("oQR[5:0]" and "oQL[5:0]"), which will cause the LEDs to move in opposite directions.
Three inputs, including two from the FSM output and one from a toggle, are present in the toggle
submodule Verilog code. Two outputs, designated as oQL and oQR, are also present. The LEDs
will light up according to the coding (oQL=QL and oQR=QR) if the toggle is set to "0," but if it is
set to "1," oQL will invert from QL and oQR will invert from QR. Then, it used an always and an
if-else statement as a selector in this code.

6.4 COUNTER

The counter submodule must count the delay for every positive edge (1ms), the counter
will add one until the value of speed is counted. The value will reset and allow it to count the next
operation. The inputs were the clock (CLK) and reset, and the output, or count, was sent to the
FSM. This sub-output module's is 12 bits long, and the transition used in the Verilog code is an if
else statement. If the user presses the reset button, the count will be 12 bits of zero; otherwise,
the count will add a value of 12 bits of one. Following that, the output and input of the testbench
code for this submodule are identical to those of the Verilog code. The 12-bit counter counts up
and outputs counted values on each rising edge of the clock.

6.5 FSM

A finite state machine, also known as a finite state automation, is a type of computation
model that can be used to imitate sequential logic and some computer programs. It can be
implemented using hardware or software. Problems in a variety of disciplines, such as
mathematics, artificial intelligence, gaming, and linguistics, can be modelled using finite state
machines. Finite state machines can be used to depict a system where certain inputs lead to
specific state changes. For the most part, digital design is based on finite state machines (FSMs).
The fundamental function of an FSM is to store a sequence of distinct states and transition
between them in accordance with the values of the inputs and the machine's current state. There
are two different forms of FSM: Moore (where the state machine's output is solely based on the
state variables) and Mealy (where the output can depend on the current state variable values and
the input values).

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 The FSM used in this experiment has three inputs: clock 1kHz, reset, a 12-bit counter,
and 12-bit output of the speed, these parameters were intended to produce LED outputs using
QL for left and QR for right LEDs as shown in Figure 5.5.1. The current state and next state
condition will be registered by the FSM for this design to display the execution of this module.
Written in Quartus, the Verilog code for the FSM module uses 6 bits on each side of the output
LED. These are the parameters for the seven states used to display how the system is being used
when the bits value is detected, with state1 beginning with state1 = 6'b000000 which means all
LEDs were OFF and state7 concluding with state7 = 6b'111111, showing all LEDs were ON.

The LED values for the initial state of the FSM module, QL= 6b'000000 for the left LEDs
and QR= 6b'000000 for the right LEDs, indicate that no LEDs are lit in this condition. This sub
module introduces the reset count (reset_cnt) statement which will be activated when low input
was detected and will auto reset when reach 25 000 counts. The reset count value is examined
by the if statement, and if it is 1, state 2 is the next state. The following if else will check whether
the next state will change even though it is still in the same state if reset count is 0. From state 1
to state 7, and then back to state 1, this also extended to other states. The timing diagram is
extracted from the Questa software using the FSM testbench. The input and output for the
testbench FSM are identical to those for the FSM Verilog code. All input values will be reset to 0
by the testbench FSM, which will then reset all subsequent values to 1 to start the timing diagram.
All input values will be reset to 0 by the testbench FSM, which will then reset all subsequent values
to 1 to start the timing diagram.

6.6 TOP MODULE

For this lab, the top-level design which is Top_LED consists of 5 sub-modules named
clock division (clk_division), Speed, toggle, Counter (counter12), and FSM. As can be seen in
Figure 5.6.1 above, other sub-modules were called using module instantiation. This module
basically calls for other sub-modules.

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7.0 CONCLUSION

From this lab, we can conclude that students learned how to use Quartus II software to
design LED daytime running lights using hardware description language Verilog (HDL) codes to
solve the given design problems and their architecture. To complete this experiment, students
must create five sub-modules: Clock Division, FSM, Speed, Counter, and Toggle. Students
learned how to design test benches for each sub-module using HDL Verilog codes, with the top
module test bench being the most important. QuestaSim is used to test the design functionality
using a timing diagram simulation waveform immediately after writing the test bench. Verilog HDL
codes were used for each sub-module and the Top module's test benches, and the design
functionality was verified using the Questasim timing simulation waveform. From this lab, FPGA
boards were used to produce the output.

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REFERENCE

1) TestBench, "Verilog for Verification," TESTBENCH.IN, 21 July 2016. [Online]. Available:

http://www.testbench.in/TB_08_CLOCK_GENERATOR.html#:%7E:text=Clocks%20are
%20the%20main%20synchronizing,more%20than%20one%20clock%20generator
2) R. Keim, "T is for Toggle: Understanding the T Flip-Flop," All About Circuits, 17 April 2018.
[Online]. Available: https://www.allaboutcircuits.com/technical-articles/t-is-for-
toggleunderstanding-the-t-flip-flop/
3) T. I. Incoperated, "Texas Instrument," 2020. [Online]. Available:
https://www.ti.com/lit/ds/symlink/sn74lv4040aep.pdf?ts=1626358680458&ref_url=https%
253A%252F%252Fwww.google.com%252F
4) M. L. Bors, "What is a Finite State Machine?," Medium, 11 March 2018. [Online]. Available:
https://medium.com/@mlbors/what-is-a-finite-state-machine-6d8dec727e2c

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