JEDEC

STANDARD

Stress-Test-Driven Qualification of
Integrated Circuits

JESD47D
(Revision of JESD47C.01)

NOVEMBER 2004

JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

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 JEDEC Standard No. 47D

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

CONTENTS
Page

1 Scope 1

2 Reference documents 2
2.1 Military 2
2.2 Industrial 2

3 General requirements 2
3.1 Objective 2
3.2 The use of generic data to satisfy qualification requirements 2
3.3 Test samples 3
3.3.1 Lot requirements 3
3.3.2 Production requirements 3
3.3.3 Reusability of test samples 3
3.3.4 Sample size requirements 3
3.3.5 Prestress and poststress test requirements 3
3.4 Definition of electrical test failure after stressing 3
3.5 Criteria for generic database adequacy 4

4 Qualification and requalification 5

4.1 Qualification of a new device 5
4.2 Requalification of a changed device 5
4.2.1 Process change notification 5
4.2.2 Changes requiring requalification 5
4.2.3 Criteria for passing requalification 5

5 Qualification tests 6
5.1 General tests 6
5.2 Device specific tests 6
5.3 Wearout reliability tests 6
5.4 Flammability/oxygen index 6

6 Explanatory comments regarding process/product changes 15

Annex A 17
A.1 Definition of qualification family 17
A.2 Wafer tab 17
A.3 Assembly process 17
A.4 Multiple family qualification 18

Annex B 19

-i-
JEDEC Standard No. 47D

-ii-
 JEDEC Standard No. 47D
Page 1

STRESS-TEST-DRIVEN QUALIFICATION OF INTEGRATED CIRCUITS

(From Board Ballots JCB-94-61, JCB-01-05, JCB-01-07, JCB-01-08, JCB-01-09, JCB-01-11, JCB-
03-60, JCB-04-69, and JCB-04-106 formulated under the cognizance of JC-14.3 Committee on
Silicon Devices Reliability Qualification and Monitoring)

1 Scope

This standard contains a set of most frequently encountered and accepted reliability stress tests.
These tests are used for qualifying new and changed technology/process/ product families as well
as individual products.

These reliability stress tests have been found capable of stimulating and precipitating
semiconductor device failures, in an accelerated manner.

This set of tests should not be used indiscriminately. Each qualification project should be
examined for:

a) Any potential new and unique failure mechanisms.

b) Any situations where these tests/conditions may induce failures.

In either case the set of reliability requirements/tests and/or conditions should be appropriately
modified to properly comprehend the new situations (for more guidance on this approach see
JESD34 "Failure-Mechanism-Driven Reliability Qualification of Silicon Devices").

The standard format is text for appropriate clarifications and tables summarizing the reliability tests
and conditions.

This document does not relieve the supplier of the responsibility to meet internal qualification
programs.
JEDEC Standard No. 47D
Page 2

2 Reference documents

The revision of the referenced documents shall be that which is in effect on the date of the
qualification plan.

2.1 Military

MIL-STD-883, Test Methods and Procedures for Microelectronics

2.2 Industrial

UL94, Tests for Flammability of Plastic Materials for Parts in Devices and Appliances

ASTM D2863, Flammability of Plastic Using the Oxygen Index Method

IEC Publication 695, Fire Hazard Testing

JESD22, Reliability Test Methods for Packaged Devices

JESD34, Failure-Mechanism-Driven Reliability Qualification of Silicon Devices

JESD46, Guidelines for User Notification of Product/process Changes by Semiconductor Suppliers

3 General requirements

3.1 Objective

The objective of this procedure is to ensure that the device to be qualified meets the most
appropriate and accepted set of stress test driven qualification requirements.

3.2 The use of generic data to satisfy qualification requirements

The use of generic data for qualification will be based on a matrix of specific requirements
associated with major characteristics of the device and manufacturing process. Sources of generic
data may include a supplier's certified test lab, supplier's qualification, user-specific qualifications
and supplier's in-process monitor program. Refer to the process change qualification guidelines
(Table 3) and annex A.

Annex A defines guidelines by which components are grouped into a qualification family.

Table 3 suggests a negotiable set of qualification test guidelines to be performed for a proposed
component/process change.
 JEDEC Standard No. 47D
Page 3

3 General requirements (cont’d)

3.3 Test samples

3.3.1 Lot requirements

Test samples shall comprise representative samples from the qualification family. Manufacturing
variability and its impact on reliability shall be assessed. Where applicable the test samples will be
composed of approximately equal numbers from three (3) nonconsecutive lots, or other
appropriate means may be used, to evaluate variability.

3.3.2 Production requirements

All test samples shall be fabricated and assembled in the same production site and with the same
production process for which the device and qualification family will be manufactured in production.
Other electrical test sites may be used for electrical measurements after the electrical quality is
validated.

3.3.3 Reusability of test samples

Devices that have been used for nondestructive qualification tests may be used to populate other
qualification tests. Devices that have been used in destructive qualification tests may not be used
in subsequent qualification stresses except for engineering analysis.

3.3.4 Sample size requirements

Sample sizes used for qualification testing and/or generic data submission should be consistent
with Table 1. Smaller sample sizes may be used on unique and/or expensive products. Acceptance
criteria for larger generic data sample sizes can be calculated using the method in 3.5.

3.3.5 Prestress and poststress test requirements

Minimum required endpoint test temperatures are specified in the "Additional Requirements"
column of Table 2. Special circumstances (e.g., new technologies) will require testing either (a) at
the extreme application temperatures or (b) at a single guard-banded temperature with the
appropriate temperature correlation data.

Qualification to applications or environments in excess of the original device specified operating

range may require additional qualification testing at the new operating range extreme, if applicable
generic data is not available.

3.4 Definition of electrical test failure after stressing

Poststress electrical failures are defined as those devices not meeting the individual device
specification or other criteria specific to the environmental stress. If the cause of failure is the
result of "mishandling" or EOS, the failure shall be discounted.
JEDEC Standard No. 47D
Page 4

3 General requirements (cont’d)

3.5 Criteria for generic database adequacy

Passing all appropriate qualification tests specified in Tables 1 and 2, either by performing the test
or demonstrating acceptable generic data (using an equivalent total percent defective at a 90%
confidence limit for the total required lot and sample size), qualifies the device per this document.

When submitting test data from generic products to satisfy the Table 1 qualification requirements of
this document, the number of samples and the total number of defective devices occurring during
those tests must satisfy the following mathematical test:

Chi2 4.61
≤
SSgen (SS × # LOTS)T1

where:

Ssgen = generic database sample size

#LOTSgen = number of lots in the generic database

(SS x #LOTS)T1 = Table 1 stress sample size multiplied by the number of lots specified in Table
1

Ssgen = (SS x # LOTS) T1

# LOTSgen = # LOTST1

Chi2 + chi-square goodness-of-fit test statistic at a 90% level of confidence

(a= 0.90). A partial listing of values is included in Table A. The number of
degrees of freedom is D.F.=2(c + 1), where "c" is the number of failures
contained in "SSgen".

Table A C Chi square distribution values at 90% confidence level

c Chi2 c Chi2 c Chi2 c Chi2
0 4.61 5 18.5 10 30.8 15 42.6
1 7.78 6 21.1 11 33.2 16 44.9
2 10.6 7 23.5 12 35.6 17 47.2
3 13.4 8 26.0 13 37.9 18 49.5
4 16.0 9 28.4 14 40.3 19 51.8
 JEDEC Standard No. 47D
Page 5

3 General requirements (cont’d)

3.5 Criteria for generic database adequacy (cont’d)

EXAMPLE Using generic data from 700 samples of Temperature Cycling, the maximum number of
failures that will meet the qualification test requirement is:

(700)(4.61 )
Chi2 ≤ = 13.94 and " c" ≤ 3 failures from the table A.
(3)(77)

4 Qualification and requalification

4.1 Qualification of a new device

New or redesigned products (die revisions) manufactured in a currently qualified qualification family
may be qualified using one (1) wafer/assembly lot.

4.2 Requalification of a changed device

Requalification of a device will be required when the supplier makes a change to the product
and/or process that could potentially impact the form, fit, function, quality and/or reliability of the
device.

4.2.1 Process change notification

Supplier will meet the requirements of JESD46 "Guidelines for User Notification of Product/Process
Changes by Semiconductor Suppliers" for product/process notification changes.

4.2.2 Changes requiring requalification

All product/process changes should be evaluated against the guidelines listed in Table 3.

4.2.3 Criteria for passing requalification

Table 3 lists qualification plan guidelines for performing the appropriate Table 1 stresses. Samples
of any requalification failure group, same stress and same electrical characteristics, should be
analyzed for root cause. Acceptable resolution of root cause and successful demonstration of
corrective and preventive actions will constitute successful requalification of the device(s) affected
by the change.

The part and/or the qualification family can be qualified as long as containment of the problem is
demonstrated until corrective and preventive actions are in place.
JEDEC Standard No. 47D
Page 6

5 Qualification tests

5.1 General tests

Test details are given in Tables 1 and 2. Not all tests apply to all devices. The test that applies to
a particular package type is indicated in the "Note" column of Table 1 and the "Additional
Requirements" column of Table 2. The "Additional Requirements" column of Table 2 also serves to
highlight test requirements that supersede those described in the test reference.

5.2 Device specific tests

The following tests must be performed on the specific device to be qualified for all hermetic and
plastic devices. Passing or failing these tests qualifies or disqualifies only the device under
qualification and not the associated qualification family:

1) Electrostatic Discharge (ESD) - All product - See Table 1.

2) Latch-up (LU) - Only for CMOS and merged technologies containing CMOS. See Table 1.

3) Electrical Characterization - The supplier shall be capable of demonstrating, over the

application temperature range, that the part is capable of meeting parametric limits in the
individual device specification or data sheet.

5.3 Wearout reliability tests

Qualification family testing for the failure mechanisms listed below must be available upon request
when a new wafer fabrication technology or a material relevant to the appropriate wearout failure
mechanism is to be qualified:

C Electromigration

C Time-Dependent Dielectric Breakdown

C Hot Carrier Injection

The data, test method, calculations, and internal criteria need not be demonstrated or performed
on the qualification of every new device.

5.4 Flammability/oxygen index

Certificates of compliance to UL94-0 or ASTM D2863 must be available upon request.

 JEDEC Standard No. 47D
Page 7

5 Qualification tests (cont’d)

Table 1 C Qualification test definitions

Number Accept on #
Stress Abbv. # Note Sample Size per lot
of lots failed
Pre- and post- All qualification parts submitted for
TST 1 HPN
Stress Electrical testing.
High Temp
HTOL 2 HPD 3 (NOTE 4) 77 0
Operating Life
High Temp Bake HTB 3 HPD 1 77 0
Low Temp
LTOL 4 HPN 1 77 0
Operating Life
All surface-mount qualification parts to be
Preconditioning PC 5 SN
subjected to THB or HAST, TC, AC
Temperature
THB 6 PD 3 (NOTE 4) 77 0
Humidity Bias
3 (NOTE 4)
UnBiased HAST UHAST 7a PD 77 0
(NOTE 6)
3 (NOTE 4)
Autoclave AC 7 PD 77 0
(NOTE 6)
Temperature
TC 8 HPD 3 (NOTE 4) 77 0
Cycling
D
Thermal Shock TS 8A 3 77 0
Optional
Power
Temperature PTC 9 HPN 1 77 0
Cycling
Accelerated Soft <1000 FITs for DRAMs
ASER 10 HPN 1
Error Rate < 100 FITs for SRAMs
Performed as a sequential test for mechanical integrity of hermetic packaged devices
Mechanical Shock MS 11 HD 3 (NOTE 4) 39 0
Vibration Variable Performed as a sequential test for mechanical integrity of
VVF 12 HD
Frequency hermetic packaged devices
Constant
CA 13 HD
Acceleration
Gross/Fine Leak may be performed at the beginning of
Gross/Fine Leak GFL 14 HD
the mechanical sequence before mechanical shock test.
All qualification parts submitted for
External Visual EV 15 HPN 0 (NOTE 1)
testing

Physical Cpk>1.66
PD 16 HPN 1 30
Dimensions (NOTE 1)
45 leads; min of 5
Lead Integrity LI 7 HPD 1 0 (NOTE 1)
devices
Lid Torque LT 18 HD 1 5 0 (NOTE 1)
JEDEC Standard No. 47D
Page 8

5 Qualification tests (cont’d)

Table 1 C Qualification test definitions (cont’d)

Number Accept on #
Stress Abbv. # Note Sample Size per lot
of lots failed
0 and Ppk>1.66
Bond Pull 30 bonds from a min or
BPS 19 HPD 1
Strength of 5 devices Cpk>1.33
(NOTE 1)
0 and Ppk>1.66
30 bonds from a min or
Bond Shear BS 20 HD 1
of 5 devices Cpk>1.33
(NOTE 1)
Die Shear DSS 21 HPD 1 5 0 (NOTE 1)
Electrostatic
ESD 22 HPD 1 3/pin combo model 0 (NOTE 5)
Discharge
Electrostatic ESD-
22A HPD 1 3 0
Discharge CDM
Latch-up LU 23 HPD 1 6 0 (NOTE 5)
Internal Water Vapor IWV 24 HD 1 3 0 (NOTE 1)
Solderability SD 25 HPD 3 (NOTE 4) 22 Leads 0 (NOTE 1)
Solvent
SR 26 HPN 1 12 0 (NOTE 1)
Resistance
EEPROM
Endurance ET 27 HPD 3 77 0
Testing
Early Life Fail Rate ELFR 28 HPN (NOTE 2)
Electrical pre: Ppk>1.66
ED 29 HPN 3 (NOTE 4) 30 (NOTE 3)
Characterization post: Ppk>1.00
 JEDEC Standard No. 47D
Page 9

5 Qualification tests (cont’d)

Table 2 — Table of methods referenced

Stress Abbv. # Reference Additional Requirements
Pre- and Post-Stress TST 1 M3000's Test is performed as specified in the applicable
Electrical M4000's test stress reference and any additional
requirements in Table 2.
High Temperature HTOL 2 JA108 125 ºC Ta/1000 hours; At Vcc Max (where dc and/
Operating Life or ac parameters quaranteed); or equivalent
(temperature, voltage, etc. acceleration with
justification.) Bias per Eng. spec static/dynamic
TEST = room temperature pre+post-stress
High Temperature Hours HTB 3 JA103 150 ºC /1000 hours for plastic and 200 ºC/72 for
Bake ceramic packages. Appropriate temperature,
acceleration is allowed.
TEST = room temperature pre+post-stress
Low Temperature LTOL 4 JA108 Test is performed on device families with CMOS
Operating Life design technology (<1 um). –10 ºC a /VCC max
240 hours
TEST = room temperature pre+post-stress
Preconditioning PC 5 JA112 Performed on surface mount devices only. PC
JA113 performed before THB (or HAST), TC and AC
stresses.
TEST = room temperature pre+post-stress
Temperature Humidity Bias THB 6 JA101 85 ºC/85% RH, 1000 hours
(standard 85/85)
with bias applied; min power dissipation
TEST = room temperature pre+post-stress
Temperature Humidity Bias HAST 6 JA110 130 ºC/85% RH, 96 hours or equivalent
(Highly Accelerated or
Temperature and Humidity 110 ºC/85% RH, 264 hours or equivalent
Stress)
with bias applied; min power dissipation
TEST = room temperature pre+post-stress
Autoclave AC 7 JA102 121 ºC/15 psig/96 hours
TEST = room temperature pre+post-stress
Unbiased Temperature UHAST 7a JA118 1300C/85% RH, 96 hours or equivalent
Humidity (Highly or
Accelerated Temperature 1100C/85% RH, 264 hours or equivalent
and Humidity Stress)
without bias applied
TEST= room temperature pre+post-stress
(See NOTE 6)
JEDEC Standard No. 47D
Page 10

5 Qualification tests (cont’d)

Table 2 — Table of methods referenced (cont’d)

Stress Abbv. # Reference Additional Requirements
Temperature Cycling TC 8 JA104 B65 ºC to +150 ºC, 500 cycles
or
B55 ºC to +125 ºC, 1000 cycles
or alternatives with technical justification
TEST = room temperature pre+post-stress
Thermal Shock TS 8A JA106 OPTIONAL may be considered for use as
alternate to Temperature Cycling with technical
justification. Technical justification must show
that the proposed accelerated Thermal Shock
conditions stimulate/precipitate Failure
Mechanisms that have been identified under
product use conditions
NOTE At times Thermal Shock has not detected
Failure Mechanisms that Temperature Cycling
identified and at other times has Thermal Shock
induced Failure Mechanisms not found under
product use conditions.
Typical Thermal Shock conditions:
-65 ºC to +150 ºC for 500 cycles
or
–55 ºC to 125 ºC for 1000 cycles
NOTE It is up to the supplier and user of devices
to discuss which Thermal shock condition is
appropriate for a given package and use condition
and what the results mean for the application
environment under consideration.
TEST: Room temperature pre and post stress
Power Temperature PTC 9 JA105 Test is performed only on devices with Pdiss >1
Cycling watt and Tj rise >40 ºC.
B40 ºC to +125 ºC, 1000 cycles
or
B65 ºC to +150 ºC, 500 cycles
TEST = room temperature pre+post-stress
Accelerated Soft Error ASER 10 M1032 Test is performed only on devices containing a
Rate significant amount of SRAM or DRAM unless
technology generic data is available
Mechanical Shock MS 11 JB104 Y1 plane only, 5 pulses, 0.5 ms duration, 1500
M2002 g peak acceleration. TEST after CA.
Vibration Variable VVF 12 JB103 20 Hz to 2 kHz (logarithmic variation) in >4
Frequency minutes, 4X in each orientation at Service
Condition 1
Constant Acceleration CA 13 M2001 Y1 plane only, 30 kg force for <40 pin packages,
20 kg for 40 pins and greater.
TEST = room temperature pre+post-stress
 JEDEC Standard No. 47D
Page 11

5 Qualification tests (cont’d)

Table 2 — Table of methods referenced (cont’d)

Stress Abbv. # Reference Additional Requirements
Gross/Fine Leak FL 14 JA109 Any fine test followed by any gross test.
M1014 May also be performed at beginning of mechanical
sequence before mechanical shock test.
Physical Dimensions PD 16 M2016 See applicable JEDEC standard outline and
JB100 individual device spec for significant dimensions
and tolerances. See NOTE 1
Lead Integrity LI 17 M2004 NOTE 1
JB105
Lid Torque LT 18 M2024 NOTE 1
Bond Pull Strength BPS 19 M2011 NOTE 1
Bond Shear BS 20 JB116 NOTE 1
Die Shear DSS 21 M2019 NOTE 1
Electrostatic Discharge ESD 22 M3015 HBM (Human Body Model) required at initial
characterization, when ESD protection structure
is changed and when fab process changes may
affect performance.
Electrostatic Discharge ESD- 22A JC101 CDM (Charged-Device Model) required at initial
CDM characterization, when ESD protection structure
is changed and when Fab and package
configuration may affect performance
TEST = Room Temperature
Latch-up LU 23 JESD78 Only for CMOS and merged technologies
containing CMOS
(NOTE 5)
Internal Water Vapor IWV 24 M1018 NOTE 1
Solderability SD 25 M2003 Samples must be representative of the
JB102 manufacturing flow. NOTE 1.
Solvent Resistance SR 26 M2015 Not required for inkless or laser marked devices.
All others see NOTE 1.
EEPROM Program/Erase ET 27 JA117 All re-programmable nonvolatile memories to be
and Data Retention subjected to HTOL and HTB with durations based
on memory density and specified number of.
Program/erase cycles.
NOTE This is required for process technology
qualifications and may not be required for individual
product qualifications.

For re-programmable nonvolatile memories only,

including Flash. Test the devices to the specified
maximum number of program -erase cycles
followed by High Temperature Life test (HTOL) and
data retention per HTB.
TEST = high temperature pre + post-stress
JEDEC Standard No. 47D
Page 12

5 Qualification tests (cont’d)

Table 2 — Table of methods referenced (cont’d)

Stress Abbv. # Reference Additional Requirements
Early Life Fail Rate ELFR 28 JA108 Ta = +125 ºC, 48 hours See NOTE 2.
JESD74
Electrical Characterization ED 29

NOTE 1 Manufacturability data, statistical process control data, or process capability study data (Ppk is
preliminary capability index; Cpk is process capability index etc.) may be substituted.

NOTE 2 ELFR process capability demonstration data is required for e ach Technology/Process/product family.
These data are generic in nature and may be the result of an internal reliability monitoring program. If the device
being qualified is the first in the Technology/Process/ product family, this requirement must be com pleted within
one (1) year of qualification completion.

NOTE 3 Minimum total sample. Smaller sample sizes from several wafer lots may be substituted.

NOTE 4 Generic data may be used to meet the three (3) lot requirement. If the amount of data exceeds
3-times -the-sample-size, the methodology of 2.6 must be employed. If there are fewer than three (3) lots of generic
data, stress testing must be performed to ensure that the total data meets the 3 -times -the-sample-size
requirement.

For parts that are deemed expensive, a new technology to the supplier or represent limited risk/low exposure the
supplier may run a total sample size specified in the "sample size per lot" column divided into three (3) sublots
(i.e., 1/3 lot sample size times 3). The supplier is then expected to accumulate data, generic and/or part specific,
over a period of time after qualification that meets the full 3-times -the-sample-size requirement.

NOTE 5 The acceptance number of zero (0) means that all the devices must be considered while determining
the classification of the device. The data shall be available to the customer upon request.

H C Required for hermetic packaged devices only.

P C Required for plastic packaged devices only.

N C Nondestructive test, devices can be used to populate other tests or they can be used for production.

D C Destructive test, devices are not to be reused for qualification or production.

S C Required for surface mount devices only.

Methods:

M C MIL-STD 883, most current revision and notice.

J C JEDEC Standard No. 22, the most current method.

# C Number of the attached procedure.

NOTE 6 Subject to either Autoclave or UnBiased HAST. UnBiased HAST is recommended for organic
substrates .
 Table 3 C Process change qualification guidelines for the selection of tests
7 11
Test # From
2 3 6 or 8 9 - 15 16 17 18 19 20 21 22 23 24 25 27 28 29
Table 2
7a 14
AC or
Process Attribute HTOL HTB THB TC PTC MSQ EV PD LI LT BPS BS DSS ESD LU IWV SD ET ELFR ED EM HCI TDB
UHAST

DESIGN
Active element
C C C m C C dJ C C d d d
design
Circuit rerouting that
f a m C C f g C
impacts reliability
Wafer dimension C e me e e e e C C
WAFER
Lithography C C C m C C g C
Diffusion/doping C m C C g C
Polysilicon C C m C C dJ C
Metalization C C C C m C C C C
Passivation/oxide C k k C m C k C C dJ g n C C C
Backside operation C C m H C m C
FAB site transfer C C C C m H C C C C C J C C C C C
ASSEMBLY
Die overcoat C C C C C m H
Leadframe plating C C C C m C C C C C
Leadframe material C C C m H C C C C C C
Leadframe

JEDEC Standard No. 47D

C C m H C C C C
dimension
Wire bonding C C C H C C m
Die scribe/separate C C C m
Die prep clean C C C m C C C
Package marking C b

Page 13
 Page 14
JEDEC Standard No. 47D
7 11
Test # From
2 3 6 or 8 9 - 15 16 17 18 19 20 21 22 23 24 25 27 28 29
Table 2
7a 14
AC or
Process Attribute HTOL HTB THB TC PTC MSQ EV PD LI LT BPS BS DSS ESD LU IWV SD ET ELFR ED EM HCI TDB
UHAST

Die attach C C C C m H C H C
Molding compound C C C C C m C C C C C
Molding process C C C C C m C C C C
Hermetic sealing H H H H H H H H H
New package C C C C C m H C C C C C C C H C C C
Ass'y site transfer C C C C m H C C C C C C H C C C

2. High Temperature Operating Life 21. Die Shear a Only for peripheral routing
3. High Temperature Bake 22. Electrostatic Discharge b For symbol rework, new cure t, T
6. Temperature Humidity Bias 23. Latchup c If bond to leadfinger
7. Autoclave 24. Internal Water Vapor d Design rule change
7a. Unbiased HAST 25. Solderability e Thickness only
8. Temperature Cycling 27. E2PROM Testing f Dependent on amount of rerouting
9. Power Temperature Cycle 28. Early Life Failure Rate g Only from non-100% burned-in part
11-14 Mechanical Sequence 29. Electrical Characterization H Hermetic only
15. External Visual EM Electromigration J EPROM or E2PROM devices only
16. Physical Dimensions HCI Hot Carrier Injection k Passivation only
17. Lead Integrity TDB Time Dependent Dielectric m For devices requiring PTC
18. Lid Torque n Passivation and Gate Oxide
19. Bond Pull Strength p Passivation and interlevel dieelectric
20. Bond Shear

NOTE A letter or "C" indicates that performance of that stress test should be considered for the appropriate process change.
 JEDEC Standard No. 47D
Page 15

6 Explanatory comments regarding process/product changes

DIE REDESIGN (New/change): Feature design rules (e.g., size, type; NOT a Major Change if
required to correct a design rule violation)

WAFER DIAMETER

WAFER FAB PROCESS: Utilizing different process techniques at critical points (excluding wafer
transport equipment)

DIFFUSION/DOPANT: New material or technique

POLYSILICON: Composition, design rules, process

WAFER FRONTSIDE METAL: Composition, design rules, process and/or technique

PASSIVATION OVERCOAT: composition, design rules, process and/or technique

DIELECTRIC MATERIALS: Composition, design rules, process and/or technique

WAFER BACKSIDE OPERATION: Metal composition, design rules, process and/or technique

WAFER FAB LOCATION

ASSEMBLY PROCESS: Utilizing different process techniques at critical points

DIE COATING: Material, process, and/or technique

LEAD FRAME: Base material, finish, and critical dimensions

BOND WIRE: Material, diameter

BONDING: Process and/or technique

DIE PREPARATION: Separation and clean methods

DIE ATTACH: Material, process, and/or technique

MOLD COMPOUND: Material, composition, process and/or technique

MARKING/SYMBOLIZATION: Process and/or technique

HERMETIC PACKAGE: Material, composition, seal material, process and/or technique

PACKAGE: Dimension or style.

JEDEC Standard No. 47D
Page 16

6 Explanatory comments regarding process/product changes (cont’d)

ASSEMBLY LOCATION

The following changes do not require requalification but do require mature qualification
maintenance programs, e.g., Statistical Process Control (SPC) programs, Process Capability
Studies, Wafer Level Reliability (WLR) programs and/or Reliability Monitor programs to assure
successful implementation.

1) The movement of product manufacturing (wafer fab or assembly) from one location to another
where the new location is already qualified for the same process and techniques only requires
completion of manufacturability tests at the new location.

2) The change of product from one qualified manufacturing process for a given technology to
another qualified manufacturing process for the same technology only requires completion of
manufacturability tests using the second qualified manufacturing process.

3) The addition of previously qualified equipment requires completion of process capability study
only, to assure that the added equipment delivers an adequate process distribution.

4) A change to a test program or test equipment requires proof of continued conformance to

product specification only.

5) Any change in a process, product or material parameter that does not exceed the current
production process range is not a major change.
 JEDEC Standard No. 47D
Page 17

Annex A - (informative)

A.1 Definition of qualification family

A qualification family will be defined by its wafer fab or its assembly attributes.

A.2 Wafer fab

All devices using the same IC technology, process and materials with major elements defined
below, are categorized as one qualification family and are qualified by association when one family
member successfully completes qualification. Family requalification is required when the process
or material is changed.

WAFER FAB TECHNOLOGY (e.g., CMOS, NMOS, Bipolar. etc.)

WAFER FAB PROCESS

Typical considerations for Wafer Fab process description: design rules, lithography technique,
metalization, polysilicon, dielectrics etc.

WAFER FAB SITE

A.3 Assembly process

The processes for plastic and hermetic package technologies must be considered and qualified
separately.

All devices using the same process and materials, major elements defined below, are categorized
as one qualification family and are qualified by association when one family member successfully
completes qualification.

Family requalification is required when the process or material is changed.

PACKAGE TYPE

Including body width (e.g., 300DIP, 600DIP, 150SOIC, 300SOIC. etc.)

ASSEMBLY PROCESS

Typical considerations for assembly process description: leadframe, die attach, package material,
bonding, external lead finish etc.

ASSEMBLY SITE
JEDEC Standard No. 47D
Page 18

Annex A - (informative) (cont’d)

A.4 Multiple family qualifications

When the specific product attribute to be qualified will affect more than one wafer fab or assembly
family, the qualification test vehicles should be:

1) One lot of a single device type from each of the three (3) families that are projected to be most
sensitive to the changed attribute, or

2) Three lots total from the most sensitive families if only one or two exist.

Below is the recommended process for qualifying changes across many process and product
families:

1) Identify all products affected by the proposed changes.

2) Identify the critical structures and interfaces potentially affected by the proposed change.

3) Identify and list the potential failure mechanisms and associated failure modes for the critical
structures and interfaces. Note that steps 1 to 3 are equivalent to the creation of an FMEA.

4) Define the product groupings or families based upon similar characteristics as they relate to the
structures and device sensitivities to be evaluated, and provide technical justification for these
groupings.

5) Provide the qualification test plan, including a description of the change, the matrix of tests and
the representative products, that will address each of the potential failure mechanisms and
associated failure modes.

6) Robust process capability must be demonstrated at each site (e.g. control of each process
step, capability of each piece of equipment involved in the process, equivalence of the process
step-by-step across all affected sites) for each of the affected process steps.
 JEDEC Standard No. 47D
Page 19

Annex B (informative) Differences between JESD47D and JESD47C.01

The following list briefly describes most of the changes made to entries that appear in this
publication, JESD47D, compared to its predecessor, JESD47C.01 (November 2004). If the change
to a concept involves any words added or deleted, it is included. Punctuation changes may not be
included.

Page Description of change

7 In Table 1: Add Unbiased HAST
9 In Table 2: Add Unbiased HAST Test Method option from JESD22A118
12 Added Note 6
13-14 In Table 3: Add 7a for Unbiased HAST

The following list briefly describes most of the changes inJESD47C.01, compared to its
predecessor, JESD47C (November 2004).

Page Description of change

3 In 3.3.4: Changed reference to 2.6 to 3.5. (This has been in error since the
document was renumbered between version JESD47 and JESD47A in November
2001.

The following list briefly describes most of the changes in JESD47C, compared to its predecessor,
JESD47B (August 2003).

Page Description of change

10 Table 2, under Vibration Variable Frequency: In forth column removed reference to
M2007.
10 Table 2, under Vibration Variable Frequency: Deleted; , 50 g peak acceleration TEST
after CA and replaced with: at Service Condition 1.

The following list briefly describes most of the changes in JESD47B, compared to its predecessor,
JESD47A (November 2001).

Page Description of change

9 Table 2, under Temperature Humidity Bias: Deleted; ‘or HAST’, ‘JA110’, and
‘130 ºC/85% RH, 50 hours or equivalent’. Added; (standard 85/85).
9 Table 2, added row: ‘Temperature Humidity Bias (Highly Accelerated Temperature
and Humidity Stress)’
JEDEC Standard No. 47D
Page 20
Standard Improvement Form JEDEC JESD47D

The purpose of this form is to provide the Technical Committees of JEDEC with input from the
industry regarding usage of the subject standard. Individuals or companies are invited to submit
comments to JEDEC. All comments will be collected and dispersed to the appropriate
committee(s).
If you can provide input, please complete this form and return to:
JEDEC Fax: 703.907.7583
Attn: Publications Department
2500 Wilson Blvd. Suite 220
Arlington, VA 22201-3834

1. I recommend changes to the following:

Requirement, clause number

Test method number Clause number

The referenced clause number has proven to be:

Unclear Too Rigid In Error

Other

2. Recommendations for correction:

3. Other suggestions for document improvement:

Submitted by
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