EEE415-Week04-Machine Language

DRAFT 6/20/2023
EEE 415 - Weekly Lecture Plan

Week Lectures Topic Textbook
01 1-3 Patterson 1
Fundamentals of microprocessor and computer design, processor data
path, architecture, microarchitecture, introduction to CISC and RISC,
complexity, metrics, and benchmark
02 4-6 Assembly Language, Harris 6.1-6.3
03 7-9 Assembly Language Programming, Harris 6.3
04 10-12 Machine Language, Compiling, Assembling, Harris 6.4
05 13-15 Performance Analysis, Single Cycle and Multicycle Processor Harris 7.1-7.4
06 16-18 Pipelining, Hazards, Advanced Microarchitecture Harris 7.5,7.7
07 19-21 Memory Systems – Cache and Virtual Memory Harris 8.2-8.4
08 20-24 Introducing Embedded System Design, IoT, Arm Cortex m4 Lecture Slides
09 25-27 General Purpose Input Output Zhu 14
10 28-30 General Purpose Timers Zhu 15.1-15.3
11 31-33 Interrupts Zhu 11, 15.4
12 34-36 ADC + DAC Zhu 20,21
13 37-39 Serial Communication Zhu 22
Dr. Sajid Muhaimin Choudhury 1
EEE 415 - Department of EEE, BUET Digital Design and Computer Architecture: ARM® Edition © 2015
EEE 415 - Weekly Lecture Plan

Week Lectures Topic Textbook
01 1-3 Patterson 1
Fundamentals of microprocessor and computer design, processor data
path, architecture, microarchitecture, introduction to CISC and RISC,
complexity, metrics, and benchmark
02 4-6 Assembly Language, Harris 6.1-6.3
03 7-9 Assembly Language Programming, Harris 6.3
04 10-12 Machine Language, Compiling, Assembling, Harris 6.4
05 13-15 Performance Analysis, Single Cycle and Multicycle Processor Harris 7.1-7.4
06 16-18 Pipelining, Hazards, Advanced Microarchitecture Harris 7.5,7.7
07 19-21 Memory Systems – Cache and Virtual Memory Harris 8.2-8.4
08 20-24 Introducing Embedded System Design, IoT, Arm Cortex m4 Lecture Slides
09 25-27 General Purpose Input Output Zhu 14
10 28-30 General Purpose Timers Zhu 15.1-15.3
11 31-33 Interrupts Zhu 11, 15.4
12 34-36 ADC + DAC Zhu 20,21
13 37-39 Serial Communication Zhu 22
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DRAFT 6/20/2023
EEE 415 - Microprocessors and Embedded Systems
EEE Machine Language
415 Lecture 4.1
Week 4
Dr. Sajid Muhaimin Choudhury, Assistant Professor

Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology
How to Encode Instructions?
– Computer only understands 1s and 0s. Instructions with these.

– 32-bit data, 32-bit instructions
– For design simplicity, would prefer a single instruction format but…
– Instructions have different needs

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How does a 32bit number represent an instruction?

Design Principle 4
Good design demands good compromises
• Multiple instruction formats allow flexibility
- ADD, SUB: use 3 register operands
- LDR, STR: use 2 register operands and a constant
• Number of instruction formats kept small
- toadhere to design principles 1 and 3 (regularity supports
design simplicity and smaller is faster)

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Machine Language
• Binary representation of instructions
• Computers only understand 1’s and 0’s
• Different Representation dependent on Architecture 32-bit instructions

• ARMv7 A 32-bit instructions
• Microcontrollers: 32-bit T2 or 16-bit Thumb architecture

Machine Language Reference

• Microprocessor: ARM v7A profile architecture 32-bit instructions
– ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition
(https://developer.arm.com/documentation/ddi0406/c/) 2734 pages
• Microcontrollers: 32-bit T2 or 16-bit thumb architecture

– ARMv7-M Architecture Reference Manual
(https://developer.arm.com/documentation/ddi0403/latest) 858 pages
• Lab: ARM v8A 32-bit instructions (Last Year)

– Arm Architecture Reference Manual for A-profile architecture

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Different ARM Encoding Versions - ADD

ARM v7 ARM v7M
ARM v8 (Aarch64)

Machine Language Reference

• Microcontrollers: 32-bit T2 or 16-bit thumb architecture

– ARMv7-M Architecture Reference Manual
• Lab: ARM v8A 32-bit instructions

– Arm Architecture Reference Manual for A-profile architecture

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Machine Language in EEE 415

• We limit our discussion to ARMv7A instruction set. Concepts are similar

in other architectures, and instruction sets, but will be completely
different.
• So,the instruction set and rules are not universal for all architectures
(even other ARM architectures are different)
• Without
compiling, a binary code for ARMv7A will not run in ARMv8 or
ARMv7M computers. Dr. Sajid Muhaimin Choudhury 11
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Instruction Formats
• Data-processing
• Memory
• Branch

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Data-processing Instruction Format

• Operands:
– Rn: first source register
– Src2: second source – register or immediate
– Rd: destination register
• Control fields:
– cond: specifies conditional execution
– op: the operation code or opcode
– funct: the function/operation to perform

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Data-processing Control Fields

• op = 002 for data-processing (DP) instructions
• funct is composed of cmd, I-bit, and S-bit
 cmd: specifies the specific data-processing instruction. For example,
 cmd = 01002 for ADD
Control Field
 cmd = 00102 for SUB
 I-bit
 I = 0: Src2 is a register
 I = 1: Src2 is an immediate
 S-bit: 1 if sets condition flags
 S = 0: SUB R0, R5, R7
 S = 1: ADDS R8, R2, R4 or CMP R3, #10

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Cmd Format
instr(11:4)=0
means immediate
na hole
instr(11:4)=0 and EEE 415 - Department of EEE, BUET Dr. Sajid Muhaimin Choudhury 15
baki 3:0 te Digital Design and Computer Architecture: ARM® Edition © 2015
register denoted
15 notation dekhabe(R0-R15).
Cmd Format

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Data-processing Src2 Variations

• Src2 can be:
 Immediate
 Register
 Register-shifted register

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Data-processing Src2 Variations

• Src2 can be:
 Immediate
 Register

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Immediate Src2
• Immediate encoded as:
 imm8: 8-bit unsigned immediate
 rot: 4-bit rotation value
• 32-bit constant is: imm8 ROR (rot × 2)

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Immediate Src2
• Immediate encoded as:
 imm8: 8-bit unsigned immediate ROR by X = ROL by (32-X)
 rot: 4-bit rotation value Ex: ROR by 30 = ROL by 2
• 32-bit constant is: imm8 ROR (rot × 2)
• Example: imm8 = abcdefgh
rot 32-bit constant
0000 0000 0000 0000 0000 0000 0000 abcd efgh
0001 gh00 0000 0000 0000 0000 0000 00ab cdef
… …
1111 0000 0000 0000 0000 0000 00ab cdef gh00

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DP Instruction with Immediate Src2

ADD R0, R1, #42
• cond = 11102 (14) for unconditional execution
• op = 002 (0) for data-processing instructions
• cmd = 01002 (4) for ADD
• Src2 is an immediate so I = 1
• Rd = 0, Rn = 1
• imm8 = 42, rot = 0
Machine Code: 0xE281002A

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DP Instruction with Immediate Src2

SUB R2, R3, #0xFF0
• cmd = 00102 (2) for SUB
• Src2 is an immediate so I=1
ROR by 28 =
• Rd = 2, Rn = 3
• imm8 = 0xFF ROL by (32-28) = 4
• imm8 must be rotated right by 28 to produce 0xFF0, so rot = 14
0xE2432EFF
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DP Instruction with Register Src2

• Src2 can be:
 Immediate
 Register

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• Rm: the second source operand
• shamt5: the amount Rm is shifted
• sh: the type of shift (i.e., >>, <<, >>>, ROR)
First, consider unshifted versions of Rm (shamt5=0, sh=0)

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ADD R5, R6, R7
• cmd = 01002 (4) for ADD
• Src2 is a register so I=0
• Rd = 5, Rn = 6, Rm = 7
• shamt = 0, sh = 0
0xE0865007
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• Rm: the second source operand
Shift Type sh
• shamt5: the amount Rm is shifted LSL 002
• sh: the type of shift LSR 012
ASR 102
ROR 112
Now, consider shifted versions.

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ORR R9, R5, R3, LSR #2
• Operation: R9 = R5 OR (R3 >> 2)
• cmd = 11002 (12) for ORR
• Rd = 9, Rn = 5, Rm = 3
• shamt5 = 2, sh = 012 (LSR)
1110 00 0 1100 0 0101 1001 00010 01 0 0011

0xE1859123

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DP with Register-shifted Reg. Src2

• Src2 can be:
 Immediate
 Register

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DP with Register-shifted Reg. Src2

EOR R8, R9, R10, ROR R12
• Operation: R8 = R9 XOR (R10 ROR R12)
• cmd = 00012 (1) for EOR
• Rd = 8, Rn = 9, Rm = 10, Rs = 12
• sh = 112 (ROR)
1110 00 0 0001 0 1001 1000 1100 0 11 1 1010

0xE0298C7A

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Shift Instructions Encoding
Shift Type sh
LSL 002
LSR 012
ASR 102
ROR 112

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Shift Instructions: Immediate shamt

ROR R1, R2, #23
• Operation: R1 = R2 ROR 23
• cmd = 11012 (13) for all shifts (LSL, LSR, ASR, and ROR)
• Src2 is an immediate-shifted register so I=0 Uses (immediate-shifted)
• Rd = 1, Rn = 0, Rm = 2
register Src2 encoding
• shamt5 = 23, sh = 112 (ROR)
1110 00 0 1101 0 0000 0001 10111 11 0 0010

0xE1A01BE2

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Shift Instructions: Register shamt

ASR R5, R6, R10
• Operation: R5 = R6 >>> R107:0
• cmd = 11012 (13) for all shifts (LSL, LSR, ASR, and ROR)
• Rd = 5, Rn = 0, Rm = 6, Rs = 10 Uses register-
• sh = 102 (ASR)
shifted register
Src2 encoding
1110 00 0 1101 0 0000 0101 1010 0 10 1 0110

0xE1A05A56

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Review: Data-processing Format

• Src2 can be:
 Immediate
 Register

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EEE Machine Language:

Memory and Branch Instructions
415 Lecture 4.2
Week 4

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415 Lecture 4.2
Week 4

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Instruction Formats
• Data-processing
• Memory
• Branch

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ARMv7-A
Memory Instruction Format
Encodes: LDR, STR, LDRB, STRB
• op = 012
• Rn = base register
• Rd = destination (load), source (store)
• Src2 = offset
• funct = 6 control bits

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ARMv7-A
Offset Options
Recall: Address = Base Address + Offset
Example: LDR R1, [R2, #4]
Base Address = R2, Offset = 4
Address = (R2 + 4)
• Base address always in a register
• The offset can be:
 an immediate
 a register
 or a scaled (shifted) register

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ARMv7-A
Offset Examples
ARM Assembly Memory Address
LDR R0, [R3, #4] R3 + 4
LDR R0, [R5, #-16] R5 – 16
LDR R1, [R6, R7] R6 + R7
LDR R2, [R8, -R9] R8 – R9
LDR R3, [R10, R11, LSL #2] R10 + (R11 << 2)
but not register shifted register LDR R4, [R1, -R12, ASR #4] R1 – (R12 >>> 4)
LDR R0, [R9] R9

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ARMv7-A
• op = 012
• Src2 = offset: register (optionally shifted) or immediate but not register shifted register
• funct = 6 control bits

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ARMv7-A

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ARMv7-A
Indexing Modes
Mode Address Base Reg. Update
Offset Base register ± Offset No change
Preindex Base register ± Offset Base register ± Offset
Postindex Base register Base register ± Offset
Examples
• Offset: LDR R1, [R2, #4] ; R1 = mem[R2+4]
• Preindex: LDR R3, [R5, #16]! ; R3 = mem[R5+16]
; R5 = R5 + 16
• Postindex: LDR R8, [R1], #8 ; R8 = mem[R1]
; R1 = R1 + 8

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ARMv7-A
• funct:
 I: Immediate bar
 P: Preindex
 U: Add
 B: Byte
 W: Writeback
 L: Load

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ARMv7-A
Memory Format funct Encodings
Type of Operation
L B Instruction
0 0 STR
0 1 STRB
1 0 LDR
1 1 LDRB

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ARMv7-A
Memory Instructions

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ARMv7-A
Type of Operation Indexing Mode
L B Instruction P W Indexing Mode
0 0 STR 0 1 Not supported
0 1 STRB 0 0 Postindex
1 0 LDR 1 0 Offset
1 1 LDRB 1 1 Preindex

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ARMv7-A
Type of Operation Indexing Mode
L B Instruction P W Indexing Mode
0 0 STR 0 1 Not supported
0 1 STRB 0 0 Postindex
1 0 LDR 1 0 Offset
1 1 LDRB 1 1 Preindex
Add/Subtract Immediate/Register Offset

Value I U
0 Immediate offset in Src2 Subtract offset from base
1 Register offset in Src2 Add offset to base

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ARMv7-A
• op = 012
• Src2 = offset: immediate or register (optionally shifted)
• funct = I (immediate bar), P (preindex), U (add),
B (byte), W (writeback), L (load)

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ARMv7-A
Memory Instr. with Immediate Src2
STR R11, [R5], #-26
• Operation: mem[R5] <= R11; R5 = R5 - 26
• op = 012 (1) for memory instruction
• funct = 00000002 (0)
I = 0 (immediate offset), P = 0 (postindex),
U = 0 (subtract), B = 0 (store word), W = 0 (postindex),
L = 0 (store)
• Rd = 11, Rn = 5, imm12 = 26

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ARMv7-A
Memory Instr. with Immediate Src2
STR R11, [R5], #-26
• Operation: mem[R5] <= R11; R5 = R5 - 26
• funct = 00000002 (0)
I = 0 (immediate offset), P = 0 (postindex),
U = 0 (subtract), B = 0 (store word), W = 0 (postindex),
L = 0 (store)
• Rd = 11, Rn = 5, imm12 = 26

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ARMv7-A
Memory Instr. with Register Src2
LDR R3, [R4, R5]
• Operation: R3 <= mem[R4 + R5]
• funct = 1110012 (57)
I = 1 (register offset), P = 1 (offset indexing),
U = 1 (add), B = 0 (load word), W = 0 (offset indexing),
L = 1 (load)
• Rd = 3, Rn = 4, Rm = 5 (shamt5 = 0, sh = 0)
1110 01 111001 0100 0011 00000 00 0 0101 = 0xE7943005

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ARMv7-A
Memory Instr. with Scaled Reg. Src2
STR R9, [R1, R3, LSL #2]
• Operation: mem[R1 + (R3 << 2)] <= R9
• funct = 1110002 (0)
I = 1 (register offset), P = 1 (offset indexing),
U = 1 (add), B = 0 (store word), W = 0 (offset indexing),
L = 0 (store)
• Rd = 9, Rn = 1, Rm = 3, shamt = 2, sh = 002 (LSL)
1110 01 111000 0001 1001 00010 00 0 0011 = 0xE7819103

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ARMv7-A
Review: Memory Instruction Format
• op = 012
• Src2 = offset: register (optionally shifted) or immediate
• funct = I (immediate bar), P (preindex), U (add),
B (byte), W (writeback), L (load)

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415 Lecture 4.2
Week 4

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Instruction Formats
• Data-processing
• Memory
• Branch

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ARMv7-A
Branch Instruction Format
Encodes B and BL
• op = 102
• imm24: 24-bit immediate
• funct = 1L2: L = 1 for BL, L = 0 for B

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ARMv7-A
Encoding Branch Target Address
• Branch Target Address (BTA): Next PC when
branch taken
• BTA is relative to current PC + 8 that means 2 instruction pore, ejonno 2 add kore
dite hoy
• imm24 encodes BTA
• imm24 = # of words BTA is away from PC+8

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ARMv7-A
Branch Instruction: Example 1
ARM assembly code
0xA0 BLT THERE PC • PC = 0xA0
0xA4 ADD R0, R1, R2 • PC + 8 = 0xA8
0xA8 SUB R0, R0, R9 PC+8 • THERE label is 3
0xAC ADD SP, SP, #8
0xB0 MOV PC, LR instructions past
0xB4 THERE SUB R0, R0, #1 BTA PC+8
0xB8 BL TEST • So, imm24 = 3

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ARMv7-A
ARM assembly code
0xA4 ADD R0, R1, R2 • PC + 8 = 0xA8
0xAC ADD SP, SP, #8

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ARMv7-A
ARM assembly code
0xA4 ADD R0, R1, R2 • PC + 8 = 0xA8
0xAC ADD SP, SP, #8
0xBA000003

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ARMv7-A
ARM assembly code
0x8040 TEST LDRB R5, [R0, R3] BTA
0x8044 STRB R5, [R1, R3] • PC = 0x8050
0x8048 ADD R3, R3, #1 • PC + 8 = 0x8058
0x8044 MOV PC, LR • TEST label is 6
0x8050 BL TEST PC instructions before
0x8054 LDR R3, [R1], #4
0x8058 SUB R4, R3, #9 PC+8 PC+8
• So, imm24 = -6

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ARMv7-A
ARM assembly code
0x8044 STRB R5, [R1, R3] • PC = 0x8050
0x8048 ADD R3, R3, #1 • PC + 8 = 0x8058
0x8054 LDR R3, [R1], #4
0x8058 SUB R4, R3, #9 PC+8 PC+8
• So, imm24 = -6

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ARMv7-A
ARM assembly code
0x8044 STRB R5, [R1, R3] • PC = 0x8050
0x8048 ADD R3, R3, #1 • PC + 8 = 0x8058
0x8054 LDR R3, [R1], #4
0x8058 SUB R4, R3, #9 PC+8 PC+8
• So, imm24 = -6
0xEBFFFFFA

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ARMv7-A
Review: Instruction Formats

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ARMv7-A
Conditional Execution
Encode in cond bits of machine instruction
For example,
ANDEQ R1, R2, R3 (cond = 0000)
ORRMI R4, R5, #0xF (cond = 0100)
SUBLT R9, R3, R8 (cond = 1011)

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ARMv7-A
Review: Condition Mnemonics
cond Mnemonic Name CondEx
0000 EQ Equal 𝑍
0001 NE Not equal 𝑍̅
0010 CS / HS Carry set / Unsigned higher or same 𝐶
0011 CC / LO Carry clear / Unsigned lower 𝐶̅
0100 MI Minus / Negative 𝑁
0101 PL Plus / Positive of zero 𝑁
0110 VS Overflow / Overflow set 𝑉
0111 VC No overflow / Overflow clear 𝑉
1000 HI Unsigned higher 𝑍̅𝐶
1001 LS Unsigned lower or same 𝑍 𝑂𝑅 𝐶̅
1010 GE Signed greater than or equal 𝑁⊕𝑉
1011 LT Signed less than 𝑁⊕𝑉
1100 GT Signed greater than 𝑍̅(𝑁 ⊕ 𝑉)
1101 LE Signed less than or equal 𝑍 𝑂𝑅 (𝑁 ⊕ 𝑉)
1110 AL (or none) Always / unconditional ignored
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ARMv7-A
Conditional Execution: Machine Code
Assembly Code Field Values
31:28 27:26 25 24:21 20 19:16 15:12 11:7 6:5 4 3:0
SUBS R1, R2, R3 14 0 0 2 1 2 1 0 0 0 3

ADDEQ R4, R5, R6 0 0 0 4 0 5 4 0 0 0 6
ANDHS R7, R5, R6 2 0 0 0 0 5 7 0 0 0 6
ORRMI R8, R5, R6 4 0 0 12 0 5 8 0 0 0 6
EORLT R9, R5, R6 11 0 0 1 0 5 9 0 0 0 6
cond op I cmd S rn rd shamt5 sh rm
Machine Code
31:28 27:26 25 24:21 20 19:16 15:12 11:7 6:5 4 3:0
1110 00 0 0010 0 0010 0001 00000 00 0 0011 (0xE0421003)
0000 00 0 0100 0 0101 0100 00000 00 0 0110 (0x00854006)
0010 00 0 0000 0 0101 0111 00000 00 0 0110 (0x20057006)
0100 00 0 1100 0 0101 1000 00000 00 0 0110 (0x41858006)
1011 00 0 0001 0 0101 1001 00000 00 0 0110 (0xB0259006)
cond op I cmd S rn rd shamt5 sh rm

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ARMv7-A
Interpreting Machine Code
• Start with op: tells how to parse rest
op = 00 (Data-processing)
op = 01 (Memory)
op = 10 (Branch)
• I-bit: tells how to parse Src2
• Data-processing instructions:
If I-bit is 0, bit 4 determines if Src2 is a register (bit 4 =
0) or a register-shifted register (bit 4 = 1)
• Memory instructions:
Examine funct bits for indexing mode, instruction, and
add or subtract offset

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ARMv7-A
Interpreting Machine Code: Example 1
0xE0475001
• Start with op: 002, so data-processing instruction
• I-bit: 0, so Src2 is a register
• bit 4: 0, so Src2 is a register (optionally shifted by shamt5)

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ARMv7-A
0xE0475001
• Start with op: 002, so data-processing instruction
• I-bit: 0, so Src2 is a register
• bit 4: 0, so Src2 is a register (optionally shifted by shamt5)
• cmd: 00102 (2), so SUB
• Rn=7, Rd=5, Rm=1, shamt5 = 0, sh = 0
• So, instruction is: SUB R5,R7,R1

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0xE5949010
• Start with op: 012, so memory instruction
• funct: B=0, L=1, so LDR; P=1, W=0, so offset indexing;
I=0, so immediate offset, U=1, so add offset
• Rn=4, Rd=9, imm12 = 16
• So, instruction is: LDR R9,[R4,#16]

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Addressing Modes, Exceptions
415 Lecture 4.3
Week 3

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Addressing Modes
Addressing Mode define how the machine language instructions in that
architecture identify the operand(s) of each instruction. An addressing mode
specifies how to calculate the effective memory address of an operand by using
information held in registers and/or constants contained within a machine
instruction or elsewhere.
How do we address operands?

• Register
• Immediate
• Base
• PC-Relative

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Addressing Modes
• Register Only
• Immediate
• Base
• PC-Relative

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Register Addressing
• Source and destination operands found in registers
• Used by data-processing instructions
• Three submodes:
• Register-only
• Immediate-shifted register
• Register-shifted register

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Register Addressing Examples

• Register-only
Example: ADD R0, R2, R7
• Immediate-shifted register
Example: ORR R5, R1, R3, LSL #1
• Register-shifted register
Example: SUB R12, R9, R0, ASR R1

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Addressing Modes
• Register Only
• Immediate
• Base
• PC-Relative

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Immediate Addressing
• Operands found in registers and immediates
Example: ADD R9, R1, #14
• Uses data-processing format with I=1
• Immediate is encoded as
– 8-bit immediate (imm8)
– 4-bit rotation (rot)
• 32-bit immediate = imm8 ROR (rot x 2)

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Addressing Modes
• Register Only
• Immediate
• Base
• PC-Relative

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Base Addressing
• Address of operand is:
base register + offset
• Offset can be a:
– 12-bit Immediate
– Register
– Immediate-shifted Register

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Base Addressing Examples

• Immediate offset
Example: LDR R0, [R8, #-11]
(R0 = mem[R8 - 11] )
• Register offset
Example: LDR R1, [R7, R9]
(R1 = mem[R7 + R9] )
• Immediate-shifted register offset
Example: STR R5, [R3, R2, LSL #4]
(R5 = mem[R3 + (R2 << 4)] )

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Addressing Modes
• Register Only
• Immediate
• Base
• PC-Relative

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PC-Relative Addressing
• Used for branches
• Branch instruction format:
– Operands are PC and a signed 24-bit immediate (imm24)
– Changes the PC
– New PC is relative to the old PC
– imm24 indicates the number of words away from PC+8
• PC = (PC+8) + (SignExtended(imm24) x 4)

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The Stored Program

Assembly Code Machine Code
MOV R1, #100 0xE3A01064
MOV R2, #69 0xE3A02045
ADD R3, R1, R2 0xE2813002
STR R3, [R1] 0xE5913000
Stored Program
Address Instructions Program Counter
(PC): keeps track of
current instruction
0000000C E5 9 1 3 0 0 0
00000008 E2 8 1 3 0 0 2
00000004 E3 A 0 2 0 4 5
00000000 E3 A 0 1 0 6 4 PC
Main Memory

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Power of the Stored Program

• 32-bit instructions & data stored in memory
• Sequence of instructions: only difference
between two applications
• To run a new program:
– No rewiring required
– Simply store new program in memory
• Program Execution:
– Processor fetches (reads) instructions from memory
in sequence
– Processor performs the specified operation

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Loading Value MOV vs LDR

• MOV only accepts a 12-bit source.
• Many programs need to load 32-bit literals, such as constants or addresses.
LDR instruction is used to load these numbers from a literal pool in the text
segment.
• LDR Rd, =literal ; loads a 32-bit constant specified by literal
LDR Rd, =label ; loads the address of a variable or pointer specified by label
• In both cases, the value to load is kept in a literal pool, which is a portion of the
text segment containing literals.

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NOP
• NOP is a mnemonic for “no operation” and is pronounced “no op.” It is a
pseudoinstruction that does nothing. The assembler translates it to MOV R0, R0
(0xE1A00000). NOPs are useful to, among other things, achieve some delay
or align instructions.

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Exceptions
Lecture 4.3
Week 4
89
Exceptions
• An exception is like an unscheduled function call that branches to a new
address.
• Exceptions may be caused by hardware or software.
• Hardware Generated Exception: Interrupt

• Software Generated Exception: Trap

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Exception Handling
• Like any other function call, an exception must save the return address, jump to
some address, do its work, clean up after itself, and return to the program where
it left off. Exceptions use a vector table to determine where to jump to the
exception handler and use banked registers to maintain extra copies of key
registers so that they will not corrupt the registers in the active program.

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ARM Execution Modes

An ARM processor can operate in one of several execution modes with different privilege levels. The
different modes allow an exception to take place in an exception handler without corrupting state.
Execution mode determined by bits 4:0 of CPSR
Privilege levels are important so that buggy or malicious user code cannot corrupt other programs or crash or infect
the system.

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Exception Vector Table

• When an exception occurs, the processor branches to an offset in the exception vector table,
depending on the cause of the exception.
• The vector table is normally located starting at address 0x00000000 in memory.
• For example, when an interrupt occurs, the processor branches to address 0x00000018.

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Banked Registers
• Before an exception changes the PC, it must save the return address in the LR
so that the exception handler knows where to return. However, it must take care
not to disturb the value already in the LR, which the program will need later.
Therefore, the processor maintains a bank of registers to use as separate LR
during each of the execution modes.
• Bank of Link Registers
• Bank of Saved Program Status Registers because CPSR of main program will be loaded in SPSR of
• Banked copy of Stack Pointer different addressing modes
• FIQ mode: R8-R12 are banked

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Exception Handling
At the start of Exception Handling…
1. Stores the CPSR into the banked SPSR
2. Sets the execution mode and privilege level based on the type of exception
3. Sets interrupt mask bits in the CPSR so that the exception handler will not be
interrupted
4. Stores the return address into the banked LR
5. Branches to the exception vector table based on the type of exception

95
• The processor then executes the instruction in the exception vector table,
typically a branch to the exception handler.
• The handler usually pushes other registers onto its stack, takes care of the
exception, and pops the registers back off the stack.
• The exception handler returns using the MOVS PC, LR

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Exception Handling
MOVS PC,LR does the following clean up:
1. Copies the banked SPSR to the CPSR to restore the status register
2. Copies the banked LR (possibly adjusted for certain exceptions) to the PC to
return to the program where the exception occurred
3. Restores the execution mode and privilege level

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Exception-Related Instruction
• Supervisor call (SVC): To transition between levels in a controlled way, the
program places arguments in registers and issues a SVC instruction, which
generates an exception and raises the privilege level.
• The OS and other code operating at PL1 can access the banked registers for
the various execution modes using the MRS (move to register from special
register) and MSR (move to special register from register) instructions. (At Boot,
initializing the stack pointers

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Start-up of Computer
• On start-up, the processor jumps to the reset vector
• Execute boot loader code in supervisor mode. The boot loader typically
configures:
• Configures the memory system
• Initializes the stack pointer
• Reads the OS from disk;
• Begins a much longer boot process in the Operating System.
• The OS eventually will load a program, change to unprivileged user mode, and
Jump to the start of the program.

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Syllabus for Chapter 6

• 6.2 – Assembly Language
• 6.3 – Programming
• 6.4 – Machine Language

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Up Next
How to implement the ARM Instruction Set
Architecture in Hardware (Chapter 7)
Microarchitecture

101
51

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DRAFT 6/20/2023

EEE 415 - Weekly Lecture Plan

EEE 415 - Weekly Lecture Plan

EEE 415 - Microprocessors and Embedded Systems

EEE Machine Language

415 Lecture 4.1

Dr. Sajid Muhaimin Choudhury, Assistant Professor

How to Encode Instructions?

– Computer only understands 1s and 0s. Instructions with these.

Dr. Sajid Muhaimin Choudhury 4

How does a 32bit number represent an instruction?

Dr. Sajid Muhaimin Choudhury 5

Dr. Sajid Muhaimin Choudhury 6

• Different Representation dependent on Architecture 32-bit instructions

Dr. Sajid Muhaimin Choudhury 7

Machine Language Reference

• Microcontrollers: 32-bit T2 or 16-bit thumb architecture

• Lab: ARM v8A 32-bit instructions (Last Year)

Dr. Sajid Muhaimin Choudhury 8

Different ARM Encoding Versions - ADD

Dr. Sajid Muhaimin Choudhury 9

Machine Language Reference

• Microcontrollers: 32-bit T2 or 16-bit thumb architecture

• Lab: ARM v8A 32-bit instructions

Dr. Sajid Muhaimin Choudhury 10

Machine Language in EEE 415

• We limit our discussion to ARMv7A instruction set. Concepts are similar

Dr. Sajid Muhaimin Choudhury 12

Data-processing Instruction Format

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Data-processing Control Fields

Dr. Sajid Muhaimin Choudhury 14

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Data-processing Src2 Variations

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Data-processing Src2 Variations

Dr. Sajid Muhaimin Choudhury 18

Dr. Sajid Muhaimin Choudhury 19

Dr. Sajid Muhaimin Choudhury 20

DP Instruction with Immediate Src2

Machine Code: 0xE281002A

DP Instruction with Immediate Src2

DP Instruction with Register Src2

Dr. Sajid Muhaimin Choudhury 23

DP Instruction with Register Src2

First, consider unshifted versions of Rm (shamt5=0, sh=0)

Dr. Sajid Muhaimin Choudhury 24

DP Instruction with Register Src2

DP Instruction with Register Src2

Dr. Sajid Muhaimin Choudhury 26

DP Instruction with Register Src2

1110 00 0 1100 0 0101 1001 00010 01 0 0011

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DP with Register-shifted Reg. Src2

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DP with Register-shifted Reg. Src2

1110 00 0 0001 0 1001 1000 1100 0 11 1 1010

Dr. Sajid Muhaimin Choudhury 29

Shift Instructions Encoding

Dr. Sajid Muhaimin Choudhury 30

Shift Instructions: Immediate shamt

1110 00 0 1101 0 0000 0001 10111 11 0 0010

Dr. Sajid Muhaimin Choudhury 31

Shift Instructions: Register shamt