DATA SHEET

MOS FIELD EFFECT TRANSISTOR

2SK4212
SWITCHING
N-CHANNEL POWER MOS FET

DESCRIPTION
The 2SK4212 is N-channel MOS FET device that features a low on-state resistance and excellent switching characteristics,
and designed for low voltage high current applications such as DC/DC converter with synchronous rectifier.

FEATURES
• Low on-state resistance
RDS(on)1 = 7.8 mΩ MAX. (VGS = 10 V, ID = 30 A)
RDS(on)2 = 14 mΩ MAX. (VGS = 4.5 V, ID = 20 A)
• Low total gate charge
QG = 27 nC TYP. (VDD = 15 V, VGS = 10 V, ID = 30 A)
• 4.5 V drive available
• Avalanche capability ratings

ORDERING INFORMATION
PART NUMBER LEAD PLATING PACKING PACKAGE
Note
2SK4212-ZK-E1-AY
Pure Sn (Tin) Tape 2500 p/reel TO-252 (MP-3ZK) typ. 0.27 g
Note
2SK4212-ZK-E2-AY

Note Pb-free (This product does not contain Pb in external electrode).

ABSOLUTE MAXIMUM RATINGS (TA = 25°C) (TO-252)

Drain to Source Voltage (VGS = 0 V) VDSS 25 V
Gate to Source Voltage (VDS = 0 V) VGSS ±20 V
Drain Current (DC) (TC = 25°C) ID(DC) ±48 A
Note1
Drain Current (pulse) ID(pulse) ±144 A
Total Power Dissipation (TC = 25°C) PT1 35 W
Total Power Dissipation (TA = 25°C) PT2 1.0 W
Channel Temperature Tch 150 °C
Storage Temperature Tstg −55 to +150 °C
Note2
Single Avalanche Current IAS 17 A
Note2
Single Avalanche Energy EAS 28.9 mJ

Notes 1. PW ≤ 10 μs, Duty Cycle ≤ 1%

2. Starting Tch = 25°C, VDD = 12.5 V, RG = 25 Ω, VGS = 20 → 0 V, L = 0.1 mH

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.

Document No. D19564EJ1V0DS00 (1st edition) 2008

Date Published December 2008 NS
Printed in Japan
 2SK4212

ELECTRICAL CHARACTERISTICS (TA = 25°C)

CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Zero Gate Voltage Drain Current IDSS VDS = 25 V, VGS = 0 V 10 μA

Gate Leakage Current IGSS VGS = ±16 V, VDS = 0 V ±100 nA

Gate to Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 1.5 3.0 V
Note
Forward Transfer Admittance | yfs | VDS = 5 V, ID = 12 A 10 22 S
Note
Drain to Source On-state Resistance RDS(on)1 VGS = 10 V, ID = 30 A 5.5 7.8 mΩ

RDS(on)2 VGS = 4.5 V, ID = 20 A 8.5 14 mΩ

Input Capacitance Ciss VDS = 15 V, 1200 pF

Output Capacitance Coss VGS = 0 V, 220 pF

Reverse Transfer Capacitance Crss f = 1 MHz 140 pF

Turn-on Delay Time td(on) VDD = 15 V, ID = 30 A, 16 ns

Rise Time tr VGS = 10 V, 14 ns

Turn-off Delay Time td(off) RG = 3 Ω 45 ns

Fall Time tf 11 ns

Total Gate Charge QG VDD = 15 V, 27 nC

Gate to Source Charge QGS VGS = 10 V, 4 nC

Gate to Drain Charge QGD ID = 30 A 7 nC

Note
Body Diode Forward Voltage VF(S-D) IF = 30 A, VGS = 0 V 0.88 1.5 V

Reverse Recovery Time trr IF = 30 A, VGS = 0 V, 26 ns

Reverse Recovery Charge Qrr di/dt = 100 A/μs 14 nC

Note Pulsed

TEST CIRCUIT 1 AVALANCHE CAPABILITY TEST CIRCUIT 2 SWITCHING TIME

D.U.T.
D.U.T.
RG = 25 Ω L
RL VGS
PG. VGS 90%
50 Ω VDD 10% VGS
Wave Form
RG 0
VGS = 20 → 0 V PG. VDD
VDS
BVDSS 90% 90%
IAS VGS VDS
VDS 0 10% 10%
ID VDS 0
Wave Form
VDD τ
td(on) tr td(off) tf

τ = 1 μs ton toff
Starting Tch Duty Cycle ≤ 1%

TEST CIRCUIT 3 GATE CHARGE

D.U.T.
IG = 2 mA RL

PG. 50 Ω VDD

2 Data Sheet D19564EJ1V0DS

 2SK4212

TYPICAL CHARACTERISTICS (TA = 25°C)

DERATING FACTOR OF FORWARD BIAS FORWARD BIAS SAFE OPERATING AREA
SAFE OPERATING AREA
120 1000
dT - Percentage of Rated Power - %

100 ID(pulse)
PW
100

ID - Drain Current - A
ID(DC) =
1i 0
80 0
μs
DC
d
60 10 it e
m )
Li V

Po
) 0

w
on 1i

er
S( =
D

D
R S

is
40
G
(V

si
pa
1 ms

t io
1

n
Li
m
10 ms

it e
20

d
TC = 25°C
Single Pulse
0 0.1
0 25 50 75 100 125 150 175 0.01 0.1 1 10 100

TC - Case Temperature - °C VDS - Drain to Source Voltage - V

TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH

1000
rth(t) - Transient Thermal Resistance - °C/W

Rth(ch-A) = 125°C/W
100

10

Rth(ch-C) = 3.57°C/W
1

0.1

Single Pulse
0.01
100 μ 1m 10 m 100 m 1 10 100 1000
PW - Pulse Width - s

FORWARD TRANSFER CHARACTERISTICS GATE TO SOURCE THRESHOLD VOLTAGE vs.

CHANNEL TEMPERATURE
VGS(th) - Gate to Source Threshold Voltage - V

30 4

3
ID - Drain Current - A

20
TA = 125°C
75°C
2
25°C
−55°C
10
1
VDS = 10 V VDS = VGS
Pulsed ID = 250 μA
0 0
0 1 2 3 4 5 -75 -25 25 75 125 175
VGS - Gate to Source Voltage - V Tch - Channel Temperature - °C

Data Sheet D19564EJ1V0DS 3

 2SK4212

FORWARD TRANSFER ADMITTANCE vs. DRAIN TO SOURCE ON-STATE RESISTANCE vs.

DRAIN CURRENT DRAIN CURRENT

RDS(on) - Drain to Source On-state Resistance - mΩ

100 20
| yfs | - Forward Transfer Admittance - S

TA = 150°C
15
10

75°C 10 VGS = 4.5 V

25°C
1 −55°C
5 10 V
VDS = 5 V
Pulsed Pulsed
0.1 0
0.1 1 10 100 0.1 1 10 100 1000

ID - Drain Current - A ID - Drain Current - A

DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE CHANNEL TEMPERATURE
RDS(on) - Drain to Source On-state Resistance - mΩ

RDS(on) - Drain to Source On-state Resistance - mΩ

20 15
ID = 30 A
Pulsed
15 VGS = 4.5 V, ID = 20 A
10

10

10 V, 30 A
5
5

Pulsed
0 0
0 5 10 15 20 -75 -25 25 75 125 175
VGS - Gate to Source Voltage - V Tch - Channel Temperature - °C

CAPACITANCE vs. DRAIN TOSOURCE VOLTAGE DYNAMIC INPUT/OUTPUT CHARACTERISTICS

10000 10
VGS - Gate to Source Voltage - V
Ciss, Coss, Crss - Capacitance - pF

VDD = 5 V
8
15 V
1000 Ciss 20 V
6

Coss 4
100 Crss

2
VGS = 0 V
f = 1 MHz ID = 30 A
10 0
0.1 1 10 100 0 5 10 15 20 25 30

VDS - Drain to Source Voltage - V QG - Gate Charge - nC

4 Data Sheet D19564EJ1V0DS

 2SK4212

SOURCE TO DRAIN DIODE FORWARD VOLTAGE

1000
IF - Diode Forward Current - A

100 VGS = 10 V

4.5 V 0V

10

Pulsed
0.1
0 0.5 1 1.5

VF(S-D) - Source to Drain Voltage - V

Data Sheet D19564EJ1V0DS 5

 2SK4212

PACKAGE DRAWINGS (Unit: mm)

TO-252 (MP-3ZK)

6.5±0.2 2.3±0.1
5.1 TYP. 1.0 TYP. 0.5±0.1
4.3 MIN.
No Plating
4
10.4 MAX. (9.8 TYP.)
4.0 MIN.

6.1±0.2

0.51 MIN.
1 2 3
0.8

No Plating

1.14 MAX. 0.76±0.12 0 to 0.25

2.3 2.3 0.5±0.1

1.0
1. Gate
2. Drain
3. Source
4. Fin (Drain)

EQUIVALENT CIRCUIT

Drain

Body
Gate Diode

Source

Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade the
device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate
it once, when it has occurred.

6 Data Sheet D19564EJ1V0DS

 2SK4212

• The information in this document is current as of December, 2008. The information is subject to
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M8E 02. 11-1