11.

The PLL
11.0. Introduction

The PLL is a circuit originally built with analog components and as such was treated in a course
"Advanced Analog Circuits". Today this very interesting circuit is mostly built with digital compo-
nents and that's why it is shifted from the course Analog Circuits to Digital Circuits. But it is more
convenient to discuss its operation as an analog function. This will be done in a first part. The se-
cond part will discuss the several phase comparators and the third part will cover the digital imple-
mentation. Finally some applications will be discussed.

11.1 Principle

The 3 building blocks of the PLL are :

* the phase comparator: this function compares two signals U1 and U2 and generates an output
signal that is proportional to the difference in phase of the inputs. Also when both inputs do not
have exactly the same frequency (and now the concept of phase difference is somewhat strange) the
output will generate a value proportional to the difference in frequency. The output can be either
'analog' or 'digital'. The digital value will be a square wave with a varying duty cycle (= ratio in
time between '1' and '0' )

* the voltage controlled oscillator : the oscillator generates a signal (either sinusoidal or square
wave) with a frequency f0 when no input signal is present. When an input voltage Uf is applied the
oscillator will generate a frequency f2 that is different from f0 :

f2 = f0 + a . Uf

where the parameter a is constant (no function of Uf) for a given VCO and Uf can be positive or ne-
geative. Remarks that 'no input voltage' is not equal to an input of zero volts. No voltage means no
deviation from a fixed reference value. This reference value will generate the iddle output
frequency f0 when 'no input' is present. A typical reference value could be half the supply voltage.
The control voltage Uf is relative to this reference.

Chap. 11 PLL p. 1 / 14
* a low pass filter : this filter operates on the output signal of the phase comparator. All higher fre-
quencies in the signal will be rejected. Only the DC and low frequency values will be transferred to
the output. Mostly first order filters are used.

Operation :

Suppose that, just by accident, the input signal U1 has exactly the same frequency and phase as the
free running VCO output U2. Free running means that there in no input ( Uf is zero). Because both
signals U1 and U2 are equal the output of the phase comparator will be zero. This zero signal will
also produce a zero signal at the output of the filter. And this output is used to control the VCO.
But there is a zero control and so the VCO will oscillate at f 0. This is a stable situation : no phase
differences between U1 and U2 will result in a non-driven VCO with output f 0.

Suppose now that the input frequency of U1 slightly increases. This will produce an output at the
phase comparator (U1 is not equal to U2), this output will be filtered and the resulting signal will be
used as a control Uf for the VCO. As a result, the output frequency U2 of the VCO will increase.
Due to the operation of the loop the VCO will produce a frequency exactly the same as the input
U1.
Indeed, if the VCO would generate a frequency higher than U1 than the comparator and filter
would produce a negative Uf signal and this would slow down the VCO. As long as the frequency
of U2 is lower than U1 the loop will produce a positive Uf signal. As a result, the loop will try to
make both frequencies the same. But to produce an VCO output different from f0 will require a
control voltage Uf and this voltage is comming from the filter and thus comming from the phase
comparator. As a result, the loop will produce a stable VCO frequency but its phase will be
different from the input signal. This phase difference will produce the energy to change the
frequency of the VCO.

Hence the name PLL : phase locked loop.

The loop will lock the VCO frequency on the input frequency and the phase difference is the signal
which will control the loop.

The operation of the PLL is quite simple and correctly to explain once the system is effectively
locked (f2=f1). The way how and why f2 is changing to f1 is not so easy to explain and requires a
lot of mathematics. Therefore only the concepts are discussed here.

Once the system is locked, the input signal f1 can change : the feedback loop will control the VCO
so that all variations in f1 will be followed by f2. Of course the bandwidth of the filter should be
larger than the bandwidth of the input changes on f1 .

Chap. 11 PLL p. 2 / 14
The lock range (or hold-in range) is the frequency range of the VCO where the system can follow
all variations on the input signal. The capture range (or lock-in range) is the frequency range
where a non-locked system has to ability to lock on an input signal. The lock range is always larger
than the capture range.

11.2. The Phase detector PD

This building block is very critical for a good operation of the PLL. During its long existance 4
different types of PD's are commonly used. The naming convention is widely used in the PLL
world.

Type I
ˇˇˇˇˇˇ
The comparison is done by a four quadrant analog multiplier. Suppose both input signals are
sinusoidal with equal frequencies but different phase. A mathematical representation could be :

U1(t) = UU1 sin(ω1t + φ1)

U2(t) = UU2 cos(ω2t + φ2)

The output Ud of the phase comparator for the case ω1 = ω2 :

Ud = k (UU1.UU2)/2 [ sin(φ1-φ2) + sin(2 ω1 t + φ1 + φ2 )]

with k a constant parameter of the multiplier.

The voltage Ud contains a DC and a AC component. The AC component is at double frequency

(because ω1 = ω2) and is quite easily filtered out by the low pass filter. The control of the VCO is
now :
Uf = k'.UU1.UU2.sin(φ1-φ2) ≈ k'.UU1.UU2.(φ1-φ2)

Chap. 11 PLL p. 3 / 14
For small phase differences the term sin(φ1-φ2) equals (φ1-φ2). A drawback however is now that the
voltage is also function of the amplitudes of the input signals. An automatic gain control (AGC)
module on the inputs is required.

What if the 2 inputs have different frequencies? Now the voltage Ud contains a term proportional to
sin(ω1 + ω2) and a term proportional to sin(ω1 - ω2). The sum term will be filtered while the min
term is suitable to control the VCO in such a way that finally locking occurs.

The big advantage of PD Type I is its good noise rejection. All kind of noises and disturbances on
the input can be considered as a broadband signal with all kind of frequencies. Because all these
frequencies will not be correlated with the output of the VCO, the output of the comparator wil be
zero (all product terms input * VCO will be zero). An usefull input frequency can be completely
'hidden' in the noise and yet the PLL with PD Type I will be able to lock on it. Only input frequen-
cies in the range of the VCO will produce a non-zero output on the comparator Type I.

Half of all data- and telecommunications principles are based on this signal recovery.

So far both input signals are considered sinusoidal. The PLL will continu to operate if the VCO
produces a square wave. This square wave contains a base frequency f2 and all odd harmonic fre-
quencies. These harmonics after multiplication with f1 can never yield a DC term under condition
of a pure sinusoidal input U1 .
Of course, if also the input is non-sinusoidal the Type I will lose all its benefits of noise rejection.

The good properties of PD Type I require a lineair operation of the multiplier (---> no non-lineari-
ties which will generates extra frequencies). The PLL will continue to operate even in the
nonlineair operation mode of PD Type I : the PD will react on the zero crossings of the overdriven
inputs and the output will be a square wave with varying duty cycle. After filtering this signal is
capable of controlling the VCO.
Of course, the noise rejection properties are gone.

The PD Type I can operate on both analog and digital inputs. The other types do only operate on
digital signals. A digital signal is a signal with only 2 values (0 and 1). The input signal U1 and the
output U2 of the VCO are now square waves.

Type II
ˇˇˇˇˇˇˇ
This PD uses the EXOR gate. The average output signal Ud of the PD is proportional with the duty
cycle of the output of the EXOR. If U1 and U2 are exactly in phase the output will always be zero
(duty cycle 0 %). If U1 and U2 are completely in anti-phase the output will be always one (duty
cycle 100%).

If both inputs have a phase shift of 90 degrees the output will be a symmetrical square wave on
double frequency. The average value of this 50% duty cycle wave will be taken as the reference
value. This reference value will produce the neutral output frequency of the VCO. A duty cycle
higher than 50 % will result in a positive Uf and will increase f2 , a duty cycle lower than 50% will

Chap. 11 PLL p. 4 / 14
produce a negative Uf and decrease f2. A duty cycle of 50% gives a zero value for Uf and results in
f2= f0 .
The input range of the EXOR, and this is related to the lock range of the PLL, is between -90 de-
grees and + 90 degrees with respect to a reference of a difference of 90 degrees. In other words sig-
nals in the range of 0 to 180 degrees will be locked. If after locking the phase difference increases
to more than 180 degrees the system will lose its locking.
Remark that the neutral situation of a Type II PLL is for a phase difference of 90 degrees. Only a
difference of 90 degrees will result in a no driving force for the VCO and this is the neutral situa-
tion.

Remark that the input range of the EXOR is also related to the symmetry of the inputs. If the inputs
are non-symmetrical (non 50% duty cycle) the range of the PLL will decrease.
Indeed, different phase relations (but with different duty cycles) can result in identical average out-
put voltages.
The figures below illustrate the operation:

Chap. 11 PLL p. 5 / 14
 Type III
ˇˇˇˇˇˇˇˇˇ
The edge triggered JK master slave Flip Flop is used a phase comparator. The output Q will go high
on the falling edge of U1, the output Q will go low on the falling edge of U2.
The duty cycle of the inputs is irrelevant (only edge triggered)

The behaviour of this PD when both frequencies f1 and f2 are very different is well predictable.
This is illustrated in the figure. The PD will generate a clean output signal to the filter and the
VCO. Its behaviour is less favorable when both frequencies are roughly the same. This is also
illustrated in the figure. The PD generates a signal with an increasing (decreasing) average value to
control the VCO. But as the frequency f2 is reaching f1 a small overshoot in f2 will result in a
sudden large change in Ud and the locking action can restart.
A stable behaviour is possible when f2 equals f1 but it seems difficult to reach this condition.

Chap. 11 PLL p. 6 / 14
Chap. 11 PLL p. 7 / 14
 Type IV
ˇˇˇˇˇˇˇ
This type is based on type III but extra logic is added to improve its behaviour. Now the PD
has 2 outputs which are non-complementary. The outputs UP and DOWN do control an integrator
(acting as a low pass filter) but never at the same time. The presence of UP (DOWN) will generate
an increasing (decreasing) voltage for the VCO. The lack of UP or DOWN will result in a non-
changing control voltage of the VCO.

The effective realisation is manufacturer dependant (see data books) but its behaviour is as follows:

1. if the rising edge of U1 occurs when U2 is low the next falling edge of U1 will activate UP and
the next falling edge of U2 will deactivate UP.
2. if the rising edge of U1 occurs when U1 is high the next falling edge of U2 will activate DOWN
and the next falling edge on U1 will deactivate DOWN.

See the following figures and note that an active UP or DOWN means active low.

Chap. 11 PLL p. 8 / 14
 11.3 The Digital PLL

The classical analog PLL can operate with either analog or digital signals. The name 'digital' PLL
indicates that the building blocks are now completely digital: the comparator, the low pass filter and
the VCO.
The benefits of a pure digital desing are obvious :
the accury is not influenced by temperature, aging, variations in power supply, ...
the bandwidth and the centre frequency f0 is digitally programmable.
Digital PLL's do exist in all kind of flavours and colours. As an example the PLL 74LS297 of the
TTL series is taken.

The phase detector can be of Type II, III or IV. The output of the phase detector is a square wave
with variable duty cycle and this wave is controlling an up/down counter. A '1' on the input will
count down. This counter has a programmable modulo K. The centre frequency f0 of the PLL is
represented by the symbol fc. (what’s in a name…). The clock of the counter equals M.f0 and f0
equals the centre frequency. The parameter M can be given any value.

Chap. 11 PLL p. 9 / 14
The modulo K means that the counter will increment from count 0 to count K thereby generating a
carry CA and than overflows back to count 0 and the cycle repeat itself. Also a count down from K
to 0 , thereby generating a borrow B0 and then underflows back to K to repeat.
A larger value for K will generate less CA or BO pulses for the same input signal up/down. If the
duty cycle of the output of the phase detector equals roughly 50 % then the counter K will generate
an equal number of CA and BO pulses. A duty cycle of more than 50% will generate more BO pul-
ses, less than 50% more CA pulses. A higher clock frequency (M.f0) will also produce more CA
and BO pulses.
This counter K act as a low-pass filter.

The pulses BO or CA will control an increment/decrement counter acting as a VCO. This counter,
driven by a clock of 2.N.f0 will generate an idle frequency of N.f0 (N is a scale factor). Basically
this counter is a divide by 2 counter. An increment (decrement) input will add (substract) one addi-
tional clock pulse on (from) the signal N.f0.
The frequency is defined as the number of pulses per second and as such this system acts as a VCO.

The output of the VCO is illustrated on the figure :

The output of the VCO will be devided once again by a N-divider before being used by the phase
detector. This N divider will smoothen the irregular pulse distribution of the VCO output.
The improvement will be a factor 2exp(N).

Chap. 11 PLL p. 10 / 14
 11.4 : PLL Applications.

In principle, every application can be built with either an analog or a digital PLL.

1. The PLL as electronic flywheel

2. FM decoder

The input U1 is a FM modulated signal :

U1 = UU1.sin.[ Asin(wt) . t ]

If the low pass filter has a higher bandwidth than the modulating signal Asin(wt) the VCO will be
adjusted non-stop to force U2 to equal U1. The control voltage for the VCO is of course Asin(wt)
and this will be the demodulated usefull output.

Chap. 11 PLL p. 11 / 14
 3. Decoder for phase shift keying PSK

The input Upsk has a phase shift of 180 degrees for every 0 / 1 or every 1 / 0 transition in the data
stream Uz. The phase comparator will generate a large signal to force the VCO to keep tracking.
This filtered output of Uf is the demodulated signal.

Chap. 11 PLL p. 12 / 14
 4. Clock recovery from a RZ signal

Take a bitstream made such that every logical '1 will last half a clock pulse while the logical '0' has
no signal (this is called a return to zero code RZ). This bitstream is generated at the transmitter side
with a clocksignal but the clock as such is not available at the receiver side. The clock recovery is
quite easy by using a PLL. Once the clock is recoverd one can demodulate the data.

Basically this kind of signal is read from a digital magnetic recorder (floppy, hard disk, tape...)
Restrictions are that the number of consecutive zeros should be restricted otherwise the locking will
end. Also some time is required (synchronisation) to allow the PLL to start tracking. A typical data-
stream will add a number of dummy ones at the start.

5. Clock recovery from a NRZ code

This situation is similar to the previousone. Here the coding is such that a '1' or a '0' do last a full
clock period. The clock is recovered with the following circuit. The first building block is a diffe-
rentiator, the second a rectifier and the third is the PLL.

Chap. 11 PLL p. 13 / 14
6. Frequency Synthesis

This very important circuit allows to generate any frequency, originating from a reference oscilla-
tor. This reference could be quartz controlled such that all generated frequencies will have the same
favorable properties as the reference.
The figure is self explaining.

Fref / M = Fosc / (P * N)

Fosc = Fref * P * N / M P, N, M : any integer value

7. Motor speed control

The motor itself is used as a VCO !

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