Teaching Plan

FAKULTI TEKNOLOGI MAKLUMAT DAN KOMUNIKASI

UNIVERSITI TEKNIKAL MALAYSIA MELAKA

COMPUTER ORGANIZATION AND ARCHITECTURE

BITS 1123 SEMESTER I SESI 2022/2023

BITS 1123 COMPUTER ORGANIZATION AND ARCHITECTURE [3, 2, 2]

TYPE OF COURSE: P
EDITION: 1
UPDATED: 21-09-2021

1.0 LEARNING OUTCOMES

Upon completion this course, students will be able to:
CLO1 Demonstrate the concept of functional computer components and the detail
interactions in computer systems (C3).
CLO2 Explain the principles and techniques used in implementing a processor.
(CS2, A3).
CLO3 Assemble basic computer components and its architectural attributes,
including instruction set and technique for addressing memory (P3, CTPS3).

2.0 SYNOPSIS
This subject provides a detail of computer system’s functional components,
characteristics, performance and interactions including system bus, different
types of memory and Input/Output and CPU, as well as practical
implementations of the components. Besides that, the architectural issues such
as instruction set design and data types are covered. This subject includes
digital circuit design and its application in microprocessor architecture.

3.0 PRE-REQUISITE
None

4.0 PRACTICAL
Students will be introduced to number representation and basic digital logic
circuit. The knowledge will be used when students learned the programming
technique of assembly language. In addition, students will be introduced to
computer system’s component and assembling them.

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5.0 REFERENCES

[1] David A. Patterson and John L. Hennessy (2013). Computer Organization

and Design: The Hardware/Software Interface, 5th Edition. Morgan Kauffman.

[2] Aslinda, Fahmi, Nurul Azma, Zakiah and Zurina (2018). Lecture Slides:
Computer Organization & Arcitecture. Second Edition

[3] Syarulnaziah, Zakiah, Marliza., Aslinda (2018). Lab Module: Computer

Organization and Architecture With MIPS Programming.

[4] William Stallings, (2016). Computer Organization and Architecture:

designing for performance 10th Edition. Pearson.

[5] Andrew S. Tanenbaum, (2013). Structured Computer Organization 6th

Edition. Prentice Hall.

[6] Irv. Englander (2014).The Architecture of Computer Hardware and System

Software: An Information Technology Approach, 5th Edition.John Wiley & Sons.

[7] Linda Null and Julia Lobur (2014). The Essentials of Computer Organization
and Architecture, 4th Edition. Jones & Bartletts Pub.

6.0 COURSE IMPLEMENTATION

i. Lecture
 2 hours per week for 14 weeks (Total = 28 hours)

ii. Laboratory Activities

 2 hours per week for 14 weeks (Total = 28 hours)

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7.0 COURSE EVALUATION

Scheme,
Assessment Method CLO 1 CLO 2 CLO 3 Rubric/
guideline
Lab Assessment LA1 (10%)
(10%)
Quiz (10%) Q1 (10%)
Group Project PRJ1 Project
(15%) (15%) Rubric.docx
Lab Test LBT1
(15%) (15%)
Mid Term
MT1 (20%)
(20%)
Final Test
FT1 (30%)
(30%)
Total 60% 25% 15%

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8.0 STUDENT LEARNING TIME
GUIDED LEARNING INDEPENDANT LEARNING ASSESSMENT TIME
TIME
WEEK CLO L T P O L T P O F T A O F T A O SLT

W1 1/3 2 2 2 0 1 0 0 0 0 7

W2 2/3 2 2 2 0 1 0 0 0 0 7

W3 2/3 2 2 2 0 1 0 0 0 0 7

W4 2/3 2 2 2 0 1 0 0 0 0 7

W5 2/3 2 2 2 0 1 0 2 0 0 0.5 7

W6 2/3 2 2 2 0 1 0 0 0 0 7

W7 2/3 2 2 2 0 1 0 0 0 0 7

W8 2/3 2 2 2 0 1 0 0 0 0 7

W9 2/3 2 2 2 0 1 0 6 0 0 1.5 14.5

W10 1 2 2 2 0 1 0 0 0 0 7

W11 1 2 2 2 0 1 0 0 0 0 7

W12 1 2 2 2 0 1 0 0 0 0 7

W13 1 2 2 2 0 1 0 0 0 0 7

W14 1 2 2 2 0 1 0 4 0 0 1 12

>W14 8 0 0 0 2 10

OVERAL 28 0 28 0 28 0 14 0 8 12 0 0 2 3 0 0 123
L
SLT CREDIT EQUIVALENT 3.08

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9.0 DETAILED SYLLABUS AND TEACHING PLAN

Week Contents References Delivery

Methods
1 Lecture 1: Introduction to Computer [1]Chapter 1 Lecture

Lab 1: Assembling PC [3] Lab 1 Lab

2 Lecture 2: Arithmetic for Computers (part 1) [1] Chapter 3 Lecture
Number System Base, Number conversion
(decimal, binary and hexadecimal)

Lab 2: Number System [3] Lab 2 Lab

3 Lecture 3: Arithmetic for Computers (part 2) [1] Chapter 3 Lecture

Binary number operation (add, sub, multiply and
divide), Hexadecimal number operation (add and
sub).

Lab 3: Number Operation [3] Lab 3 Lab

Negative number representation and conversion

4 Lecture 4: The Basics of Logic Design (part 1) [1] Appendix C Lecture

Basic logic gates, combinational circuit, Boolean
equation forms, Laws of Boolean Algebra

Lab 4: Digital Logic [3] Lab 4 Lab

Boolean Algebra

5 Lecture 5: The Basics of Logic Design (part 2) Lecture

Karnaugh Map, Simplification of combinational [3] Lab 4
circuit
[3] Lab 5, 6
Lab 5: Introduction to Multimedia Logic Lab
Introduction of multimedia logic; Introduction to
adder, multiplexer, decoder and SR flip flop.
6 Lecture 6: Language of the Computers [1] Chapter 2 Lecture
Instruction Sets, Type of operands (register,
memory, immediate)

Lab 6: Introduction to Microprocessor [3] Lab 7 Lab

Introduction to assembly language and simulator
7 Lecture 7: Language of the Computers [1] Chapter 2 Lecture
Mips Addressing modes (Register, Immediate, PC-
relative, Base, Pseudo-direct); Addressing formats
(R, I and J-Type)

Lab 7: Introduction to Microprocessor [3] Lab 8

Instruction format and addressing mode
Lab
8 Lecture 8: The Processor [1] Chapter 4 Lecture
CPU overview; Control unit; Intro to Datapath

Lab 8: Assembly Language 1 [3] Lab 9 Lab

Load and store operations
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 9 Lecture 9: The Processor [1] Chapter 4 Lecturer
Building Datapath (R and I-type)

Lab 9: Assembly Language 2 [3] Lab 10 Lab

Arithmetic operations (add, sub, mult)
10 Lecture 10: Exploiting Memory Hierarchy [4] Chapter 5 & 6 Lecture
Memory type; Principle of locality; Intro to cache
mapping technique (direct, associative, set-
associative); cache mapping example (direct
mapping)

Lab 10: Assembly Language 3 [3] Lab 11 Lab

Logical operation (sll, ori, and)
11 Lecture 11: Exploiting Memory Hierarchy [4] Chapter 5 & 6 Lecture
RAM, Memory Module, SRAM, DRAM, Introduction
to ROM

Lab 11: Assembly Language 4 [3] Lab 11 Lab

Translating HLL code to assembly language
(Syscall and if-else statement)
12 Lecture 12: Exploiting Memory Hierarchy [4] Chapter 5 & 6 Lecture
Magnetic disc; Magnetic disc access, RAID

Lab 12: Assembly Language 5 [3] Lab 11 Lab

Translating HLL code to assembly language (loop
statement)
13 Lecture 13: Input/Output Architecture [4] Chapter 7 Lecture

Lab 13: Assembly Language 6

Translating HLL code to assembly language (part
1) [3] Lab 11 Lab
14 Lecture 14: Input/Output Architecture [4] Chapter 7 Lecture

Lab 14: Assembly Language 6

Translating HLL code to assembly language (part [3] Lab 11 Lab
2)
15 Revision Week

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10.0 MATRIX OF LEARNING OUTCOMES
SUBJECT vs PROGRAM OUTCOME (PO) LEARNING OUTCOME (LO)
PROGRAM OUTCOME (PO) Demonstrate the concept of functional computer
Subjec components and the detail interactions in computer
CLO1
t PO PO PO PO PO PO PO PO systems (C3).
1 2 3 4 PO5 6 7 8 9
BITS
1123 X X X Explain the principles and techniques used in
CLO2
implementing a processor. (CS2,A3).

LEARNING OUTCOME (LO) vs PROGRAM OUTCOME (PO) Assemble basic computer components and its
architectural attributes, including instruction set and
CLO3
technique for addressing memory (P3, CTPS3)
CLO PROGRAM OUTCOME (PO)
PO PO PO PO
1 2 3 4 PO5 PO6 PO7 PO8 PO9
CLO1 X
CLO2 X
CLO3 X

SUBJECT vs SOFT SKILLS

SOFT SKILLS
Subject entrepreneurshi ethics&moral leadership
communication skill critical thinking & problem solving team work lifelong learning
p skills professionalism skills
L
CS CS CS CS CS CTPS CTPS CTPS CTPS TS TS TS LL L ES ES ES EM EM EM LS LS S
1 2 3 4 5 CTPS1 2 3 4 5 1 2 3 1 LL2 L3 1 2 3 1 2 3 1 2 3
BITS
1123 X X

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 LEARNING OUTCOME (LO) vs SOFT SKILLS

SOFT SKILLS
LO entrepreneurship ethics & moral leadership
communication skill critical thinking & problem solving team work lifelong learning
skills professionalism skills
CS1 CS2 CS3 CS4 CS5 L L
CTPS CTPS CTPS CTPS CTPS TS TS TS LL LL LL ES ES ES EM EM EM S S LS
1 2 3 4 5 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3
CLO1
CLO2 X
CLO3 X

SUBJECT vs TAXONOMY
Taxonomy
Subject
Affective Cognitive Psychomotor
A1 A2 A3 A4 A5 C1 C2 C3 C4 C5 C6 P1 P2 P3 P4 P5 P6 P7
BITS
1123 X X X X X X X X X

LEARNING OUTCOME (LO) vs TAXONOMY

Taxonomy
LO Affective Cognitive Psychomotor
A1 A2 A3 A4 A5 C1 C2 C3 C4 C5 C6 P1 P2 P3 P4 P5 P6 P7
CLO1 X X X
CLO2 X X X
CLO3 X X X

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 TEACHING PLAN APPROVAL

Prepared by; Approved by;

…………………………. ………………………………..
Nama : ZAKIAH AYOP Dean/Deputy Dean(Academic)/
HOD
Stamp : Stamp :

Date : _________________ Date : __________________

TEACHING PLAN IMPLEMENTATION

(MID SEMESTER BREAK)

Comment :

Checked by ;

………………………………..
Dean/Deputy Dean (Academic)/HOD
Stamp : Date: _______________

TEACHING PLAN IMPLEMENTATION

(WEEK 16)

Comment :

Checked by ;

………………………………..
Dean/Deputy Dean (Academic)/HOD
Stamp : Date: _______________

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