Rule Value Description Notes Comments

Technology Definitions and Considerations

All gates must be vertical (gate direction strictly vertical) - all directions in this design rule manual should define HORIZONTAL or VERTICAL in relation to gate (HORIZONTAL = Perpendicular to gate, VERTICAL = gate direction)
To be independent of gate-first or gate-last strategy, layers are kept in the same order as presented in older process nodes and may not correlate directly with industry standards.
ACT horizontal distance is 32nm which is equivalent to having a ACT cut mask with 32nm horizontal resolution. We consider for this design rule set that this technique is defined at process level and not design.

Version 1.2 Release Date (Not Yet Released)

NW LAYER
NW.1 180 nm Minimum spacing of NW/(not NW) at different potential (3) Updated scale ratio to 0.8 (20% reduction only)
NW.2 110 nm Minimum spacing of NW/(not NW) at the same potential (3)
NW.3 160 nm Minimum width of NW/(not NW) (3)
NW.4 0.140 um2 Minimum area/enclosed area of NW This is just a resolution rule added with fictitious value that fit other rules defined in this document.
NW.5 NW Must be orthogonal Restriction rule
NW.6 80nm Minimum extension of NW past GATE This is just a resolution rule added with fictitious value that fit other rules defined in this document.
ACTIVE LAYER
Looking at the graph comparing different Fin pitches, and making a trade off with M1 pitch at 64nm, the best option is to choose a Fin Pitch
that is a multiple of 8nm. We choose 40nm vs the 45nm in the paper default analysis, which seems to have tolerable impact in Rinterface, and
ACT.1 48 nm Minimum vertical width of ACT (1)
we shrink in theory the fin size from 10nm to 8nm. This results in min ACT width of 2*half_fin_width+1*fin_pitch=48nm. ACT grows in
incremental of 40nm fin pitch.
ACT.2 40 nm Incremental vertical width of ACT (1) See description in ACT.1
ACT.3 62 nm Minimum vertical spacing of ACT Twice the horizontal spacing
ACT.4 96 nm Minimum horizontal width of ACT Just enough for 6nm spacing to adjacent dummy GATE shape on either side of a single useful gate.
32, 96, or >= Just enough for (a) 6nm space on either side of a dummy GATE, or (b) a space between two gate lines, or (c) something larger than a space
ACT.5 160 nm HORIZONTAL spacing of ACT (5) between three gate lines
ACT.6 112 nm Minimum notch of ACT Assuming spacing use a special resolution technique (eg cut mask), notch doesn't match spacing rule. Using min horizontal width.
ACT.7 31 nm Minimum enclosure/spacing of NW to ACT Used 31nm which is half of vertical ACT space (to facilitate layout and still reflect multiple fin alignment/imprint strategies)
ACT.8 0.004608 um^2 Minimum area/enclosed area of ACT Transistor with 98nm x 48 nm to be the smallest allowed single ACT shape in technology.
Maximum distance between ACT forming a MOS device and ACT forming a This rule is to prevent latch-up. The value was calculated using 10x the size of a normal SDFFRS cell (26 * 116 * 10 rounded to 30000 from
ACT.9 30 um
bulk/substrate contact within the same well/substrate 30160). Would be nice to do real TCAD modeling on this to find more accurate value.
GATE LAYER (Double Patterning - 2 colors)
20 nm
GATE.1 16 nm GATE[A|B] exact horizontal width (1) Range of values allowed to permit gate shrinking at either process side or design side (mask).
14 nm
Enough to permit 64nm gate pitch. 58nm and 62nm pithes were explored in [1], but slight increase was chosent to accomodate other design
GATE.2 128 nm Horizontal Pitch of GATE[A|B] (1) rules when forming transistor + gap or transistor in series. 128nm is measured from middle projection line (lined perpendicular to longest
sides, centered in between.
GATE.3 44 nm Min HORIZONTAL spacing of GATEA and GATEB (1) Exact spacing to match GATE.1 and GATE.2 with 20nm gate length
GATE.4 GATE[A|B] may not bend (2)
GATE.5 38 nm ACT min extension past GATE[A|B] (4) Calculating exact ACT extension past gate to ensure 32nm exact ACT to ACT distance.
GATE.6 62 nm GATE[A|B] min extension past ACT (GATEC ignored) (4) This is a wild guess. Using vertical spacing between ACT shapes.
GATE.7 200 nm GATE[A|B] minimum length (vertical edge, GATEC ignored) Used transistor with 76nm + 2x min GATE extension past ACT as min gate size These layers
cannot co-exist.
(GATE[A|B] not GATEC) maximum distance to neighbor shape (same design mask Either GATEA
GATE.8 236 nm Can only skip one neighbor transistor (GATEC). This is to emphasize that one cannot cut two consecutive GATEA|B shapes.
outside GATEC) and GATEB are
GATE LAYER (Double Patterning - 1 color that will be processed later into 2 colors / decomposition at process level) used, or
GATEAB.
20 nm
GATE.1AB 16 nm GATEAB exact horizontal width (1) Same as GATE[A|B], just made single color assuming coloring is done at process level.
14 nm
GATE.2AB 64 nm Horizontal Pitch of GATEAB (1) Half pitch as coloring will be done as post-processing step.
GATE.3AB 44 nm Min HORIZONTAL spacing of GATEAB (1)
GATE.4AB GATEAB may not bend (2)
GATE.5AB 38 nm ACT min extension past GATEAB (4)
GATE.6AB 62 nm GATEAB min extension past ACT (GATEC ignored) (4)
GATE.7AB 200 nm GATEAB minimum length (vertical edge, GATEC ignored)
(GATEAB not GATEC) maximum distance to neighbor shape (same design mask outside
GATE.8AB 236 nm
GATEC)
Rule Value Description Notes Comments
GATE C (Gate Metal Cut Mask)
GATEC.1.a 32 nm Exact vertical width of GATEC (shape is oriented horizontally) Gate cut layer - also a wild guess. Using same as ACT-ACT spacing which could also be a cut layer.
GATEC.1.b 64 nm Exact horizontal width of GATEC (shape is oriented vertically)
GATEC.2.a 128 nm Minimum horizontal length of GATEC (shape is oriented horizontally) This assumes 22nm min extension of GATEC past GATEA|B and min length for RET that overlaps 2 consecutive gates.
GATEC.2.b 64nm Exact vertical length of GATEC (shape is oriented vertically) Square cut to be drawn on a single gate. Could be useful on cross-cut nets (e.g. clock net on flops)
GATEC.3 128 nm Minimum space of GATEC Two gate pitches assumed between GATEC shapes (maybe too much?)
GATEC.4 22nm Minimum extension of GATEC past GATE[A|B], HORIZONTAL direction This is to force GATEC alignment of gates. This value was calulated assuming 128nm length (H dir), cutting 2 gates only.
GATEC.5 15 nm GATEC minimum space to ACT 62nm - GATEC width on horizontal shape (32nm) = 30nm. Divided it by two to define min space to ACT.
GATEC.6 GATEC may not bend
GATEC.7 GATEC shape bottom or top must be aligned if distance < 192 nm This should add regularity in layout to improve resolution
VTL/VTH LAYERS
VT.1 144 nm Minimum width of VTL/VTH/(not (VTL or VTH)) (3)
VT.2 144 nm Minimum space of VTL/VTH/(not (VTL or VTH)) (3)
VT.3 64nm Minimum enclosure of GATE[A|B] by VTL/VTH (3) Used GATE-GATE space with ACT break in the middle (128nm - 20nm gate L = 108nm) - Distributed 64nm to encl and 44nm to space
VT.4 44 nm Minimum space of VTL/VTH to GATEA|B (3) See description in VT.3
NIM/PIM LAYER
For layout regularity purposes and assuming resolution techniques, implants are rounded up to gate pitch value - space and notch rules are
NIM/PIM.1 128 nm Minimum width/spacing/notch of NIM/PIM
defined similarly.
NIM/PIM.2 32 nm Minimum spacing of NIM/PIM to channel Based on NIM/PIM.1
NIM/PIM.3 32 nm Minimum extension of NIM/PIM past channel (HORIZONTAL directions) Based on NIM/PIM.1
NIM/PIM.4 30 nm Minimum extension of NIM/PIM past channel (VERTICAL directions) Based on NIM/PIM.1 and ACT.3
NIM/PIM.5 30 nm Minimum space of NIM/PIM to (ACT enclosed by PIM/NIMP)
NIM/PIM.6 30 nm Minimum enclosure of ACT by NIM/PIM
NIM/PIM.7 0.049 um2 Minimum NIM/PIM area/enclosed area (3) Scaling to 35% of NWell min area (0.35 * 0.14 um2)
AIL1 LAYER
AIL1.1 28 nm Minimum Horizontal Width of AIL1 (1) [1] has 27nm. It was rounded up to 28nm for symmetry (simplification) purposes.
We'll assume double patterning of AIL1 to be done, but at process level. So single color will be defined at CAD level, similar to GATEA|B.
AIL1.2 36 nm Minimum Horizontal Spacing of AIL1 (1) Considering paper [1] gives us a minimum of 31nm, if we use AIL1.1 rule and the gate pitch rule, we derive 36nm. (8nm spacing from AIL1 to
GATEA|B, GATEA|B max width of 20nm, 8nm spacing again).
AIL1.3 8 nm Minimum spacing of AIL1 to GATE[A|B] (1) Enough to accomodate AIL1.1 and AIL1.2
AIL1.4 2 nm Minimum extension of ACT past AIL1 (HORIZONTAL direction) (1) Compliance rule to AIL1.3
AIL1.5 58 nm Vertical length of AIL1 Assuming ACT-ACT min vertical space
AIL1.6 62 nm Vertical spacing of AIL1
AIL1 horizontal edges (perpendicular to gate direction) must be aligned or extend beyond
AIL1.7 0nm ACT horizontal edges (AIL1 must extend across ACT shape). Minimum vertical extension (3) This rule automatically inherit the min ACT vertical width rule, and was chosen for simplification.
of AIL1 past ACT is 0nm.
AIL1.8 AIL1 may not bend (2)
AIL2 LAYER
AIL2.1 24 nm Minimum Horizontal width of AIL2 (4) Reflects assumptions in AIL1 layer, ensures 2nm side enclosure by AIL1 (reduced from 3 nm in [1]).
AIL2.2 40 nm Minimum Horizontal spacing of AIL2 (4) Reflects assumptions in AIL1 layer
AIL2.3 2 nm Minimum spacing between AIL2 and GATE[A|B] Inferred from NanGate 15nm OCL
AIL2.4 2 nm Minimum enclosure of AIL2 by AIL1, HORIZONTAL direction (4) In [1], IM1 extends about 3nm beyond IM2. AIL2.1 was modified in a way this rule results in 2nm.
AIL2.5 6 nm Minimum Vertical overlap of AIL1 and AIL2 Inferred from NanGate 15nm OCL
AIL2.6 68 nm Vertical length of AIL2 Maintain area constant on critical shapes. E.g. AIL1 = 28x58=1624. Then AIL2 length = 1624/24=67.67 (rounding to 68)
AIL2.7 62nm Vertical spacing of AIL2 Using same value as AIL1.6
AIL2.8 AIL2 may not bend (2)
AIL2.9 16 nm Horizontal spacing of AIL2 and AIL1 not on same net Inferred from NanGate 15nm OCL
AIL2.10 16 nm Vertical spacing of AIL2 and AIL1 not on same net Inferred from NanGate 15nm OCL
GIL LAYER
GIL.1 44 nm Minimum VERTICAL width of GIL (4) Reduced to 44nm from 45nm (assumed based on [1]). This is to match other layout resolutions used in this pdk.
GIL.2 56 nm Minimum HORIZONTAL length of GIL (4) Based on layout regularity. Calculated from AIL2 and GATE rules considering at least 20% longer edge on H dir.
GIL.3 32 nm GIL minimum VERTICAL space (40nm rectangular extension) Considered 20% smaller space when compared to HORIZONTAL spacing
Rule Value Description Notes Comments
GIL.4 40 nm GIL minimum HORIZONTAL space (32nm rectangular extension) This is calculated assuming GIL.2 and GIL.6
GIL.5 6 nm GIL VERTICAL space to ACT This was calculated assuming 62nm ACT to ACT vertical spacing and CB vertical width
In [1], IM2 extends about 4nm beyond GATE[A|B], ITRS 2011 states "The fundamental premise is that both the line and the space must meet
GIL.6 2 nm GIL minimum HORIZONTAL extension past GATE[A|B] (4)
the 12% CD specification"... and 12% of CD is about 2nm
GIL.7 8 nm GIL HORIZONTAL space to AIL2 (different nets)
GIL.8 5 nm GIL VERTICAL space to AIL2 Inferred from NanGate 15nm OCL, should reflect the fact that these two layers are in different masks but should not overlap if != nets.
GIL.9 10 nm GIL minimum HORIZONTAL space to GATE[A|B] Derived from other rules
GIL.10 2 nm AIL2 min HORIZONTAL overlap of GIL (same net) Inferred from NanGate 15nm OCL
GIL.11 4 nm AIL2 minimum VERTICAL extension past GIL (4) In [1], IM2 extends about 4nm
GIL.12 GIL may not bend (2)
V0 LAYER (double patterning ignored at design level, assuming decomposition at mask level)
V0 shape is a square or rectangle respecting V0.1.a or V0.1.b. V0.1.b is mandatory when
V0.1 This is a wild guess on a rule to accomodate current crawding on square vias.
V0 is enclosed by Metal1 shapes with width >= 60nm.
V0.1.a 28 nm V0 is a square with 28nm edge length Made it 2nm bigger than AIL2 to express negative enclosure properties (may be a challenge to P&R tools).
V0.1.b [28nm, 56nm] V0 is a rectangular of sides = [28nm, 56nm, 28nm, 56nm] Rectangular shape should be equal to two square shapes merged (aligned edges)
V0.2 36 nm Minimum spacing of V0 (if runlength exactly 28nm) - Full alignment To match AIL2 pitch
Used a right isosceles triangle with 64nm (the V0 pitch) on the sides. This results in an hipotenuse of ~90nm to a V0 offset by 1 routing track.
V0.3 50 nm Minimum spacing of V0 for runlength < 28nm
Using 14nm displacement and similar calculation, the corner to corner distance is ~50nm. We are using this value in case of Via offset.
V0.4 V0 must be inside [AIL2|GIL] and M1[A|B] (3)
V0.5.a -2 nm V0 enclosure by AIL2 on two opposite sides, HORIZONTAL direction
V0.5.b 20 nm V0 enclosure by AIL2 on two opposite sides, VERTICAL direction
V0.6.a -2 nm V0 enclosure by (GIL and AIL2) on two opposite sides, HORIZONTAL direction
V0.6.b 8 nm V0 enclosure by (GIL and AIL2) on two opposite sides, VERTICAL direction
V0.7.a 14 nm V0 enclosure by (GIL not AIL2) on two opposite sides, HORIZONTAL direction Wild guess
V0.7.b 8 nm V0 enclosure by (GIL not AIL2) on two opposite sides, VERTICAL direction
V0.8 38 nm Minimum space of V0 and AIL2 of different net
V0.9 6 nm Minimum space of V0 and GIL of different net Inferred from NanGate 15nm OCL
V0.10 V0 enclosed by GIL may not overlap with (GATE[A|B] over ACT) Gate stacking restriction
METAL1 LAYER
2016 node in [2] has 19nm for M1 half-pitch. Even though this is conveniently the same as GATE[A|B] min width, it would restrict to one
M1.1 28 nm M1[A|B] width
direction only. We're growing M1 width to 28nm to assume it can bend (illumination), while keeping the same pitch.
M1.2 56 nm One of two edges connected to the same vertex must have at least Assumed to be double the minimum half-pitch, to model off-axis illumination
M1.3 1800 nm Maximum length of M1[A|B] for wires with min width (28nm) Inferred from NanGate 15nm OCL, puts restriction on metal routing to avoid IR drop, EM
M1.4 68 nm M1[A|B] end-of-Line spacing (EOL edge defined as edge < 32nm) Assume spacing requirement to increase 20% on EOL patterns
M1.5 54 nm M1[A|B] minimum space and notch This is a wild guess. We're assuming 50% over double patterning spacing
2016 node in [2] has 19nm for M1 half-pitch. This is conveniently the same as GATE[A|B] min width. Keeping same pitch as GATE before
M1.6 36 nm Minimum spacing of M1A to M1B
adjustment (58nm). This gives space to grow M1 width, move shapes, bend. [1] talks about M1 pitch at 64nm.
M1.7 44 nm End-of-Line spacing of M1A to M1B (EOL edge defined as edge < 32nm) Assume spacing requirement to increase 20% on EOL patterns
M1.8 68 nm Minimum spacing of M1[A|B] wider than 32 nm and longer than 240 nm (3) Wild guess, start at EOL value, grow randomly
M1.9 76 nm Minimum spacing of M1[A|B] wider than 40 nm and longer than 240 nm (3)
M1.10 92 nm Minimum spacing of M1[A|B] wider than 64 nm and longer than 480 nm (3)
M1.11 120 nm Minimum spacing of M1[A|B] wider than 120 nm and longer than 1.2 um (3)
M1.12 240 nm Minimum spacing of M1[A|B] wider than 240 nm and longer than 1.8 um (3)
M1.13 320 nm Minimum spacing of M1[A|B] wider than 320 nm and longer than 2.4 um (3)
M1.14 600 nm Minimum spacing of M1[A|B] wider than 600 nm and longer than 2.4 um (3)
M1.15 44 nm M1[A|B] minimum spacing to M1[B|A] wider than 32 nm and longer than 240 nm (3)
M1.16 50 nm M1[A|B] minimum spacing to M1[B|A] wider than 40 nm and longer than 240 nm (3)
M1.17 60 nm M1[A|B] minimum spacing to M1[B|A] wider than 64 nm and longer than 480 nm (3)
M1.18 78 nm M1[A|B] minimum spacing to M1[B|A] wider than 120 nm and longer than 1.2 um (3)
M1.19 156 nm M1[A|B] minimum spacing to M1[B|A] wider than 240 nm and longer than 1.8 um (3)
M1.20 200 nm M1[A|B] minimum spacing to M1[B|A] wider than 320 nm and longer than 2.4 um (3)
M1.21 400 nm M1[A|B] minimum spacing to M1[B|A] wider than 600 nm and longer than 2.4 um (3)
Rule Value Description Notes Comments
M1.22 40 nm Minimum overlap of M1A and M1B (stitch reagion length) Wild guess
[28, 2, 28, 2]
M1.23 [32, 0, 32, 0] Allowed enclosures of V0 by M1[A|B] (6) Derived from min edge and other values
[10, 10, 10, 10]
[32, 2, 32, 2]
M1.24 [40, 0, 40, 0] Allowed enclosures of V0 by M1[A|B] on overlapping zone (stitch area) Adding conservative values compared to enclosure
[14, 14, 14, 14]
M1.26 V0 shape must be rectangular if enclosing M1[A|B] wire width >= 60nm
M1.27 0.0024 um2 M1[A|B] minimum area for rectangular shape Assuming 120nm x 20nm min shape size. Should create enough blockage to reflect routing congestion.
M1.28 0.0036 um2 M1[A|B] minimum area for non-rectangular shape Assuming 50% more than area rule for rectangular shapes
Vn LAYER, n=1..5
Vn.1 V1|VINTn shape is a square or rectangle respecting Vn.1.a or Vn.1.b. Vn.1.b is mandatory when V1|VINTn is enclosed by [M1|MINT1] or [MINTn|MINT(n+1)] shapes with width >= 60nm.
Vn.1.a 28 nm V1|VINTn is a square with 28nm edge length
Vn.1.b [28nm, 56nm] V1|VINTn is a rectangular of sides = [28nm, 56nm, 28nm, 56nm] Twice the size of a square Via
Vn.2 36 nm Minimum spacing of V1|VINTn (if runlength exactly 28nm) - Full alignment
Vn.3 50 nm Minimum spacing of V1|VINTn for runlength < 28nm
Vn.4 V1 must be inside M1 and MINT1, VINTn must be inside MINTn[A|B] and M(n+1)[A|B] (3)
Vn.5 V1/VINTn shape must be rectangular if enclosing M1[A|B]/MINTn[A|B] wire width >= 60nm
MINTn LAYERS, n=2..6
MINT.1 28 nm MINTn[A|B] width minimum Changed to a minimum width rule
MINT.2 56 nm One of two edges connected to the same vertex must have at least
MINT.3 1800 nm Maximum length of MINTn[A|B] for wires with min width (28nm) Inferred from NanGate 15nm OCL, puts restriction on metal routing to avoid IR drop, EM
MINT.4 68 nm MINTn[A|B] end-of-Line spacing (EOL edge defined as edge < 32nm)
MINT.5 54 nm MINTn[A|B] minimum space and notch
MINT.6 36 nm Minimum spacing of MINTnA to MINTnB
MINT.7 44 nm End-of-Line spacing of MINTnA to MINTnB (EOL edge defined as edge < 32nm)
MINT.8 68 nm Minimum spacing of MINTn[A|B] wider than 32 nm and longer than 240 nm (3)
MINT.9 76 nm Minimum spacing of MINTn[A|B] wider than 40 nm and longer than 240 nm (3)
MINT.10 92 nm Minimum spacing of MINTn[A|B] wider than 64 nm and longer than 480 nm (3)
MINT.11 120 nm Minimum spacing of MINTn[A|B] wider than 120 nm and longer than 1.2 um (3)
MINT.12 240 nm Minimum spacing of MINTn[A|B] wider than 240 nm and longer than 1.8 um (3)
MINT.13 320 nm Minimum spacing of MINTn[A|B] wider than 320 nm and longer than 2.4 um (3)
MINT.14 600 nm Minimum spacing of MINTn[A|B] wider than 600 nm and longer than 2.4 um (3)
MINT.15 44 nm MINTn[A|B] minimum spacing to MINTn[B|A] wider than 32 nm and longer than 240 nm (3)
MINT.16 50 nm MINTn[A|B] minimum spacing to MINTn[B|A] wider than 40 nm and longer than 240 nm (3)
MINT.17 60 nm MINTn[A|B] minimum spacing to MINTn[B|A] wider than 64 nm and longer than 480 nm (3)
MINT.18 78 nm MINTn[A|B] minimum spacing to MINTn[B|A] wider than 120 nm and longer than 1.2 um (3)
MINT.19 156 nm MINTn[A|B] minimum spacing to MINTn[B|A] wider than 240 nm and longer than 1.8 um (3)
MINT.20 200 nm MINTn[A|B] minimum spacing to MINTn[B|A] wider than 320 nm and longer than 2.4 um (3)
MINT.21 400 nm MINTn[A|B] minimum spacing to MINTn[B|A] wider than 600 nm and longer than 2.4 um (3)
MINT.22 40 nm Minimum overlap of MINTnA and MINTnB (stitch reagion length)
[28, 2, 28, 2]
MINT.23 [32, 0, 32, 0] Allowed enclosures of V(n-1) by MINTn[A|B]
[10, 10, 10, 10]
[32, 2, 32, 2]
MINT.24 [40, 0, 40, 0] Allowed enclosures of V(n-1) by MINTn[A|B] on overlapping zone (stitch area)
[14, 14, 14, 14]
MINT.26 V(n-1) shape must be rectangular if enclosing MINTn[A|B] wire width >= 60nm
MINT.27 0.0024 um2 MINTn[A|B] minimum area for rectangular shape
MINT.28 0.0036 um2 MINTn[A|B] minimum area for non-rectangular shape
VSMGn LAYERS
VSMGn shape is a square or rectangle respecting VSMGn.1.a or VSMGn.1.b. VSMGn.1.
VSMGn.1 b is mandatory when Vn is enclosed by [MSMGn|MSMG(n+1)] shapes with width >=
120nm.
Rule Value Description Notes Comments
VSMGn.1.a 56 nm VSMGn is a square with 56nm edge length 2X of Vn.1.a
VSMGn.1.b [56nm, 112nm] VSMGn is a rectangular of sides = [56nm, 112nm, 56nm, 112nm] 2X of Vn.1.b
VSMGn.2 72 nm Minimum spacing of VSMGn (if runlength exactly 56nm) - Full alignment
VSMGn.3 100 nm Minimum spacing of VSMGn for runlength < 56nm
VSMGn.4 VSMGn must be inside (MSMGn[A|B] and MSMG (n+1) ) or ( MSMG(n)[A|B] and MG1)
VSMGn.5 VSMGn shape must be rectangular if enclosing (MSMGn[A|B] if n>1) wire width >= 80nm

MSMGn LAYERS
MSMGn.1 56 nm MSMGn width 2X the width of MINTn
MSMGn.2 112 nm One of two edges connected to the same vertex must have at least Assumed to be double the minimum half-pitch, to model off-axis illumination
MSMGn.3 1.920 um Maximum length of MSMGn for wires with min width (56nm) 2X MINTn.3
MSMGn.4 136 nm MSMGn end-of-Line spacing (EOL edge defined as edge < 64nm) Assume spacing requirement to increase 20% on EOL patterns
MSMGn.5 56nm MSMGn minimum space and notch 2X MINTn.5
MSMGn.6 92 nm Minimum spacing of MSMGn wider than 64 nm and longer than 480nm (3) Wild guess, start at EOL value, grow randomly
MSMGn.7 120 nm Minimum spacing of MSMGn wider than 120 nm and longer than 1.2 um (3) Wild guess, start at EOL value, grow randomly
MSMGn.8 240 nm Minimum spacing of MSMGn wider than 240 nm and longer than 1.8 um (3)
MSMGn.9 320 nm Minimum spacing of MSMGn wider than 320 nm and longer than 2.4 um (3)
MSMGn.10 600 nm Minimum spacing of MSMGn wider than 600 nm and longer than 2.4 um (3)
[28, 2, 28, 2]
MSMGn.11 [32, 0, 32, 0] Allowed enclosures of VSMG(n-1) by MSMGn (6) Derived from min edge and other values
[10, 10, 10, 10]
MSMGn.12 VSMG(n-1) center must be aligned to wire center (between the 2 longest edges)
MSMGn.13 VSMG(n-1) shape must be rectangular if enclosing wire width >= 120nm
MSMGn.14 0.0024 um2 MSMGn minimum area for rectangular shape Assuming 120nm x 20nm min shape size. Should create enough blockage to reflect routing congestion.
MSMGn.15 0.0036 um2 MSMGn minimum area for non-rectangular shape Assuming 50% more than area rule for rectangular shapes

VGn LAYERS
VG1 shape is a square or rectangle respecting VG1.1.a or VG1.1.b. VG1.1.b is
VG1.1
mandatory when VG1n is enclosed by [MGn|MG(n+1)] shapes with width >= 240nm.
VG1.1.a 112 nm VG1 is a square with 112nm edge length 4X of Vn.1.a
VG1.1.b [112nm, 224nm] VG1 is a rectangular of sides = [112nm, 224nm, 112nm, 224nm] 4X of Vn.1.b
VG1.2 144 nm Minimum spacing of VG1 (if runlength exactly 112nm) - Full alignment 4X of Vn.2
VG1.3 200 nm Minimum spacing of VG1 for runlength < 112nm 4X of Vn.3
VG1.4 VG1 must be inside (MGn[A|B] and MG(n+1)[A|B])
VG1 shape must be rectangular if enclosing (MGn[A|B] if n>1, or MSMG5[A|B] if n=1) wire
VG1.5
width >= 160nm

MGn LAYERS
MGn.1 112 nm MGn width 4X the width of MINTn
MGn.2 224nm One of two edges connected to the same vertex must have at least Assumed to be double the minimum half-pitch, to model off-axis illumination
MGn.3 3.840 um Maximum length of MGn for wires with min width (112nm) 4X MINTn.3
MGn.4 272 nm MGn end-of-Line spacing (EOL edge defined as edge < 128nm) Assume spacing requirement to increase 20% on EOL patterns
MGn.5 112nm MGn minimum space and notch 4X MINTn.5
MGn.6 120 nm Minimum spacing of MGn wider than 120 nm and longer than 1.2 um (3) Wild guess, start at EOL value, grow randomly
MGn.7 240 nm Minimum spacing of MGn wider than 240 nm and longer than 1.8 um (3)
MGn.8 320 nm Minimum spacing of MGn wider than 320 nm and longer than 2.4 um (3)
MGn.9 600 nm Minimum spacing of MGn wider than 600 nm and longer than 2.4 um (3)
MGn.10 0 Allowed enclosures of VGn by MGn (6) 4X of MINTn.23
MGn.11 VSMGn center must be aligned to wire center (between the 2 longest edges)
MGn.12 VSMGn shape must be rectangular if enclosing wire width >= 160nm
MGn.13 0.0024 um2 MGn minimum area for rectangular shape Assuming 120nm x 20nm min shape size. Should create enough blockage to reflect routing congestion.
MGn.14 0.0036 um2 MGn minimum area for non-rectangular shape Assuming 50% more than area rule for rectangular shapes
Rule Value Description Notes Comments

Other Rules
GRID 0.5 nm Shapes on all layers must be on a 0.5 nm grid
ANTENNA 100:1 Ratio of Maximum Allowed (GATE[A|B] or Metal Layer Area) to transistor Gate Area