A B C D E

1 1

Compal confidential
2

Liverpool/Sunderland 10AT 2

NSWAE/NTWAE LA-5332P Schematics Document

Mobile AMD S1G3/
RS880M & RS880MC / SB710
3 3

2009-11-24 Rev. 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2009-02-12 2009-02-12 Title
Issued Date Deciphered Date Schematic, MB LA-5332P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, February 05, 2010 Sheet 1 of 45
A B C D E
 A B C D E

Compal Confidential

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EC SMBUS
R5F211B4D33SP page 19 page 19

2
PCIe 4x 1.5V 2.5GHz(250MB/s) page 11,12,13,14,15 2

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SB710 USB 5x
USB 5V 480MHz
USB port 5
PCIe port 3 page 26 PCIe Port 2 page 27 5V 480MHz
PCIe port 0 page 27

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SATA 5V 1.5GHz(150MB/s) 3IN1

USBPort 8 page 27 USBPort 7 page 32 USBPort 4 page 29 page 29
page 26 USB port 2
USB 5V 480MHz
SATA port 2 page 25

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SATA
PCI BUS 3.3V 33 MHz
SATA port 1 page 25
5V 1.5GHz(150MB/s)
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5V 1.5GHz(150MB/s)
SLG8SP626VTR page 16 page 35 LPC BUS 3.3V 33 MHz
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page 35 page 25 page 33 ALC272 page 30

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page 36 page 35
page 33 TPA6017 page 31 page 31 page 31 page 31
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page 31

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page 37,38,39,40,41,42,43
4 4

page 31

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 12, 2009 Sheet 2 of 45
A B C D E
 5 4 3 2 1

DESIGN CURRENT 0.1A +3VL

DESIGN CURRENT 0.1A +5VL
B+
TPS51125RGER DESIGN CURRENT 1A +3VALW
DESIGN CURRENT 3.5A +5VALW

D SUSP D

N-CHANNEL DESIGN CURRENT 2A +5VS

SI4800
SUSP
N-CHANNEL DESIGN CURRENT 1.5A +3VS
SI4800
ENVDD
P-CHANNEL DESIGN CURRENT 1A +LCD_VDD
AO-3413
NSWAE Liverpool AMD SUSP
NTWAE Sunderland AMD DESIGN CURRENT 1.5A +1.5VS
APL5331KAC

BT_PWR#
C DESIGN CURRENT 180mA C
P-CHANNEL +BT_VCC
AO-3413
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413

DESIGN CURRENT 300mA +2.5VS

APL5508
POK
DESIGN CURRENT 0.3A +1.2VALW
TPS51117RGYR
VLDT_EN#
N-CHANNEL DESIGN CURRENT 4.5A +1.2V_HT
IRF8113
VR_ON
B DESIGN CURRENT 18A B
+CPU_CORE0
DESIGN CURRENT 18A +CPU_CORE1
ISL6265
DESIGN CURRENT 3A +VDDNB

SYSON
DESIGN CURRENT 7A +1.8V
TPS51117RGYR
SUSP
N-CHANNEL DESIGN CURRENT 1A +1.8VS
IRF8113
SYSON#
DESIGN CURRENT 2A +0.9V
APL5331KAC
A A
SUSP#
DESIGN CURRENT 7A +NB_CORE
TPS51117RGYR
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 12, 2009 Sheet 3 of 45
5 4 3 2 1
 A B C D E

@ : just reserve , no build Platform CPU NB VGA SB Comment

Voltage Rails
DEBUG@ : reserve for debug. S1G3 RS880MC NA SB710
O : ON S1G3 RS880M NA SB710
X : OFF

BTO (Build-To-Order) Option Table

+5VS Function Express card / PCMCIA BLUE TOOTH RJ11 SSD SATA ODD WiFi HDMI G- sensor 3 in 1 card reader FingerPrinter CAMERA & MIC

1
+3VS 1
power Description (E/A) (B) (R) (H) (Y) (S) (C) (F) (X)
plane +2.5VS
+1.8VS Explain 16" 17" Half - size First Second RTS5159 CAMERA MIC

+1.5VS
BTO EXPCARD@ / PCMCIA@ BT@ MDC@ SSD@ 16inch@ 17inch@ WLAN@ H@ G@ + G_1st@ G@ + G_2nd@ CARD@ FP@ CAM@ MIC@
+1.1VS
+B +5VALW +1.8V
+VGA_CORE
+3VL +3VALW +0.9V
+1.2V_HT Function DC-IN Side port
+5VL +1.2VALW +0.9V
State +CPU_CORE_NB
+RTCVCC +3V_LAN Description (L)
+CPU_CORE_0
+CPU_CORE_1 Explain

BTO 16inch_45@ 17inch_45@ SIDE@ NSIDE@

S0 O O O O
S1 O O O O
2 2

S3 O O O X
S5 S4/AC O O X X
S5 S4/ Battery only O X X X
SMBUS Control Table
S5 S4/AC & Battery
don't exist X X X X CPU LCD HDMI
SOURCE INVERTER BATT HDMI SODIMM CLK WLAN DDC DDC NEW
CEC THERMAL GEN CARD
I / II ROM ROM
SENSOR
EC_SMB_CK1
KB926
I2C / SMBUS ADDRESSING EC_SMB_DA1 V V
EC_SMB_CK2
KB926
EC_SMB_DA2 V
DEVICE HEX ADDRESS
I2C_CLK
RS880M
3
DDR SO-DIMM 0 A0 10100000 I2C_DATA V 3

DDR SO-DIMM 1 A2 10100010 DDC_CLK0

RS880M
CLOCK GENERATOR (EXT.) D2 11010010 DDC_DATA0 V
DDC_CLK1
RS880M
DDC_DATA1
SCL0
SB710
SDA0 V V V
EC SM Bus1 address EC SM Bus2 address SCL1
SB710
SDA1 V
Device HEX Address Device HEX Address
SCL2
Smart Battery 16H 0001 011X b ADI1032-1 CPU 98H 1001 100X b SB710
SDA2
HDMI-CEC 34H 0011 010X b ADI1032-2 VGA 9AH 1001 101X b
SCL3
EC KB926D3 EC KB926D3 SB710
SDA3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 12, 2009 Sheet 4 of 45
A B C D E
 A B C D E

+1.2V_HT

250 mil VLDT CAP. Near CPU Socket

1 1 1 1 1 1
C1 C2 C3 C4 C5 C6

10U_0805_10V6K 10U_0805_10V6K 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J

2 2 2 2 2 2

1 1

H_CADIP[0..15] H_CADOP[0..15]
11 H_CADIP[0..15] H_CADOP[0..15] 11
H_CADIN[0..15] H_CADON[0..15]
11 H_CADIN[0..15] H_CADON[0..15] 11

+1.2V_HT JCPUA
C7
D1 HT LINK AE2 +VLDT_B 1 2 10U_0805_10V6K < VLDT_A & VLDT_B : HyperTransport I/O ring power >
VLDT_A0 VLDT_B0
VLDT=500mA D2 VLDT_A1 VLDT_B1 AE3
D3 VLDT_A2 VLDT_B2 AE4
D4 VLDT_A3 VLDT_B3 AE5

H_CADIP0 E3 AD1 H_CADOP0

H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
2 H_CADIP4 H_CADOP4 2
J1 L0_CADIN_H4 L0_CADOUT_H4 W2
H_CADIN4 K1 W3 H_CADON4
H_CADIP5 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP5
L3 L0_CADIN_H5 L0_CADOUT_H5 V1
H_CADIN5 L2 U1 H_CADON5
H_CADIP6 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP6
L1 L0_CADIN_H6 L0_CADOUT_H6 U2
H_CADIN6 M1 U3 H_CADON6
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H_CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H_CADIN8 F5 AD3 H_CADON8
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9
< From NB > F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 < To NB >
H_CADIN9 F4 AC5 H_CADON9
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
H_CADIN10 H5 AB3 H_CADON10
H_CADIP11 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP11
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5
H_CADIN11 H4 AA5 H_CADON11
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 L0_CADIN_H12 L0_CADOUT_H12 Y5
H_CADIN12 K4 W5 H_CADON12
H_CADIP13 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP13
L5 L0_CADIN_H13 L0_CADOUT_H13 V4
H_CADIN13 M5 V3 H_CADON13
H_CADIP14 L0_CADIN_L13 L0_CADOUT_L13 H_CADOP14
M3 L0_CADIN_H14 L0_CADOUT_H14 V5
H_CADIN14 M4 U5 H_CADON14
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 L0_CADIN_H15 L0_CADOUT_H15 T4
H_CADIN15 P5 T3 H_CADON15
L0_CADIN_L15 L0_CADOUT_L15

11 H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 11

11 H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 11
11 H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 11
11 H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 11

11 H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 11

11 H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 11
3 3
11 H_CTLIP1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 H_CTLOP1 11
11 H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 11

@ 6090022100G_B

< FAN Control Circuit : Vout = 1.6 x Vset >

+5VS

1A
1

D1
2 @
+FAN1 C183 1SS355_SOD323-2
JFAN +3VS
1
2

C192 10U_0805_10V4Z +FAN1 1

1 1
2 2
1

10U_0805_10V4Z 1 3
2 U6 D2 C9 3 R12
1 8 @ @ 4
EN GND BAS16_SOT23-3 1000P_0402_50V7K GND 10K_0402_5%
2 VIN GND 7 5 GND
2
3 6
2

VOUT GND @ ACES_85204-0300N

< From EC > 34 EN_DFAN1 4 VSET GND 5 FAN_SPEED1 34 < To EC >
4 4
2
APL5607KI-TRG_SO8 C8
@
0.01U_0402_25V7K
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 5 of 45
A B C D E
 A B C D E

< DDR2 VREF is 0.5 ratio > < PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH > < Processor DDR2 Memory Interface >
+1.8V
DDR_A_CLK0 DDR_B_CLK0
1 1
2

C10 C14
R1
1.5P_0402_50V9C 1.5P_0402_50V9C JCPUC
9 DDR_B_D[63..0]
1K_0402_1% DDR_A_CLK#0 2 DDR_B_CLK#0 2 MEM:DATA
DDR_A_D[63..0] 10
< From/To SO_DIMMB > DDR_B_D0 C11 G12 DDR_A_D0
1

+MCH_REF DDR_B_D1 MB_DATA0 MA_DATA0 DDR_A_D1

A11 MB_DATA1 MA_DATA1 F12 < From/To SO_DIMMA >
DDR_B_D2 A14 H14 DDR_A_D2
MB_DATA2 MA_DATA2
2

1 1 DDR_A_CLK1 DDR_B_CLK1 DDR_B_D3 B14 G14 DDR_A_D3

R2 C12 C13 DDR_B_D4 MB_DATA3 MA_DATA3 DDR_A_D4
1 1 G11 MB_DATA4 MA_DATA4 H11
C11 C15 DDR_B_D5 E11 H12 DDR_A_D5
1 1K_0402_1% 0.1U_0402_16V7K 1000P_0402_50V7K DDR_B_D6 MB_DATA5 MA_DATA5 DDR_A_D6 1
D12 MB_DATA6 MA_DATA6 C13
2 2 1.5P_0402_50V9C 1.5P_0402_50V9C DDR_B_D7 DDR_A_D7
A13 E13
1

DDR_A_CLK#1 2 DDR_B_CLK#1 2 DDR_B_D8 MB_DATA7 MA_DATA7 DDR_A_D8

A15 MB_DATA8 MA_DATA8 H15
DDR_B_D9 A16 E15 DDR_A_D9
DDR_B_D10 MB_DATA9 MA_DATA9 DDR_A_D10
A19 MB_DATA10 MA_DATA10 E17
DDR_B_D11 A20 H17 DDR_A_D11
DDR_B_D12 MB_DATA11 MA_DATA11 DDR_A_D12
C14 MB_DATA12 MA_DATA12 E14
DDR_B_D13 D14 F14 DDR_A_D13
DDR_B_D14 MB_DATA13 MA_DATA13 DDR_A_D14
C18 MB_DATA14 MA_DATA14 C17
DDR_B_D15 D18 G17 DDR_A_D15
DDR_B_D16 MB_DATA15 MA_DATA15 DDR_A_D16
D20 MB_DATA16 MA_DATA16 G18
DDR_B_D17 A21 C19 DDR_A_D17
DDR_B_D18 MB_DATA17 MA_DATA17 DDR_A_D18
D24 MB_DATA18 MA_DATA18 D22
DDR_B_D19 C25 E20 DDR_A_D19
DDR_B_D20 MB_DATA19 MA_DATA19 DDR_A_D20
B20 MB_DATA20 MA_DATA20 E18
DDR_B_D21 C20 F18 DDR_A_D21
DDR_B_D22 MB_DATA21 MA_DATA21 DDR_A_D22
B24 MB_DATA22 MA_DATA22 B22
DDR_B_D23 C24 C23 DDR_A_D23
DDR_B_D24 MB_DATA23 MA_DATA23 DDR_A_D24
E23 MB_DATA24 MA_DATA24 F20
DDR_B_D25 E24 F22 DDR_A_D25
DDR_B_D26 MB_DATA25 MA_DATA25 DDR_A_D26
G25 MB_DATA26 MA_DATA26 H24
DDR_B_D27 G26 J19 DDR_A_D27
DDR_B_D28 MB_DATA27 MA_DATA27 DDR_A_D28
C26 MB_DATA28 MA_DATA28 E21
DDR_B_D29 D26 E22 DDR_A_D29
DDR_B_D30 MB_DATA29 MA_DATA29 DDR_A_D30
G23 MB_DATA30 MA_DATA30 H20
DDR_B_D31 G24 H22 DDR_A_D31
+0.9V +0.9V DDR_B_D32 MB_DATA31 MA_DATA31 DDR_A_D32
AA24 MB_DATA32 MA_DATA32 Y24
JCPUB DDR_B_D33 AA23 AB24 DDR_A_D33
DDR_B_D34 MB_DATA33 MA_DATA33 DDR_A_D34
AD24 MB_DATA34 MA_DATA34 AB22
D10 W10 DDR_B_D35 AE24 AA21 DDR_A_D35
VTT1 MEM:CMD/CTRL/CLK VTT5 DDR_B_D36 MB_DATA35 MA_DATA35 DDR_A_D36
C10 VTT2 VTT6 AC10 < VTT regulator voltage > AA26 MB_DATA36 MA_DATA36 W22
Place them close to CPU within 1" B10 AB10 DDR_B_D37 AA25 W21 DDR_A_D37
2 VTT3 VTT7 DDR_B_D38 MB_DATA37 MA_DATA37 DDR_A_D38 2
AD10 VTT4 VTT8 AA10 AD26 MB_DATA38 MA_DATA38 Y22
A10 DDR_B_D39 AE25 AA22 DDR_A_D39
R4 1 VTT9 MB_DATA39 MA_DATA39
2 39.2_0402_1% MEM_P AF10 MEMZP
DDR_B_D40 AC22 MB_DATA40 MA_DATA40 Y20 DDR_A_D40
+1.8V R3 1 2 39.2_0402_1% MEM_N AE10 Y10 VTT_SENSE DDR_B_D41 AD22 AA20 DDR_A_D41
MEMZN VTT_SENSE PAD T1 MB_DATA41 MA_DATA41
DDR_B_D42 AE20 AA18 DDR_A_D42
+MCH_REF DDR_B_D43 MB_DATA42 MA_DATA42 DDR_A_D43
T2 PAD H16 RSVD_M1 MEMVREF W17 AF20 MB_DATA43 MA_DATA43 AB18
DDR_B_D44 AF24 AB21 DDR_A_D44
DDR_A_ODT0 DDR_B_D45 MB_DATA44 MA_DATA44 DDR_A_D45
10 DDR_A_ODT0 T19 MA0_ODT0 RSVD_M2 B18 PAD T3 AF23 MB_DATA45 MA_DATA45 AD21
< To SO_DIMMA > DDR_A_ODT1 V22 DDR_B_D46 AC20 AD19 DDR_A_D46
10 DDR_A_ODT1 MA0_ODT1 MB_DATA46 MA_DATA46
U21 W26 DDR_B_ODT0 DDR_B_D47 AD20 Y18 DDR_A_D47
MA1_ODT0 MB0_ODT0 DDR_B_ODT0 9 MB_DATA47 MA_DATA47
V19 W23 DDR_B_ODT1 < To SO_DIMMB > DDR_B_D48 AD18 AD17 DDR_A_D48
MA1_ODT1 MB0_ODT1 DDR_B_ODT1 9 MB_DATA48 MA_DATA48
Y26 DDR_B_D49 AE18 W16 DDR_A_D49
DDR_CS0_DIMMA# T20 MB1_ODT0 DDR_B_D50 MB_DATA49 MA_DATA49 DDR_A_D50
10 DDR_CS0_DIMMA# MA0_CS_L0 AC14 MB_DATA50 MA_DATA50 W14
< To SO_DIMMA > DDR_CS1_DIMMA# U19 V26 DDR_CS0_DIMMB# DDR_B_D51 AD14 Y14 DDR_A_D51
10 DDR_CS1_DIMMA# MA0_CS_L1 MB0_CS_L0 DDR_CS0_DIMMB# 9 MB_DATA51 MA_DATA51
U20 W25 DDR_CS1_DIMMB# < To SO_DIMMB > DDR_B_D52 AF19 Y17 DDR_A_D52
MA1_CS_L0 MB0_CS_L1 DDR_CS1_DIMMB# 9 MB_DATA52 MA_DATA52
V20 U22 DDR_B_D53 AC18 AB17 DDR_A_D53
MA1_CS_L1 MB1_CS_L0 DDR_B_D54 MB_DATA53 MA_DATA53 DDR_A_D54
AF16 MB_DATA54 MA_DATA54 AB15
DDR_CKE0_DIMMA J22 J25 DDR_CKE0_DIMMB DDR_B_D55 AF15 AD15 DDR_A_D55
10 DDR_CKE0_DIMMA MA_CKE0 MB_CKE0 DDR_CKE0_DIMMB 9 MB_DATA55 MA_DATA55
< To SO_DIMMA > DDR_CKE1_DIMMA J20 H26 DDR_CKE1_DIMMB < To SO_DIMMB > DDR_B_D56 AF13 AB13 DDR_A_D56
10 DDR_CKE1_DIMMA MA_CKE1 MB_CKE1 DDR_CKE1_DIMMB 9 MB_DATA56 MA_DATA56
DDR_B_D57 AC12 AD13 DDR_A_D57
DDR_B_D58 MB_DATA57 MA_DATA57 DDR_A_D58
N19 MA_CLK_H0 MB_CLK_H0 P22 AB11 MB_DATA58 MA_DATA58 Y12
N20 R22 DDR_B_D59 Y11 W11 DDR_A_D59
DDR_A_CLK0 MA_CLK_L0 MB_CLK_L0 DDR_B_CLK0 DDR_B_D60 MB_DATA59 MA_DATA59 DDR_A_D60
10 DDR_A_CLK0 E16 MA_CLK_H1 MB_CLK_H1 A17 DDR_B_CLK0 9 AE14 MB_DATA60 MA_DATA60 AB14
< To SO_DIMMA > DDR_A_CLK#0 F16 A18 DDR_B_CLK#0 < To SO_DIMMB > DDR_B_D61 AF14 AA14 DDR_A_D61
10 DDR_A_CLK#0 MA_CLK_L1 MB_CLK_L1 DDR_B_CLK#0 9 MB_DATA61 MA_DATA61
DDR_A_CLK1 Y16 AF18 DDR_B_CLK1 DDR_B_D62 AF11 AB12 DDR_A_D62
10 DDR_A_CLK1 MA_CLK_H2 MB_CLK_H2 DDR_B_CLK1 9 MB_DATA62 MA_DATA62
DDR_A_CLK#1 AA16 AF17 DDR_B_CLK#1 DDR_B_D63 AD11 AA12 DDR_A_D63
10 DDR_A_CLK#1 MA_CLK_L2 MB_CLK_L2 DDR_B_CLK#1 9 MB_DATA63 MA_DATA63
P19 MA_CLK_H3 MB_CLK_H3 R26 9 DDR_B_DM[7..0] DDR_A_DM[7..0] 10
P20 R25 DDR_B_DM0 A12 E12 DDR_A_DM0
MA_CLK_L3 MB_CLK_L3 DDR_B_DM1 MB_DM0 MA_DM0 DDR_A_DM1
< To SO_DIMMA > 10 DDR_A_MA[15..0] DDR_B_MA[15..0] 9 < To SO_DIMMB > < To SO_DIMMB > B16 MB_DM1 MA_DM1 C15 < To SO_DIMMA >
DDR_A_MA0 N21 P24 DDR_B_MA0 DDR_B_DM2 A22 E19 DDR_A_DM2
DDR_A_MA1 MA_ADD0 MB_ADD0 DDR_B_MA1 DDR_B_DM3 MB_DM2 MA_DM2 DDR_A_DM3
M20 MA_ADD1 MB_ADD1 N24 E25 MB_DM3 MA_DM3 F24
DDR_A_MA2 N22 P26 DDR_B_MA2 DDR_B_DM4 AB26 AC24 DDR_A_DM4
3 DDR_A_MA3 MA_ADD2 MB_ADD2 DDR_B_MA3 DDR_B_DM5 MB_DM4 MA_DM4 DDR_A_DM5 3
M19 MA_ADD3 MB_ADD3 N23 AE22 MB_DM5 MA_DM5 Y19
DDR_A_MA4 M22 N26 DDR_B_MA4 DDR_B_DM6 AC16 AB16 DDR_A_DM6
DDR_A_MA5 MA_ADD4 MB_ADD4 DDR_B_MA5 DDR_B_DM7 MB_DM6 MA_DM6 DDR_A_DM7
L20 MA_ADD5 MB_ADD5 L23 AD12 MB_DM7 MA_DM7 Y13
DDR_A_MA6 M24 N25 DDR_B_MA6
DDR_A_MA7 MA_ADD6 MB_ADD6 DDR_B_MA7 DDR_B_DQS0 DDR_A_DQS0
L21 MA_ADD7 MB_ADD7 L24 9 DDR_B_DQS0 C12 MB_DQS_H0 MA_DQS_H0 G13 DDR_A_DQS0 10
DDR_A_MA8 L19 M26 DDR_B_MA8 DDR_B_DQS#0 B12 H13 DDR_A_DQS#0
MA_ADD8 MB_ADD8 9 DDR_B_DQS#0 MB_DQS_L0 MA_DQS_L0 DDR_A_DQS#0 10
DDR_A_MA9 K22 K26 DDR_B_MA9 DDR_B_DQS1 D16 G16 DDR_A_DQS1
MA_ADD9 MB_ADD9 9 DDR_B_DQS1 MB_DQS_H1 MA_DQS_H1 DDR_A_DQS1 10
DDR_A_MA10 R21 T26 DDR_B_MA10 DDR_B_DQS#1 C16 G15 DDR_A_DQS#1
MA_ADD10 MB_ADD10 9 DDR_B_DQS#1 MB_DQS_L1 MA_DQS_L1 DDR_A_DQS#1 10
DDR_A_MA11 L22 L26 DDR_B_MA11 DDR_B_DQS2 A24 C22 DDR_A_DQS2
MA_ADD11 MB_ADD11 9 DDR_B_DQS2 MB_DQS_H2 MA_DQS_H2 DDR_A_DQS2 10
DDR_A_MA12 K20 L25 DDR_B_MA12 DDR_B_DQS#2 A23 C21 DDR_A_DQS#2
MA_ADD12 MB_ADD12 9 DDR_B_DQS#2 MB_DQS_L2 MA_DQS_L2 DDR_A_DQS#2 10
DDR_A_MA13 V24 W24 DDR_B_MA13 DDR_B_DQS3 F26 G22 DDR_A_DQS3
MA_ADD13 MB_ADD13 9 DDR_B_DQS3 MB_DQS_H3 MA_DQS_H3 DDR_A_DQS3 10
DDR_A_MA14 K24 J23 DDR_B_MA14 DDR_B_DQS#3 E26 G21 DDR_A_DQS#3
MA_ADD14 MB_ADD14 9 DDR_B_DQS#3 MB_DQS_L3 MA_DQS_L3 DDR_A_DQS#3 10
DDR_A_MA15 K19 J24 DDR_B_MA15 DDR_B_DQS4 AC25 AD23 DDR_A_DQS4
MA_ADD15 MB_ADD15 9 DDR_B_DQS4 MB_DQS_H4 MA_DQS_H4 DDR_A_DQS4 10
DDR_B_DQS#4 AC26 AC23 DDR_A_DQS#4
9 DDR_B_DQS#4 MB_DQS_L4 MA_DQS_L4 DDR_A_DQS#4 10
DDR_A_BS#0 R20 R24 DDR_B_BS#0 DDR_B_DQS5 AF21 AB19 DDR_A_DQS5
10 DDR_A_BS#0 MA_BANK0 MB_BANK0 DDR_B_BS#0 9 9 DDR_B_DQS5 MB_DQS_H5 MA_DQS_H5 DDR_A_DQS5 10
< To SO_DIMMA > DDR_A_BS#1 R23 U26 DDR_B_BS#1 < To SO_DIMMB > DDR_B_DQS#5 AF22 AB20 DDR_A_DQS#5
10 DDR_A_BS#1 MA_BANK1 MB_BANK1 DDR_B_BS#1 9 9 DDR_B_DQS#5 MB_DQS_L5 MA_DQS_L5 DDR_A_DQS#5 10
DDR_A_BS#2 J21 J26 DDR_B_BS#2 DDR_B_DQS6 AE16 Y15 DDR_A_DQS6
10 DDR_A_BS#2 MA_BANK2 MB_BANK2 DDR_B_BS#2 9 9 DDR_B_DQS6 MB_DQS_H6 MA_DQS_H6 DDR_A_DQS6 10
DDR_B_DQS#6 AD16 W15 DDR_A_DQS#6
9 DDR_B_DQS#6 MB_DQS_L6 MA_DQS_L6 DDR_A_DQS#6 10
DDR_A_RAS# R19 U25 DDR_B_RAS# DDR_B_DQS7 AF12 W12 DDR_A_DQS7
10 DDR_A_RAS# MA_RAS_L MB_RAS_L DDR_B_RAS# 9 9 DDR_B_DQS7 MB_DQS_H7 MA_DQS_H7 DDR_A_DQS7 10
< To SO_DIMMA > DDR_A_CAS# T22 U24 DDR_B_CAS# < To SO_DIMMB > DDR_B_DQS#7 AE12 W13 DDR_A_DQS#7
10 DDR_A_CAS# MA_CAS_L MB_CAS_L DDR_B_CAS# 9 9 DDR_B_DQS#7 MB_DQS_L7 MA_DQS_L7 DDR_A_DQS#7 10
DDR_A_WE# T24 U23 DDR_B_WE#
10 DDR_A_WE# MA_WE_L MB_WE_L DDR_B_WE# 9
< From/To SO_DIMMB > < From/To SO_DIMMA >
@ 6090022100G_B
@ 6090022100G_B

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 6 of 45
A B C D E
 A B C D E

JCPUD

+CPU_CORE_0 < Close to CPU > +2.5VDDA F8 VDDA1 KEY1 M11

R487 F9 W18
10_0402_5% CPU_VDD0_RUN_FB_H VDDA2 KEY2
1 2
CPU_CLKIN_SC_P A9 A6 CPU_SVC
R486 CPU_CLKIN_SC_N CLKIN_H SVC CPU_SVD CPU_SVC 43 < Serial VID Interface clock & data >
A8 CLKIN_L SVD A4 CPU_SVD 43
1 2 10_0402_5% CPU_VDD0_RUN_FB_L
LDT_RST# B7
H_PWRGD RESET_L
A7 PWROK
LDT_STOP# F10 AF6 CPU_THERMTRIP#_R < Thermal Sensor Trip output >
CPU_LDT_REQ_R# LDTSTOP_L THERMTRIP_L
Un-Mount R488 & R489 For Caspian C6 LDTREQ_L PROCHOT_L AC7 CPU_PROCHOT#_1.8 < HTC-active state indication or command >
+CPU_CORE_1 AA8 2 1 @ R42
MEMHOT_L +1.8V
R489 < Sideband-Temperature Sensor Interface Clock & Data> AF4 300_0402_5%
@ 1 10_0402_5% CPU_VDD1_RUN_FB_H SIC
2 AF5 SID
1 < Sideband-Temperature Sensor Interface interrupt > THERMDC_CPU 1
AE6 ALERT_L THERMDC W7
R488 W8 THERMDA_CPU < Thermal diode cathode & anode >
@ 1 10_0402_5% CPU_VDD1_RUN_FB_L R13 CPU_HTREF0 THERMDA
2 < Compensation Resistor to VSS > 1 2 44.2_0402_1% R6 HT_REF0
+1.2V_HT R14 1 2 44.2_0402_1% CPU_HTREF1 P6
< Compensation Resistor to VLDT > HT_REF1
+1.8V sense no support
43 CPU_VDD0_RUN_FB_H CPU_VDD0_RUN_FB_H F6 W9
VDD0_FB_H VDDIO_FB_H PAD T22
43 CPU_VDD0_RUN_FB_L CPU_VDD0_RUN_FB_L E6 Y9 < Differential feedback for VDDIO >
VDD0_FB_L VDDIO_FB_L PAD T21 < VDDIO : DDR SDRAM I/O ring power supply>
< 200-MHz PLL Reference Clock > 43 CPU_VDD1_RUN_FB_H CPU_VDD1_RUN_FB_H Y6 H6 CPU_VDDNB_RUN_FB_H < Differential feedback for VDDNB >
VDD1_FB_H VDDNB_FB_H CPU_VDDNB_RUN_FB_H 43
C20 43 CPU_VDD1_RUN_FB_L CPU_VDD1_RUN_FB_L AB6 G6 CPU_VDDNB_RUN_FB_L < Northbridge power supply >
VDD1_FB_L VDDNB_FB_L CPU_VDDNB_RUN_FB_L 43
1 2 3900P_0402_50V7K CPU_CLKIN_SC_P
16 CLK_CPU_BCLK < Debug ready >
T9 PAD G10 DBRDY
AA9 E10 CPU_DBREQ# < Debug request >
T10 PAD TMS DBREQ_L
1 < JTAG debug port >
T11 PAD AC9 TCK
R8 AD9 AE9
T12 PAD TRST_L TDO PAD T20
T19 PAD AF9 TDI
169_0402_1%
CPU_TEST23_TSTUPD AD7 J7 CPU_TEST28_H_PLLCHRZ_P route as differential
PAD T5
2

C21 TEST23 TEST28_H CPU_TEST28_L_PLLCHRZ_N as short as possible

TEST28_L H8 PAD T6
1 2 3900P_0402_50V7K CPU_CLKIN_SC_N H10 testpoint under package
16 CLK_CPU_BCLK# TEST18
G9 D7 CPU_TEST17_BP3
TEST19 TEST17 PAD T7
Address:100_1100 Place close to CPU wihtin 1.5" E7 CPU_TEST16_BP2
TEST16 PAD T8
CPU_TEST25_H_BYPASSCLK_H E9 F7
CPU_TEST25_L_BYPASSCLK_L TEST25_H TEST15
E8 TEST25_L TEST14 C7

< Filtered PLL Supply Voltage > CPU_TEST21_SCANEN AB8 C3 @R32

@ R32
CPU_TEST20_SCANCLK2 TEST21 TEST7 CPU_TEST10_ANALOGOUT 2
AF7 TEST20 TEST10 K8 1 300_0402_5% +1.2V_HT
CPU_TEST24_SCANCLK1 AE7
+2.5VS +2.5VDDA TEST24
AE8 TEST22 TEST8 C4 Add R32 at PVT
VDDA=300mA AC8 TEST12
L1 1 2 FBM_L11_201209_300L_0805 +2.5VDDA AF8 TEST27 CPU_TEST29_H_FBCLKOUT_P
1 1 1 1 TEST29_H C9 PAD T13
2 C17 C18 C19 CPU_TEST29_L_FBCLKOUT_N 2
1 2 R25 C2 TEST9 TEST29_L C8 PAD T14
@ + C16 0_0402_5% AA6
4.7U_0805_10V4Z 3300P_0402_50V7K 0.22U_0603_16V4Z TEST6
100U_D2_10VM 2 2 2
A3 RSVD1 RSVD10 H18
2
A5 RSVD2 RSVD9 H19
B3 RSVD3 RSVD8 AA7
B5 RSVD4 RSVD7 D5
C1 RSVD5 RSVD6 C5

< Serial VID Interface clock & data >

@ 6090022100G_B
+1.8VS 0718 AMD --> 1K ohm
R22
2 1 1K_0402_5% CPU_SVC

R23 < HDT Connector >

2 1 1K_0402_5% CPU_SVD
< R41 Close to CPU > < R494 Close to CPU > JP3

CPU_DBREQ# 1 2
+1.8VS @ R494 3 4
R41 5 6
+1.8V 1 2 300_0402_5% 1 2 0_0402_5% 7 8
T23 PAD 9 10
2

@ R40 1 2 220_0402_5%
R15 @ R39 220_0402_5% 11 12
1 2 13 14
@ R38 1 2 220_0402_5%
300_0402_5% @ R37 220_0402_5% 15 16
+1.8V 1 2 17 18
T24 PAD
1

LDT_RST# 19 20
20 LDT_RST# 21 22
1 +1.8V LDT_RST#
C22 23 24
3 @
Add R497 and R500 for Caspian +1.8V 26 3
0.01U_0402_25V7K
2 R497 R498 @ SAMTEC_ASP-68200-07
1 2 510_0402_5% CPU_TEST25_H_BYPASSCLK_H @ 1 2 510_0402_5%
NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.
+1.8VS +1.8VS
R499 R500
@ 1 2 510_0402_5% CPU_TEST25_L_BYPASSCLK_L 1 2 510_0402_5%
2

R21 R36

300_0402_5% 300_0402_5%
1

H_PWRGD LDT_STOP# R10 @ D12 < To power circuitry>

20,43 H_PWRGD
1
12,20 LDT_STOP#
1 +1.8V 1 2 10K_0402_5% 1 2 CH751H-40PT_SOD323-2 +3VS < Thermal Sensor >
ENTRIP2 38,40
C23 C25 U2 < From EC >
@ @ D20 < To power circuitry> 1 8 EC_SMB_CK2 EC_SMB_CK2 34,35
0.1U_0402_16V7K 0.01U_0402_25V7K R5 VDD SCLK
1 2 CH751H-40PT_SOD323-2 EN0 37,40 1
2 2 300_0402_5% C26 THERMDA_CPU EC_SMB_DA2
1 2 2 D+ SDATA 7 EC_SMB_DA2 34,35
2
B

Q3
D16 < To SB710 ACPI block> 0.1U_0402_16V7K 1 2 C27 THERMDC_CPU 3 6
+1.8VS 2 D- ALERT#
E

CPU_THERMTRIP#_R 3 1 1 2 CH751H-40PT_SOD323-2 2200P_0402_50V7K

H_THERMTRIP# 21
C

4 THERM# GND 5
MMBT3904_NL_SOT23-3 < noise filter cap >
2

R30 ADM1032ARM-1 ZREEL_MSOP8

300_0402_5% Add R29 and R31 for Caspian < Differential feedback for VDDNB >
@ R27
@R27
1

CPU_LDT_REQ# 1 2 0_0402_5% CPU_LDT_REQ_R# R31 Close to CPU

12,20 CPU_LDT_REQ# +VDDNB
1 2 1 300_0402_5% CPU_TEST20_SCANCLK2
C24 Un-Mount R27 For Caspian R484
4 @ 4
2 1 10_0402_5% CPU_VDDNB_RUN_FB_H
0.01U_0402_25V7K R29
2
1 2 300_0402_5% CPU_TEST23_TSTUPD R485
2 1 10_0402_5% CPU_VDDNB_RUN_FB_L

R26
2 1 300_0402_5% CPU_TEST21_SCANEN

R9 Security Classification Compal Secret Data Compal Electronics, Inc.

+1.8V 1 2 300_0402_5% R28 Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
< To SB700 CPU block> 1 2 300_0402_5% CPU_TEST24_SCANCLK1
@ R11
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
CPU_PROCHOT#_1.8 1 2 0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
H_PROCHOT# 20
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 7 of 45
A B C D E
 A B C D E

+CPU_CORE_0 JCPUE +CPU_CORE_1

VDD decoupling : +CPU_CORE G4 P8
VDD0_1 VDD1_1
H2 VDD0_2 VDD1_2 P10
+CPU_CORE_0 +CPU_CORE_0 +CPU_CORE_0 J9 R4
VDD0_3 VDD1_3
J11 VDD0_4 VDD1_4 R7
J13 VDD0_5 VDD1_5 R9
1 1 1 1 1 1 1 1 1 J15 VDD0_6 VDD1_6 R11
C32 C33 C34 C35 C40 C41 C42 K6 T2
+ C30 + C28 VDD0_7 VDD1_7
K10 VDD0_8 VDD1_8 T6
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0603_16V4Z 0.01U_0402_25V7K 180P_0402_50V8J K12 T8
330U_X_2VM_R6M 330U_X_2VM_R6M 2 2 2 2 2 2 2 VDD0_9 VDD1_9
K14 VDD0_10 VDD1_10 T10
2 2
L4 VDD0_11 VDD1_11 T12
Near CPU Socket Under CPU Socket Under CPU Socket L7 VDD0_12 VDD1_12 T14
L9 VDD0_13 VDD1_13 U7
1 1
L11 VDD0_14 VDD1_14 U9
L13 VDD0_15 VDD1_15 U11
+CPU_CORE_1 +CPU_CORE_1 +CPU_CORE_1 L15 U13
VDD0_16 VDD1_16
M2 VDD0_17 VDD1_17 U15
M6 VDD0_18 VDD1_18 V6
1 1 1 1 1 1 1 1 1 M8 VDD0_19 VDD1_19 V8
C36 C37 C38 C39 C43 C44 C45 M10 V10
+ C31 + C29 VDD0_20 VDD1_20
N7 VDD0_21 VDD1_21 V12
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0603_16V4Z 0.01U_0402_25V7K 180P_0402_50V8J N9 V14
330U_X_2VM_R6M 330U_X_2VM_R6M 2 2 2 2 2 2 2 +VDDNB VDD0_22 VDD1_22
N11 VDD0_23 VDD1_23 W4
2 2
VDD1_24 Y2
Near CPU Socket Under CPU Socket Under CPU Socket K16 VDDNB_1 VDD1_25 AC4
M16 AD2 +1.8V
VDDNB_2 VDD1_26
P16 VDDNB_3
T16 VDDNB_4 VDDIO27 Y25
+1.8V V16 V25
VDDNB_5 VDDIO26
VDDIO decoupling : DDR SDRAM I/O ring power H25
VDDIO25 V23
V21
+1.8V VDDIO1 VDDIO24
J17 VDDIO2 VDDIO23 V18
K18 VDDIO3 VDDIO22 U17
K21 VDDIO4 VDDIO21 T25
1 1 1 1 1 1 K23 VDDIO5 VDDIO20 T23
C46 C47 C48 C49 C50 C51 K25 T21
VDDIO6 VDDIO19
L17 VDDIO7 VDDIO18 T18
22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J M18 R17
2 2 2 2 2 2 VDDIO8 VDDIO17
M21 VDDIO9 VDDIO16 P25
Under CPU Socket M23 VDDIO10 VDDIO15 P23
M25 VDDIO11 VDDIO14 P21
N17 VDDIO12 VDDIO13 P18
+1.8V

@ 6090022100G_B Athlon 64 S1 Processor Socket

2 2
1 1 1 1
C55 C56 C57 C58
JCPUF
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z AA4 J6
2 2 2 2 VSS1 VSS66
AA11 VSS2 VSS67 J8
Between CPU Socket and DIMM AA13 VSS3 VSS68 J10
AA15 VSS4 VSS69 J12
AA17 VSS5 VSS70 J14
+1.8V AA19 J16
VSS6 VSS71
AB2 VSS7 VSS72 J18
AB7 VSS8 VSS73 K2
1 1 AB9 VSS9 VSS74 K7
C60 C61 AB23 K9
VSS10 VSS75
AB25 VSS11 VSS76 K11
0.01U_0402_25V7K 0.01U_0402_25V7K AC11 K13
2 2 VSS12 VSS77
AC13 VSS13 VSS78 K15
Between CPU Socket and DIMM AC15 VSS14 VSS79 K17
AC17 VSS15 VSS80 L6
AC19 VSS16 VSS81 L8
AC21 VSS17 VSS82 L10
+1.8V AD6 L12
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch> VSS18 VSS83
AD8 VSS19 VSS84 L14
AD25 VSS20 VSS85 L16
1 1 1 1 AE11 VSS21 VSS86 L18
C62 C63 C64 C65 AE13 M7
VSS22 VSS87
AE15 VSS23 VSS88 M9
180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J AE17 AC6
2 2 2 2 VSS24 VSS89
AE19 VSS25 VSS90 M17
Between CPU Socket and DIMM AE21 VSS26 VSS91 N4
AE23 VSS27 VSS92 N8
B4 VSS28 VSS93 N10
+1.8V Change to B2 size B6 N16
3 VSS29 VSS94 3
B8 VSS30 VSS95 N18
1 B9 VSS31 VSS96 P2
1 1 1 1 B11 VSS32 VSS97 P7
C74 C75 C76 C77 @ + C78 B13 P9
VSS33 VSS98
220U_B2_4VM_R45M B15 VSS34 VSS99 P11
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z B17 P17
2 2 2 2 2 VSS35 VSS100
B19 VSS36 VSS101 R8
Between CPU Socket and DIMM B21 VSS37 VSS102 R10
B23 VSS38 VSS103 R16
B25 VSS39 VSS104 R18
D6 VSS40 VSS105 T7
D8 VSS41 VSS106 T9
+0.9V
VTT decoupling. D9
D11
VSS42 VSS107 T11
T13
VSS43 VSS108
D13 VSS44 VSS109 T15
1 1 1 1 1 1 1 1 D15 VSS45 VSS110 T17
C66 C67 C68 C69 C70 C71 C72 C73 D17 U4
VSS46 VSS111
D19 VSS47 VSS112 U6
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J +0.9V D21 U8
2 2 2 2 2 2 2 2 VSS48 VSS113
1. Near Power Supply D23 VSS49 VSS114 U10
Near CPU Socket Right side 1 2. Change to B2 size D25 VSS50 VSS115 U12
+0.9V E4 U14
+ C59 VSS51 VSS116
F2 VSS52 VSS117 U16
220U_B2_4VM_R45M F11 VSS53 VSS118 U18
1 1 1 1 1 1 1 1 F13 VSS54 VSS119 V2
C79 C80 C81 C82 C83 C84 C85 C86 2
F15 VSS55 VSS120 V7
F17 VSS56 VSS121 V9
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 180P_0402_50V8J 180P_0402_50V8J F19 V11
2 2 2 2 2 2 2 2 VSS57 VSS122
F21 VSS58 VSS123 V13
Near CPU Socket Left side F23 VSS59 VSS124 V15
F25 VSS60 VSS125 V17
H7 VSS61 VSS126 W6
4 4
H9 VSS62 VSS127 Y21
H21 VSS63 VSS128 Y23
+VDDNB decoupling : Northbridge power Add 22uF for Caspaian H23
J4
VSS64 VSS129 N6
+VDDNB VSS65
@ 6090022100G_B Athlon 64 S1 Processor Socket
1 1 1
C52 C53 C54 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 8 of 45
A B C D E
 A B C D E

+1.8V +1.8V

< EMI require > < EMI require >

0.1U_0402_16V7K 1 2 C160 C155 2 1 0.1U_0402_16V7K
+0.9V +1.8V
JDDRH RP8
1 2 DDR_B_MA4 1 8 C105 2 1 0.1U_0402_16V7K
10 +V_DDR_MCH_REF VREF VSS
1 3 4 DDR_B_D4 DDR_B_MA2 2 7
C104 DDR_B_D0 VSS DQ4 DDR_B_D5 DDR_B_MA0 C106 2
5 DQ0 DQ5 6 3 6 1 0.1U_0402_16V7K
1 DDR_B_D1 DDR_B_RAS# 1
7 DQ1 VSS 8 4 5
1000P_0402_50V7K 9 10 DDR_B_DM0
2 DDR_B_DQS#0 VSS DM0 47_0804_8P4R_5%
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7 RP9
15 VSS DQ7 16
DDR_B_D2 17 18 DDR_B_MA14 1 8 C108 2 1 0.1U_0402_16V7K
DDR_B_D3 DQ2 VSS DDR_B_D12 DDR_B_MA11
19 DQ3 DQ12 20 2 7
21 22 DDR_B_D13 DDR_B_MA7 3 6 C107 2 1 0.1U_0402_16V7K
DDR_B_D8 VSS DQ13 DDR_B_MA6
23 DQ8 VSS 24 4 5
DDR_B_D9 25 26 DDR_B_DM1
DQ9 DM1 47_0804_8P4R_5%
27 VSS VSS 28
DDR_B_DQS#1 29 30
DQS1# CK0 DDR_B_CLK0 6
DDR_B_DQS1 31 32 RP10
DQS1 CK0# DDR_B_CLK#0 6
33 34 DDR_CKE0_DIMMB 8 1 C109 2 1 0.1U_0402_16V7K
DDR_B_D10 VSS VSS DDR_B_D14 DDR_B_BS#2
35 DQ10 DQ14 36 7 2
DDR_B_D11 37 38 DDR_B_D15 DDR_B_MA15 6 3 C110 2 1 0.1U_0402_16V7K
DQ11 DQ15 DDR_CKE1_DIMMB
39 VSS VSS 40 5 4

47_0804_8P4R_5%
41 VSS VSS 42
DDR_B_D16 43 44 DDR_B_D20 RP11
DDR_B_D17 DQ16 DQ20 DDR_B_D21 DDR_B_MA3 C111 2
45 DQ17 DQ21 46 8 1 1 0.1U_0402_16V7K
47 48 DDR_B_MA8 7 2
DDR_B_DQS#2 VSS VSS DDR_B_MA12 C112 2
49 DQS2# NC 50 6 3 1 0.1U_0402_16V7K
DDR_B_DQS2 51 52 DDR_B_DM2 DDR_B_MA9 5 4
DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22 47_0804_8P4R_5%
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
59 60 RP12
DDR_B_D24 VSS VSS DDR_B_D28 DDR_B_BS#0 C114 2
61 DQ24 DQ28 62 8 1 1 0.1U_0402_16V7K
DDR_B_D25 63 64 DDR_B_D29 DDR_B_MA10 7 2
DQ25 DQ29 DDR_B_MA1 C113 2
65 VSS VSS 66 6 3 1 0.1U_0402_16V7K
2 DDR_B_DM3 DDR_B_DQS#3 DDR_B_MA5 2
67 DM3 DQS3# 68 5 4
69 70 DDR_B_DQS3
NC DQS3 47_0804_8P4R_5%
71 VSS VSS 72
DDR_B_D26 73 74 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31 RP13
75 DQ27 DQ31 76
77 78 DDR_CS1_DIMMB# 8 1 C116 2 1 0.1U_0402_16V7K
DDR_CKE0_DIMMB VSS VSS DDR_CKE1_DIMMB DDR_B_ODT1
6 DDR_CKE0_DIMMB 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMB 6 7 2
81 82 DDR_B_CAS# 6 3 C115 2 1 0.1U_0402_16V7K
VDD VDD DDR_B_MA15 DDR_B_WE#
83 NC NC/A15 84 5 4
DDR_B_BS#2 85 86 DDR_B_MA14
6 DDR_B_BS#2 BA2 NC/A14
87 88 47_0804_8P4R_5%
DDR_B_MA12 VDD VDD DDR_B_MA11
89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7 RP14
DDR_B_MA8 A9 A7 DDR_B_MA6 DDR_B_BS#1 C118 2
93 A8 A6 94 1 8 1 0.1U_0402_16V7K
95 96 DDR_CS0_DIMMB# 2 7
DDR_B_MA5 VDD VDD DDR_B_MA4 DDR_B_MA13 C117 2
97 A5 A4 98 3 6 1 0.1U_0402_16V7K
DDR_B_MA3 99 100 DDR_B_MA2 DDR_B_ODT0 4 5
DDR_B_MA1 A3 A2 DDR_B_MA0
101 A1 A0 102
103 104 47_0804_8P4R_5%
DDR_B_MA10 VDD VDD DDR_B_BS#1
105 A10/AP BA1 106 DDR_B_BS#1 6
DDR_B_BS#0 107 108 DDR_B_RAS#
6 DDR_B_BS#0 BA0 RAS# DDR_B_RAS# 6
DDR_B_WE# 109 110 DDR_CS0_DIMMB#
6 DDR_B_WE# WE# S0# DDR_CS0_DIMMB# 6
111 VDD VDD 112
DDR_B_CAS# 113 114 DDR_B_ODT0
6 DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 6
DDR_CS1_DIMMB# 115 116 DDR_B_MA13
6 DDR_CS1_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
DDR_B_ODT1 119 120
6 DDR_B_ODT1 NC/ODT1 NC
121 VSS VSS 122
DDR_B_D32 123 124 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_B_DQS#4 129 130 DDR_B_DM4
3 DDR_B_DQS4 DQS4# DM4 3
131 DQS4 VSS 132
133 134 DDR_B_D38
DDR_B_D34 VSS DQ38 DDR_B_D39
135 DQ34 DQ39 136
DDR_B_D35 137 138 DDR_B_D[0..63]
DQ35 VSS DDR_B_D44 DDR_B_D[0..63] 6
139 VSS DQ44 140
DDR_B_D40 141 142 DDR_B_D45 DDR_B_DM[0..7]
DQ40 DQ45 DDR_B_DM[0..7] 6
DDR_B_D41 143 144
DQ41 VSS DDR_B_DQS#5 DDR_B_DQS[0..7]
145 VSS DQS5# 146 DDR_B_DQS[0..7] 6
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5 DDR_B_MA[0..15]
149 VSS VSS 150 DDR_B_MA[0..15] 6
DDR_B_D42 151 152 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47 DDR_B_DQS#[0..7]
153 DQ43 DQ47 154 DDR_B_DQS#[0..7] 6
155 VSS VSS 156
DDR_B_D48 157 158 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 NC,TEST CK1 164 DDR_B_CLK1 6
165 VSS CK1# 166 DDR_B_CLK#1 6
DDR_B_DQS#6 167 168
DDR_B_DQS6 DQS6# VSS DDR_B_DM6
169 DQS6 DM6 170
171 VSS VSS 172
DDR_B_D50 173 174 DDR_B_D54
DDR_B_D51 DQ50 DQ54 DDR_B_D55
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_B_D56 179 180 DDR_B_D60
DDR_B_D57 DQ56 DQ60 DDR_B_D61
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_B_DM7 185 186 DDR_B_DQS#7
DM7 DQS7# DDR_B_DQS7
187 VSS DQS7 188
DDR_B_D58 189 190
DDR_B_D59 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
193 194 DDR_B_D63
4 VSS DQ63 4
10,16,21,27 SMB_CK_DAT0 195 SDA VSS 196
10,16,21,27 SMB_CK_CLK0 197 SCL SAO 198 +3VS
+3VS 199 VDDSPD SA1 200
1 201 VSS VSS 202
C119
@ P-TWO_A5692B-A0G16-P
0.1U_0402_16V7K
2
DIMM0 STD H:9.2mm (Bot) Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 9 of 45
A B C D E
 A B C D E

+1.8V

2
R43
1K_0402_1%

1
+V_DDR_MCH_REF
9 +V_DDR_MCH_REF
1 1

2
C96 C95
R44
1K_0402_1% 0.1U_0402_16V7K 1000P_0402_50V7K DDR_A_D[0..63]
2 2 DDR_A_D[0..63] 6
DDR_A_DM[0..7]
DDR_A_DM[0..7] 6
1
1 < EMI require > +1.8V +1.8V < EMI require > 1
DDR_A_DQS[0..7]
0.1U_0402_16V7K DDR_A_DQS[0..7] 6
1 2 C193 JDDRL C161 2 1 0.1U_0402_16V7K
1 2 DDR_A_MA[0..15]
VREF VSS DDR_A_MA[0..15] 6
3 4 DDR_A_D4
DDR_A_D0 VSS DQ4 DDR_A_D5 DDR_A_DQS#[0..7]
5 DQ0 DQ5 6 DDR_A_DQS#[0..7] 6
DDR_A_D1 7 8
DQ1 VSS DDR_A_DM0
9 VSS DM0 10
DDR_A_DQS#0 11 12
DDR_A_DQS0 DQS0# VSS DDR_A_D6
13 DQS0 DQ6 14
15 16 DDR_A_D7
DDR_A_D2 VSS DQ7
17 DQ2 VSS 18
DDR_A_D3 19 20 DDR_A_D12
DQ3 DQ12 DDR_A_D13
21 VSS DQ13 22
DDR_A_D8 23 24
DDR_A_D9 DQ8 VSS DDR_A_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_A_DQS#1 29 30 +0.9V +1.8V
DQS1# CK0 DDR_A_CLK0 6
DDR_A_DQS1 31 32 RP1
DQS1 CK0# DDR_A_CLK#0 6
33 34 DDR_A_MA6 1 8 C87 1 2 0.1U_0402_16V7K
DDR_A_D10 VSS VSS DDR_A_D14 DDR_A_MA14
35 DQ10 DQ14 36 2 7
DDR_A_D11 37 38 DDR_A_D15 DDR_A_MA7 3 6 C88 1 2 0.1U_0402_16V7K
DQ11 DQ15 DDR_A_MA11
39 VSS VSS 40 4 5

47_0804_8P4R_5%
41 42 RP2
DDR_A_D16 VSS VSS DDR_A_D20 DDR_CKE0_DIMMA C90
43 DQ16 DQ20 44 8 1 1 2 0.1U_0402_16V7K
DDR_A_D17 45 46 DDR_A_D21 DDR_A_BS#2 7 2
DQ17 DQ21 DDR_CKE1_DIMMA C89
47 VSS VSS 48 6 3 1 2 0.1U_0402_16V7K
DDR_A_DQS#2 49 50 DDR_A_MA15 5 4
DDR_A_DQS2 DQS2# NC DDR_A_DM2
51 DQS2 DM2 52
53 54 47_0804_8P4R_5%
2 DDR_A_D18 VSS VSS DDR_A_D22 RP3 2
55 DQ18 DQ22 56
DDR_A_D19 57 58 DDR_A_D23 DDR_A_BS#1 1 8 C91 1 2 0.1U_0402_16V7K
DQ19 DQ23 DDR_A_MA2
59 VSS VSS 60 2 7
DDR_A_D24 61 62 DDR_A_D28 DDR_A_MA0 3 6 C92 1 2 0.1U_0402_16V7K
DDR_A_D25 DQ24 DQ28 DDR_A_D29 DDR_A_MA4
63 DQ25 DQ29 64 4 5
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3 47_0804_8P4R_5%
DM3 DQS3# DDR_A_DQS3 RP4
69 NC DQS3 70
71 72 DDR_A_MA5 8 1 C93 1 2 0.1U_0402_16V7K
DDR_A_D26 VSS VSS DDR_A_D30 DDR_A_MA8
73 DQ26 DQ30 74 7 2
DDR_A_D27 75 76 DDR_A_D31 DDR_A_MA9 6 3 C94 1 2 0.1U_0402_16V7K
DQ27 DQ31 DDR_A_MA12
77 VSS VSS 78 5 4
DDR_CKE0_DIMMA 79 80 DDR_CKE1_DIMMA
6 DDR_CKE0_DIMMA CKE0 NC/CKE1 DDR_CKE1_DIMMA 6
81 82 47_0804_8P4R_5%
VDD VDD DDR_A_MA15 RP5
83 NC NC/A15 84
DDR_A_BS#2 85 86 DDR_A_MA14 DDR_A_BS#0 8 1 C98 1 2 0.1U_0402_16V7K
6 DDR_A_BS#2 BA2 NC/A14
87 88 DDR_A_MA10 7 2
DDR_A_MA12 VDD VDD DDR_A_MA11 DDR_A_MA3 C97
89 A12 A11 90 6 3 1 2 0.1U_0402_16V7K
DDR_A_MA9 91 92 DDR_A_MA7 DDR_A_MA1 5 4
DDR_A_MA8 A9 A7 DDR_A_MA6
93 A8 A6 94
95 96 47_0804_8P4R_5%
DDR_A_MA5 VDD VDD DDR_A_MA4 RP6
97 A5 A4 98
DDR_A_MA3 99 100 DDR_A_MA2 DDR_A_ODT1 8 1 C100 1 2 0.1U_0402_16V7K
DDR_A_MA1 A3 A2 DDR_A_MA0 DDR_CS1_DIMMA#
101 A1 A0 102 7 2
103 104 DDR_A_CAS# 6 3 C99 1 2 0.1U_0402_16V7K
DDR_A_MA10 VDD VDD DDR_A_BS#1 DDR_A_WE#
105 A10/AP BA1 106 DDR_A_BS#1 6 5 4
DDR_A_BS#0 107 108 DDR_A_RAS#
6 DDR_A_BS#0 BA0 RAS# DDR_A_RAS# 6
DDR_A_WE# 109 110 DDR_CS0_DIMMA# 47_0804_8P4R_5%
6 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 6
111 112 RP7
DDR_A_CAS# VDD VDD DDR_A_ODT0 DDR_A_MA13 C102 1
6 DDR_A_CAS# 113 CAS# ODT0 114 DDR_A_ODT0 6 1 8 2 0.1U_0402_16V7K
DDR_CS1_DIMMA# 115 116 DDR_A_MA13 DDR_A_ODT0 2 7
6 DDR_CS1_DIMMA# NC/S1# NC/A13
117 118 DDR_A_RAS# 3 6 C101 1 2 0.1U_0402_16V7K
3 DDR_A_ODT1 VDD VDD DDR_CS0_DIMMA# 3
6 DDR_A_ODT1 119 NC/ODT1 NC 120 4 5
121 VSS VSS 122
DDR_A_D32 123 124 DDR_A_D36 47_0804_8P4R_5%
DDR_A_D33 DQ32 DQ36 DDR_A_D37
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_A_D38
DDR_A_D34 VSS DQ38 DDR_A_D39
135 DQ34 DQ39 136
DDR_A_D35 137 138
DQ35 VSS DDR_A_D44
139 VSS DQ44 140
DDR_A_D40 141 142 DDR_A_D45
DDR_A_D41 DQ40 DQ45
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D42 151 152 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D48 157 158 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
159 DQ49 DQ53 160
161 VSS VSS 162
163 NC,TEST CK1 164 DDR_A_CLK1 6
165 VSS CK1# 166 DDR_A_CLK#1 6
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 VSS VSS 172
DDR_A_D50 173 174 DDR_A_D54
DDR_A_D51 DQ50 DQ54 DDR_A_D55
175 DQ51 DQ55 176
177 VSS VSS 178
DDR_A_D56 179 180 DDR_A_D60
DDR_A_D57 DQ56 DQ60 DDR_A_D61
181 DQ57 DQ61 182
4 4
183 VSS VSS 184
DDR_A_DM7 185 186 DDR_A_DQS#7
DM7 DQS7# DDR_A_DQS7
187 VSS DQS7 188
DDR_A_D58 189 190
DDR_A_D59 DQ58 VSS DDR_A_D62
191 DQ59 DQ62 192
193 194 DDR_A_D63
VSS DQ63
9,16,21,27 SMB_CK_DAT0 195 SDA VSS 196
197 198
9,16,21,27 SMB_CK_CLK0
+3VS 199
SCL
VDDSPD
SAO
SA1 200
Security Classification Compal Secret Data Compal Electronics, Inc.
1 203 VSS VSS 204 Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
C103
@ PTI_A5652D-A0G16-P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
0.1U_0402_16V7K AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2 Custom C
DIMM0 STD H:5.2mm (Bot) DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 401721
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 10 of 45
A B C D E
 A B C D E

U3B
D4 GFX_RX0P GFX_TX0P A5 HDMI_TXD2+ 19
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5 HDMI_TXD2- 19
A3 GFX_RX1P GFX_TX1P A4 HDMI_TXD1+ 19
B3 GFX_RX1N GFX_TX1N B4 HDMI_TXD1- 19
C2 GFX_RX2P GFX_TX2P C3 HDMI_TXD0+ 19
C1 GFX_RX2N GFX_TX2N B2 HDMI_TXD0- 19
E5 GFX_RX3P GFX_TX3P D1 HDMI_CLK0+ 19
F5 GFX_RX3N GFX_TX3N D2 HDMI_CLK0- 19
G5 GFX_RX4P GFX_TX4P E2
G6 GFX_RX4N GFX_TX4N E1
H5 GFX_RX5P GFX_TX5P F4
H6 GFX_RX5N GFX_TX5N F3
J6 GFX_RX6P GFX_TX6P F1
1 1
J5 GFX_RX6N GFX_TX6N F2 < If integrated GFX is used, some PCIE pairs are used as HDMI signal pairs >
J7 GFX_RX7P GFX_TX7P H4
J8 H3 RS880M Display Port Support (muxed on GFX)
GFX_RX7N GFX_TX7N
L5 GFX_RX8P GFX_TX8P H1
L6 GFX_RX8N GFX_TX8N H2
M8 J2 DP0 GFX_TX0,TX1,TX2 and TX3 AUX0 and HPD0
GFX_RX9P GFX_TX9P
L8 GFX_RX9N GFX_TX9N J1
P7

PCIE I/F GFX

GFX_RX10P GFX_TX10P K4
M7 K3 DP1 GFX_TX4,TX5,TX6 and TX7 AUX1 and HPD1
GFX_RX10N GFX_TX10N
P5 GFX_RX11P GFX_TX11P K1
M5 GFX_RX11N GFX_TX11N K2
R8 GFX_RX12P GFX_TX12P M4
P8 GFX_RX12N GFX_TX12N M3
R6 GFX_RX13P GFX_TX13P M1
R5 GFX_RX13N GFX_TX13N M2
P4 GFX_RX14P GFX_TX14P N2
P3 GFX_RX14N GFX_TX14N N1
T4 GFX_RX15P GFX_TX15P P1
T3 GFX_RX15N GFX_TX15N P2

AE3 AC1 PCIE_ITX_PRX_P0 C152 1 2 0.1U_0402_16V7K

27 PCIE_PTX_C_IRX_P0 GPP_RX0P GPP_TX0P PCIE_ITX_C_PRX_P0 27
< To New Card > AD4 AC2 PCIE_ITX_PRX_N0 C153 1 2 0.1U_0402_16V7K < To New Card >
27 PCIE_PTX_C_IRX_N0 GPP_RX0N GPP_TX0N PCIE_ITX_C_PRX_N0 27
AE2 GPP_RX1P GPP_TX1P AB4
AD3 GPP_RX1N GPP_TX1N AB3
AD1 AA2 PCIE_ITX_PRX_P2 WLAN@ C156 1 2 0.1U_0402_16V7K
27 PCIE_PTX_C_IRX_P2 GPP_RX2P GPP_TX2P PCIE_ITX_C_PRX_P2 27
< To WLAN > AD2 PCIE I/F GPP AA1 PCIE_ITX_PRX_N2 WLAN@ C157 1 2 0.1U_0402_16V7K < To WLAN >
27 PCIE_PTX_C_IRX_N2 GPP_RX2N GPP_TX2N PCIE_ITX_C_PRX_N2 27
V5 Y1 PCIE_ITX_PRX_P3 C158 1 2 0.1U_0402_16V7K
26 PCIE_PTX_C_IRX_P3 GPP_RX3P GPP_TX3P PCIE_ITX_C_PRX_P3 26
< To LAN > W6 Y2 PCIE_ITX_PRX_N3 C159 1 2 0.1U_0402_16V7K < To LAN >
26 PCIE_PTX_C_IRX_N3 GPP_RX3N GPP_TX3N PCIE_ITX_C_PRX_N3 26
U5 GPP_RX4P GPP_TX4P Y4
U6 GPP_RX4N GPP_TX4N Y3
U8 GPP_RX5P GPP_TX5P V1
U7 GPP_RX5N GPP_TX5N V2
2 2

20 SB_RX0P AA8 AD7 SB_TX0P_C C162 1 2 0.1U_0402_16V7K

SB_RX0P SB_TX0P SB_TX0P 20
20 SB_RX0N Y8 AE7 SB_TX0N_C C163 1 2 0.1U_0402_16V7K
SB_RX0N SB_TX0N SB_TX0N 20
< From SB710 : x4 PCIE A-link > 20 SB_RX1P AA7 AE6 SB_TX1P_C C164 1 2 0.1U_0402_16V7K
SB_RX1P SB_TX1P SB_TX1P 20
20 SB_RX1N Y7 AD6 SB_TX1N_C C165 1 2 0.1U_0402_16V7K < To SB710 : x4 PCEI A-link>
SB_RX1N SB_TX1N SB_TX1N 20
20 SB_RX2P AA5 PCIE I/F SB AB6 SB_TX2P_C C166 1 2 0.1U_0402_16V7K
SB_RX2P SB_TX2P SB_TX2P 20
20 SB_RX2N AA6 AC6 SB_TX2N_C C168 1 2 0.1U_0402_16V7K
SB_RX2N SB_TX2N SB_TX2N 20
20 SB_RX3P W5 AD5 SB_TX3P_C C169 1 2 0.1U_0402_16V7K
SB_RX3P SB_TX3P SB_TX3P 20
20 SB_RX3N Y5 AE5 SB_TX3N_C C167 1 2 0.1U_0402_16V7K
SB_RX3N SB_TX3N SB_TX3N 20
AC8 PCIE_CALRP R55 1 2 1.27K_0402_1% < TX Impedance Calibration. Connect to GND >
PCE_CALRP(PCE_BCALRP) PCIE_CALRN R56 2K_0402_1% < RX Impedance Calibration. Connect to VDDPCIE >
PCE_CALRN(PCE_BCALRN) AB8 1 2 +1.1VS

RS880MR1@ RS780M_FCBGA528
U3A
H_CADOP[0..15] H_CADOP0 Y25 D24 H_CADIP0 H_CADIP[0..15]
H_CADOP[0..15] 5 HT_RXCAD0P HT_TXCAD0P H_CADIP[0..15] 5
H_CADON0 Y24 PART 1 OF 6 D25 H_CADIN0
H_CADON[0..15] H_CADOP1 HT_RXCAD0N HT_TXCAD0N H_CADIP1 H_CADIN[0..15]
H_CADON[0..15] 5 V22 HT_RXCAD1P HT_TXCAD1P E24 H_CADIN[0..15] 5
H_CADON1 V23 E25 H_CADIN1
H_CADOP2 HT_RXCAD1N HT_TXCAD1N H_CADIP2
V25 HT_RXCAD2P HT_TXCAD2P F24
H_CADON2 V24 F25 H_CADIN2
H_CADOP3 HT_RXCAD2N HT_TXCAD2N H_CADIP3
U24 HT_RXCAD3P HT_TXCAD3P F23
H_CADON3 U25 F22 H_CADIN3
H_CADOP4 HT_RXCAD3N HT_TXCAD3N H_CADIP4
T25 HT_RXCAD4P HT_TXCAD4P H23
H_CADON4 T24 H22 H_CADIN4
H_CADOP5 HT_RXCAD4N HT_TXCAD4N H_CADIP5
P22 HT_RXCAD5P HT_TXCAD5P J25
HYPER TRANSPORT CPU I/F

H_CADON5 P23 J24 H_CADIN5

H_CADOP6 HT_RXCAD5N HT_TXCAD5N H_CADIP6
P25 HT_RXCAD6P HT_TXCAD6P K24
H_CADON6 P24 K25 H_CADIN6
H_CADOP7 HT_RXCAD6N HT_TXCAD6N H_CADIP7
N24 HT_RXCAD7P HT_TXCAD7P K23
H_CADON7 N25 K22 H_CADIN7
3 HT_RXCAD7N HT_TXCAD7N 3
< From S1G3 CPU : x16 HT> < To S1G3 CPU : x16 HT>
H_CADOP8 AC24 F21 H_CADIP8
H_CADON8 HT_RXCAD8P HT_TXCAD8P H_CADIN8
AC25 HT_RXCAD8N HT_TXCAD8N G21
H_CADOP9 AB25 G20 H_CADIP9
H_CADON9 HT_RXCAD9P HT_TXCAD9P H_CADIN9
AB24 HT_RXCAD9N HT_TXCAD9N H21
H_CADOP10 AA24 J20 H_CADIP10
H_CADON10 HT_RXCAD10P HT_TXCAD10P H_CADIN10
AA25 HT_RXCAD10N HT_TXCAD10N J21
H_CADOP11 Y22 J18 H_CADIP11
H_CADON11 HT_RXCAD11P HT_TXCAD11P H_CADIN11
Y23 HT_RXCAD11N HT_TXCAD11N K17
H_CADOP12 W21 L19 H_CADIP12
H_CADON12 HT_RXCAD12P HT_TXCAD12P H_CADIN12
W20 HT_RXCAD12N HT_TXCAD12N J19
H_CADOP13 V21 M19 H_CADIP13
H_CADON13 HT_RXCAD13P HT_TXCAD13P H_CADIN13
V20 HT_RXCAD13N HT_TXCAD13N L18
H_CADOP14 U20 M21 H_CADIP14
H_CADON14 HT_RXCAD14P HT_TXCAD14P H_CADIN14
U21 HT_RXCAD14N HT_TXCAD14N P21
H_CADOP15 U19 P18 H_CADIP15
H_CADON15 HT_RXCAD15P HT_TXCAD15P H_CADIN15
U18 HT_RXCAD15N HT_TXCAD15N M18

5 H_CLKOP0 T22 HT_RXCLK0P HT_TXCLK0P H24 H_CLKIP0 5

5 H_CLKON0 T23 HT_RXCLK0N HT_TXCLK0N H25 H_CLKIN0 5
5 H_CLKOP1 AB23 HT_RXCLK1P HT_TXCLK1P L21 H_CLKIP1 5
5 H_CLKON1 AA22 HT_RXCLK1N HT_TXCLK1N L20 H_CLKIN1 5
H_CTLOP0 M22 M24 H_CTLIP0
5 H_CTLOP0 HT_RXCTL0P HT_TXCTL0P H_CTLIP0 5
H_CTLON0 M23 M25 H_CTLIN0
5 H_CTLON0 HT_RXCTL0N HT_TXCTL0N H_CTLIN0 5
H_CTLOP1 R21 P19 H_CTLIP1
5 H_CTLOP1 HT_RXCTL1P HT_TXCTL1P H_CTLIP1 5
H_CTLON1 R20 R18 H_CTLIN1
5 H_CTLON1 HT_RXCTL1N HT_TXCTL1N H_CTLIN1 5
301_0402_1%1 2 R57 HT_RXCALP C23 B24 HT_TXCALP R58 1 2 301_0402_1% < Transmitter Calibration Resistor to HT_TXCALN >
HT_RXCALN HT_RXCALP HT_TXCALP HT_TXCALN
A24 HT_RXCALN HT_TXCALN B25

0718 Place within 1" 0718 Place within 1"

4 RS880MR1@ RS780M_FCBGA528 4
layout 1:2 layout 1:2
NEED CHECK R57 & R58 WITH AMD

/
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 11 of 45
A B C D E
 A B C D E

AVDD=100mA U3C
+AVDD1 F12 A22 UMA_LCD_TXOUT0_A0+ 18
AVDD1(NC) TXOUT_L0P(NC)
E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22 UMA_LCD_TXOUT0_A0- 18
+AVDD2 F14 A21 UMA_LCD_TXOUT0_A1+ 18
AVDDDI(NC) TXOUT_L1P(NC) < LVDS dual channel : channel 1 >
G15 AVSSDI(NC) TXOUT_L1N(NC) B21 UMA_LCD_TXOUT0_A1- 18
+AVDDQ H15 B20 UMA_LCD_TXOUT0_A2+ 18
AVDDQ(NC) TXOUT_L2P(NC)
H14 AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) A20 UMA_LCD_TXOUT0_A2- 18
TXOUT_L3P(NC) A19
E17 C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) B19

CRT/TVOUT
F17 Y(DFT_GPIO2)
F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18 UMA_LCD_TZOUT0_B0+ 18
TXOUT_U0N(NC) A18 UMA_LCD_TZOUT0_B0- 18
UMA_CRT_R G18 A17 UMA_LCD_TZOUT0_B1+ 18
17 UMA_CRT_R RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) < LVDS dual channel : channel 2 >
G17 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) B17 UMA_LCD_TZOUT0_B1- 18
UMA_CRT_G E18 D20 UMA_LCD_TZOUT0_B2+ 18
1 17 UMA_CRT_G GREEN(DFT_GPIO1) TXOUT_U2P(NC) 1
F18 GREENb(NC) TXOUT_U2N(NC) D21 UMA_LCD_TZOUT0_B2- 18
UMA_CRT_B E19 D18
17 UMA_CRT_B BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5)
F19 BLUEb(NC) TXOUT_U3N(NC) D19

UMA_CRT_HSYNC A11 B16 UMA_LCD_TXCLK_ACLK+ 18

15,17 UMA_CRT_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1)
UMA_CRT_VSYNC B11 A16 UMA_LCD_TXCLK_ACLK- 18
15,17 UMA_CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3)
17 UMA_CRT_CLK F8 DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4) D16 UMA_LCD_TZCLK_BCLK+ 18
17 UMA_CRT_DATA E8 DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) D17 UMA_LCD_TZCLK_BCLK- 18
R65 1 2 715_0402_1% G14
< DAC internal reference to set full scale DAC current > DAC_RSET(PWM_GPIO1) +VDDLTP18
VDDLTP18(NC) A13
+NB_PLLVDD +NB_PLLVDD A12 B13
+NB_HTPVDD D14 PLLVDD(NC) VSSLTP18(NC)
+NB_HTPVDD PLLVDD18(NC)
B12 A15 +VDDLT18

LVTM
PLLVSS(NC) VDDLT18_1(NC)
B15

PLL PWR
VDDLT18_2(NC)
+VDDA18HTPLL H17 VDDA18HTPLL VDDLT33_1(NC) A14
VDDLT33_2(NC) B14
+VDDA18PCIEPLL D7 VDDA18PCIEPLL1
E7 VDDA18PCIEPLL2 VSSLT1(VSS) C14
VSSLT2(VSS) D15
R67 1 2 0_0402_5% NB_RESET# D8 C16
+1.1VS 15,20,26,27,33,34 PLT_RST# SYSRESETb VSSLT3(VSS)
NB_PWRGD A10 C18
21 NB_PWRGD POWERGOOD VSSLT4(VSS)
7,20 LDT_STOP# C10 LDTSTOPb VSSLT5(VSS) C20
C12 E20

PM
7,20 CPU_LDT_REQ# ALLOW_LDTSTOP VSSLT6(VSS)
2

VSSLT7(VSS) C22
R71 C25
16 CLK_NBHT HT_REFCLKP
4.7K_0402_5% C24
16 CLK_NBHT# HT_REFCLKN

16 NB_OSC_14.318M E11
1

REFCLK_P/OSCIN(OSCIN)

CLOCKs
F11 E9 < LVDS digital power enable >
REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) UMA_ENVDD 18
LVDS_BLON(PCE_RCALRP) F7 UMA_ENBKL 34
1

T2 G12 < LVDS backlight enable >

2 16 NBGFX_CLK GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) 2
R72 T1
16 NBGFX_CLK# GFX_REFCLKN
4.7K_0402_5% PAD T17 R73
U1 GPP_REFCLKP 2 1 100K_0402_5%
U2
2

GPP_REFCLKN

16 CLK_SBLINK_BCLK V4 GPPSB_REFCLKP(SB_REFCLKP)
16 CLK_SBLINK_BCLK# V3 GPPSB_REFCLKN(SB_REFCLKN)

18 UMA_LCD_DDC_CLK B9 I2C_CLK < HDMI hot-plug detection >

18 UMA_LCD_DDC_DAT A9
B8
I2C_DATA MIS. TMDS_HPD(NC) D9
D10
HPD 19,21
19 HDMIDAT_UMA DDC_DATA0/AUX0N(NC) HPD(NC)
19 HDMICLK_UMA A8 DDC_CLK0/AUX0P(NC)
B7 D12 < Strap option pin or gate side-port memory IO >
DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5) SUS_STAT# 15,21
A7 DDC_DATA1/AUX1N(NC)
THERMALDIODE_P AE8
+3VS @R88
@ R88 2 1 10K_0402_5% B10 AD8
STRP_DATA THERMALDIODE_N
G11 D13 R80 1 2 1.8K_0402_5%
RSVD TESTMODE
Strap pin 15 AUX_CAL C8 AUX_CAL(NC)

RS880MR1@ RS780M_FCBGA528

< Dedicated power for the DAC which can affect display quality > < Dedicated power for the DAC which can affect display quality >
+1.8VS R371 1 2 300_0402_5% NB_PWRGD

RS780 use 140 ohm, check RS880 use what value

+3VS +1.8VS
L2 L4
1 2 BLM18PG121SN1D_0603 +AVDD1 0_0603_5% +AVDD2 R62 1 2 140_0402_1% UMA_CRT_R
3 3
1 1 1
C170 C172 C198
R63 1 2 150_0402_1% UMA_CRT_G
2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z 0.1U_0402_16V7K
2 2 2 R64 1 2 150_0402_1% UMA_CRT_B

< DAC Bandgap Reference Voltage >

< 1.8V power for system PLLs > < Power for integrated DVI/HDMI PLL macro >

+1.8VS
L6 +1.8VS +1.8VS
1 2 BLM18PG121SN1D_0603 +AVDDQ L7 +NB_HTPVDD L3
1 1 2 BLM18PG121SN1D_0603 2 1 BLM18PG121SN1D_0603 +VDDLTP18
C175 1 1
C176 C171
2.2U_0603_6.3V4Z
2 2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z
2 2

< IO power for HyperTransport PLL >

< 1.1V Power for system PLLs > < 1.8V IO power for the integrated DVI/HDMI interface >
+1.8VS +VDDA18HTPLL
L10
1 2 BLM18PG121SN1D_0603
+1.1VS +1.8VS
1
C179 L9 +NB_PLLVDD L5
1 2 BLM18PG121SN1D_0603 2 1 BLM18PG121SN1D_0603 +VDDLT18
2.2U_0603_6.3V4Z 1 1 1
4 2 C178 C174 C173 4
< 1.8V IO power for PCI-E PLLs >
2.2U_0603_6.3V4Z 4.7U_0805_10V4Z 0.1U_0402_16V7K
+1.8VS 2 2 2
L11 +VDDA18PCIEPLL
1 2 BLM18PG121SN1D_0603
1
C180 /

2.2U_0603_6.3V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
2 Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 12 of 45
A B C D E
 2 1

220 ohm @ 100MHz,2A U3D

PAR 4 OF 6
+1.8V_MEM_VDDQ SIDE@ +1.8VS MEM_A0 AB12 AA18 MEM_DQ0
L15 MEM_A1 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1
AE16 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) AA20
1 2 0_0805_5% MEM_A2 V11 AA19 MEM_DQ2
MEM_A3 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) MEM_DQ3
AE15 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) Y19
2 2 1 1 1 MEM_A4 AA12 V17 MEM_DQ4
SIDE@ SIDE@ SIDE@ SIDE@ SIDE@ MEM_A5 MEM_A4(NC) MEM_DQ4(NC) MEM_DQ5
AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
C611 C610 C248 C213 C205 MEM_A6 AB14 AA15 MEM_DQ6
1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 22U_0805_6.3V6M MEM_A7 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7
AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
1 1 2 2 2 MEM_A8 MEM_DQ8
AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20
MEM_A9 AD15 AD19 MEM_DQ9
MEM_A9(NC) MEM_DQ9/DVO_D5(NC)

SBD_MEM/DVO_I/F
MEM_A10 AC16 AE22 MEM_DQ10
MEM_A11 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) MEM_DQ11
AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
MEM_A12 AC14 AB20 MEM_DQ12
+1.8V_MEM_VDDQ MEM_A12(NC) MEM_DQ12(NC) MEM_DQ13
Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
AC22 MEM_DQ14
MEM_BA0 MEM_DQ14/DVO_D10(NC) MEM_DQ15
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
MEM_BA1 AE17 L14
MEM_BA1(NC)
2

1 MEM_BA2 AD17 Y17 MEM_DQS_P0 1 2 0_0603_5% +1.8VS

SIDE@ SIDE@ MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) MEM_DQS_N0
MEM_DQS0N/DVO_IDCKN(NC) W18 1
C255 R97 MEM_RAS# W12 AD20 MEM_DQS_P1 SIDE@
0.1U_0402_16V4Z 1K_0402_1% MEM_CAS# MEM_RASb(NC) MEM_DQS1P(NC) MEM_DQS_N1 C261
Y12 MEM_CASb(NC) MEM_DQS1N(NC) AE21
2 MEM_WE# 2.2U_0603_6.3V4Z
AD18
1

+MEM_VREF MEM_CS# MEM_WEb(NC) MEM_DM0 2

AB13 MEM_CSb(NC) MEM_DM0(NC) W17
MEM_CKE AB18 AE19 MEM_DM1
MEM_CKE(NC) MEM_DM1/DVO_D8(NC)
2

1 MEM_ODT V14
SIDE@ SIDE@ MEM_ODT(NC)
IOPLLVDD18(NC) AE23 +1.8V_IOPLLVDD
C259 R106 MEM_CLKP V15 AE24 +NB_IOPLLVDD L13 1 2 0_0603_5% +1.1VS
0.1U_0402_16V4Z 1K_0402_1% MEM_CLKN MEM_CKP(NC) IOPLLVDD(NC)
W14 MEM_CKN(NC) 1 1
B 2 SIDE@ SIDE@ SIDE@ B
AD23
1

R92 2 MEM_COMP_P IOPLLVSS(NC)

1 40.2_0402_1% AE12 MEM_COMPP(NC)
C260 C270
AD12 AE18 +MEM_VREF1 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z
MEM_COMPN(NC) MEM_VREF(NC) 2 2

SIDE@ RS880MR1@ RS780M_FCBGA528

+1.8V_MEM_VDDQ R93 2 1 40.2_0402_1% MEM_COMP_N
+1.8V_MEM_VDDQ

MEM_COMP_P and MEM_COMP_N trace

2

1 width >=10mils and 10mils spacing from

SIDE@ SIDE@
C254 R98 other Signals in X,Y,Z directions
0.1U_0402_16V4Z 1K_0402_1%
2
1

+MEM_VREF1 U61
MEM_BA0 L2 B9 MEM_DQ15
BA0 DQ15
2

1 MEM_BA1 L3 B1 MEM_DQ11
SIDE@ SIDE@ BA1 DQ14 MEM_DQ13
DQ13 D9
C249 R105 MEM_A12 R2 D1 MEM_DQ12
0.1U_0402_16V4Z 1K_0402_1% MEM_A11 A12 DQ12 MEM_DQ8
P7 A11 DQ11 D3
2 MEM_A10 MEM_DQ10
M2 D7
1

MEM_A9 A10/AP DQ10 MEM_DQ9

P3 A9 DQ9 C2
MEM_A8 P8 C8 MEM_DQ14
MEM_A7 A8 DQ8 MEM_DQ3
P2 A7 DQ7 F9
MEM_A6 N7 F1 MEM_DQ7
MEM_A5 A6 DQ6 MEM_DQ1
N3 A5 DQ5 H9
MEM_A4 N8 H1 MEM_DQ6
MEM_A3 A4 DQ4 MEM_DQ5
N2 A3 DQ3 H3
MEM_A2 M7 H7 MEM_DQ0
MEM_A1 A2 DQ2 MEM_DQ4
M3 A1 DQ1 G2
MEM_A0 M8 G8 MEM_DQ2
A0 DQ0
1

R91 MEM_CLKN K8 A9 +1.8V_MEM_VDDQ

@ MEM_CLKP CK VDDQ
J8 CK VDDQ C1
100_0402_1% C3
MEM_CKE VDDQ
K2 C7
2

CKE VDDQ
VDDQ C9
VDDQ E9
VDDQ G1
MEM_CS# L8 G3
CS VDDQ
VDDQ G7
MEM_WE# K3 G9
WE VDDQ
MEM_RAS# K7 A1
RAS VDD
VDD E1
MEM_CAS# L7 J9
CAS VDD
MEM_DM0 VDD M9
+1.8V_MEM_VDDQ Layout Note: 50 mil for VSSDL
F3 LDM VDD R1
MEM_DM1 B3 UDM +VDDL
VDDL J1
VSSDL J7
MEM_ODT K9 1
ODT SIDE@
C271
MEM_DQS_P0 F7 1U_0603_10V6K
MEM_DQS_N0 LDQS 2
E8 LDQS VSSQ A7
VSSQ B2
VSSQ B8
VSSQ D2
MEM_DQS_P1 B7 D8
MEM_DQS_N1 UDQS VSSQ
A8 UDQS VSSQ E7
A A
VSSQ F2
VSSQ F8
+MEM_VREF J2 H2
VREF VSSQ
VSSQ H8
A2 NC
E2 NC VSS A3 SA00002UH00 : Hynix (EVT verification)
MEM_BA2 L1 E3
NC VSS SA000031O00 : Samsung (DVT verification)
R3 NC VSS J3
R7 NC VSS N1
R8 NC VSS P9 64M*16 DDR2 500MHZ

H5PS1G63EFR-20L FBGA84
@

/
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 12, 2009 Sheet 13 of 45
2 1
 A B C D E

U3E < Main IO power for PCI-E graphics, SB, and GPP interfaces >
2A < Digital IO power for HyperTransport interface >
+1.1VS 2 1 L16 0_0805_5% +VDDHT J17 A6 +VDDA11PCIE FBMA-L11-201209-221LMA30T_0805 1 2 L17 +1.1VS
VDDHT_1 VDDPCIE_1
1 1 1 1 1 K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6

C220

C219

C222

C221

C224

C223

C211

C212
C209 C206 C207 C208 C210 L16 C6 VDDA_12=2.5A
VDDHT_3 VDDPCIE_3
M16 VDDHT_4 VDDPCIE_4 D6
4.7U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K P16 E6 1 1 1 1 2 2
2 2 2 2 2 VDDHT_5 VDDPCIE_5
R16 VDDHT_6 VDDPCIE_6 F6
T16 VDDHT_7 VDDPCIE_7 G7
2A < IO power for HyperTransport receive interface > VDDPCIE_8 H8
2 2 2 2 1 1

10U_0805_10V4Z

10U_0805_10V4Z
1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z

1U_0402_6.3V4Z
2 1 L18 0_0805_5% +VDDHTRX H18 J9
VDDHTRX_1 VDDPCIE_9

0.1U_0402_16V7K

0.1U_0402_16V7K
1 1 1 1 G19 VDDHTRX_2 VDDPCIE_10 K9
C215 C214 C216 C217 C218 F20 M9
1 VDDHTRX_3 VDDPCIE_11 1
E21 VDDHTRX_4 VDDPCIE_12 L9
10U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K D22 P9
2 2 2 2 VDDHTRX_5 VDDPCIE_13
B23 VDDHTRX_6 VDDPCIE_14 R9
A23 VDDHTRX_7 VDDPCIE_15 T9
2A < IO power for HyperTransport transmit interface > VDDPCIE_16 V9
+1.2V_HT 2 1 L19 0_0805_5% +VDDHTTX AE25 U9
VDDHTTX_1 VDDPCIE_17
1 1 1 1 1 AD24 VDDHTTX_2
C225 C226 C227 C228 C229 AC23 K12
VDDHTTX_3 VDDC_1
AB22 VDDHTTX_4 VDDC_2 J14
4.7U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K AA21 U16 +NB_CORE
2 2 2 2 2 VDDHTTX_5 VDDC_3 L90
Y20 VDDHTTX_6 VDDC_4 J11
W19 VDDHTTX_7 VDDC_5 K15 < Core power > VDD_CORE:GM=5A/PM=10A

POWER
V18 VDDHTTX_8 VDDC_6 M12 1 2 +1.1VS
U17 VDDHTTX_9 VDDC_7 L14
T17 L11 FBMA-L11-201209-121LMA40T_0805
VDDHTTX_10 VDDC_8

C120

C247

C240

C241

C242

C243

C230

C231

C244

C232
R17 M13

For EMI require

VDDHTTX_11 VDDC_9

C233

C245

C234
P17 VDDHTTX_12 VDDC_10 M15 1
M17 VDDHTTX_13 VDDC_11 N12 1 2 2 2 2 2 2 2 2 2 1 1
2A < 1.8V IO power for PCI-E graphics, SB, and GPP interfaces > N14 +
L22 0_0805_5% +VDDA18PCIE VDDC_12
+1.8VS 2 1 J10 VDDA18PCIE_1 VDDC_13 P11

1000P_0402_50V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

10U_0805_10V4Z

10U_0805_10V4Z

330U_D2E_2.5VM
1 1 1 1 1 1 P10 VDDA18PCIE_2 VDDC_14 P13
C235 C246 C236 C237 C238 C239 2 1 1 1 1 1 1 1 1 1 2 2 2
K10 VDDA18PCIE_3 VDDC_15 P14
M10 VDDA18PCIE_4 VDDC_16 R12 DVT change to B size
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K L10 R15
2 2 2 2 2 2 VDDA18PCIE_5 VDDC_17
W9 VDDA18PCIE_6 VDDC_18 T11
H9 VDDA18PCIE_7 VDDC_19 T15
T10 VDDA18PCIE_8 VDDC_20 U12
R10 VDDA18PCIE_9 VDDC_21 T14
Y9 J16 SIDE@
VDDA18PCIE_10 VDDC_22 L82
AA9 VDDA18PCIE_11 < Isolated power for side-port memory interface >
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10 1 2 0_0603_5% +1.8VS
AD9 VDDA18PCIE_13 VDD_MEM2(NC) AA11

C272SIDE@

C273SIDE@

C597SIDE@

C598SIDE@

C599SIDE@
2 2

R625 NSIDE@
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11
U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10
< 1.8V IO transform power > VDD_MEM5(NC) AB10
+1.8VS F9 VDD18_1 VDD_MEM6(NC) AC10

1
1 < 1.8V power for side-port memory interface > G9 VDD18_2 1 1 1 1 1
C251 +1.8VS L89 1 2 0_0603_5% AE11 H11 < 3.3V IO power >
VDD18_MEM1(NC) VDD33_1(NC)
1 AD11 VDD18_MEM2(NC) VDD33_2(NC) H12

1U_0402_6.3V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1U_0402_6.3V4Z C252
2 RS880MR1@ RS780M_FCBGA528 2 2 2 2 2

2
1U_0402_6.3V4Z
2

0_0402_5%
U3F

A25 VSSAHT1 VSSAPCIE1 A2

D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
E22 VSSAHT3 VSSAPCIE3 D3
G22 VSSAHT4 VSSAPCIE4 D5
G24 VSSAHT5 VSSAPCIE5 E4
G25 VSSAHT6 VSSAPCIE6 G1
H19 VSSAHT7 VSSAPCIE7 G2
J22 VSSAHT8 VSSAPCIE8 G4
L17 VSSAHT9 VSSAPCIE9 H7
L22 VSSAHT10 VSSAPCIE10 J4
L24 VSSAHT11 VSSAPCIE11 R7
L25 VSSAHT12 VSSAPCIE12 L1
M20 VSSAHT13 VSSAPCIE13 L2 +3VS
N22 VSSAHT14 VSSAPCIE14 L4 1 1
P20 L7 C250 C253
VSSAHT15 VSSAPCIE15
R19 VSSAHT16 VSSAPCIE16 M6
R22 N4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VSSAHT17 VSSAPCIE17 2 2
R24 VSSAHT18 VSSAPCIE18 P6
R25 VSSAHT19 VSSAPCIE19 R1
3 3
H20 VSSAHT20 VSSAPCIE20 R2
U22 VSSAHT21 VSSAPCIE21 R4
V19 VSSAHT22 VSSAPCIE22 V7

GROUND
W22 VSSAHT23 VSSAPCIE23 U4
W24 VSSAHT24 VSSAPCIE24 V8
W25 VSSAHT25 VSSAPCIE25 V6
Y21 VSSAHT26 VSSAPCIE26 W1
AD25 VSSAHT27 VSSAPCIE27 W2
VSSAPCIE28 W4
L12 VSS11 VSSAPCIE29 W7
M14 VSS12 VSSAPCIE30 W8
N13 VSS13 VSSAPCIE31 Y6
P12 VSS14 VSSAPCIE32 AA4
P15 VSS15 VSSAPCIE33 AB5
R11 VSS16 VSSAPCIE34 AB1
R14 VSS17 VSSAPCIE35 AB7
T12 VSS18 VSSAPCIE36 AC3
U14 VSS19 VSSAPCIE37 AC4
U11 VSS20 VSSAPCIE38 AE1
U15 VSS21 VSSAPCIE39 AE4
V12 VSS22 VSSAPCIE40 AB2
W11 VSS23
W15 VSS24
AC12 VSS25 VSS1 AE14
AA14 VSS26 VSS2 D11
Y18 VSS27 VSS3 G8
AB11 VSS28 VSS4 E14
AB15 VSS29 VSS5 E15
AB17 VSS30 VSS6 J15
AB19 VSS31 VSS7 J12
AE20 VSS32 VSS8 K14
AB21 VSS33 VSS9 M11
4 4
K11 VSS34 VSS10 L15

RS880MR1@ RS780M_FCBGA528

/
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 14 of 45
A B C D E
 A B C D E

< RS880 VSYNC mux at CRT_VSYNC pull High to 3K > < VSYNC : STRAP_DEBUG_BUS_GPIO_ENABLEb >

Enables the Test Debug Bus using GPIO.

SI2: Change to 3K pull high
R101
3K_0402_5%
1 : Enable (RX881, RS880)
12,17 UMA_CRT_VSYNC 2 1 +3VS
0 : Disable (RX881, RS880)

PIN: RS880--> VSYNC#

1 R102 1
@ 2 1 3K_0402_5%

< RS880 use register to control PCI-E configure > < DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0] >

These pin straps are used to configure PCI-E GPP mode.

000 : 00001
001 : 00010
010 : 01011
011 : 00100
100 : 01010
101 : 01100
111 : 01011

< SUS_SATA# : LOAD_EEPROM_STRAPS >

< RS880 SUS_STAT# >
Selects Loading of STRAPS from EPROM
R104
@ 1 2 150_0402_1%
12 AUX_CAL 1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected
2 2

D4 RS880:SUS_STAT#
12,21 SUS_STAT# @ 2 1 CH751H-40PT_SOD323-2 PLT_RST# 12,20,26,27,33,34

< HSYNC : STRAP_DEBUG_BUS_PCIE_ENABLEb >

< RS880 use HSYNC to enable SIDE PORT (internal pull high) >
RX881: Enables the Test Debug Bus using PCIE bus
R125
NSIDE@ 2 1 3K_0402_5%
1 : Disable ( Can still be enabled using nbcfg register access )
12,17 UMA_CRT_HSYNC +3VS
0 : Enable
R111
SIDE@ 2 1 3K_0402_5% RS880: Enables Side port memory ( RS780 use HSYNC#)

1. Disable (RS880)
0 : Enable (RS880)

3 3

4 4

/
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 15 of 45
A B C D E
 A B C D E

+3VS +3VS_CLK
+1.2V_HT +VDDCLK_IO
R167 1 2 0_0805_5%
1 1 1 1 1 1 1 1
R168 1 2 0_0805_5% C445 C446 C447 C448 C449 C450
1 1 1 1 1 1 C444 C451
22U_0805_6.3V6M 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 1U_0402_6.3V4Z
C452 C453 C454 C455 C456 C457 2 2 2 2 2 2 2 2
22U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2

CLK_48M R185 1 2 33_0402_5% < To Card Reader >

CLK_48M_CR 29
+3VS_CLK
1 1 1 1
C458 C459 C460 C461 CLK_48M_CRUSB R170 1 2 33_0402_5% < To SB710 USB host >
1 CLK_48M_USB 21 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 NB_OSC_14.318M_R R379 158_0402_1%
1 2
NB_OSC_14.318M 12 < To RS880 Clock block >

R380 1 2 90.9_0402_1%

R187 1 2 33_0402_5%
CLK_XTAL_OUT SB_14.318M 20

CLK_XTAL_IN
CLK_NBHT 12

< To RS880 Clock block >

CLK_NBHT# 12

Y2
R174 1 2 8.2K_0402_5% +3VS_CLK

+3VS_CLK

+3VS_CLK
+3VS_CLK
2 1

14.31818MHZ_20P_6X1430004201 C629 1 2 1U_0402_6.3V4Z

1 1
C464 C465
CLK_CPU_BCLK_R R946 1 2 0_0402_5%
CLK_CPU_BCLK 7
22P_0402_50V8J 22P_0402_50V8J

2
2 2
R186
@ < To CPU >

CLK_XTAL_OUT
Routing the trace at least 10mil 261_0402_1%

CLK_XTAL_IN

1
2 CLK_CPU_BCLK_R# R945 0_0402_5% 2

SEL_SATA
1 2 CLK_CPU_BCLK# 7

27M_SEL
73

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
U10

GND

XTAL_IN

REF_1/SEL_SATA
VSS_48
48MHz_0
48MHz_1
VDD_48

PD#
CPU_K8_0
XTAL_OUT

REF_2/SEL_27

HTT_0/66M_0
HTT_0#/66M_1

CPU_K8_0#
VSS_REF
REF_0/SEL_HTT66

VDD_REF
VDD_HTT

VSS_HTT
CLKREQ_NCARD# 1 2 +3VS_CLK
R324 8.2K_0402_5%
CLKREQ_MCARD2# 1 2
1 54 +3VS_CLK R325 8.2K_0402_5%
9,10,21,27 SMB_CK_CLK0 SCL VDD_CPU CLKREQ_LAN
2 SDA VDD_CPU_I/O 53 +VDDCLK_IO 1 2
9,10,21,27 SMB_CK_DAT0 R390 8.2K_0402_5%
+3VS_CLK 3 VDD_DOT VSS_CPU 52
4 51 CLKREQ_NCARD#
SRC_7#/27M CLKREQ_1# CLKREQ_MCARD2# CLKREQ_NCARD# 27
5 SRC_7/27M_SS CLKREQ_2# 50
CLKREQ_MCARD2# 27
6 VSS_DOT VDD_A 49 +3VS_CLK
7 SRC_5# VSS_A 48
8 SRC_5 VSS_SATA 47
12 CLK_SBLINK_BCLK# 9 SRC_4# SRC_6/SATA 46 CLK_SBSRC_BCLK 20
SB LINK 12 CLK_SBLINK_BCLK 10 SRC_4 SRC_6#/SATA# 45 CLK_SBSRC_BCLK# 20 SB SRC
11 VSS_SRC VDD_SATA 44 +3VS_CLK
+VDDCLK_IO 12 VDD_SRC_IO CLKREQ_3# 43
13 SRC_3# CLKREQ_4# 42
14 41 R372 1 2 10K_0402_5% +3VS_CLK
SRC_3 SB_SRC_SLOW#
27 CLK_PCIE_MCARD2# 15 SRC_2# SB_SRC_0 40
WLAN 27 CLK_PCIE_MCARD2 16 SRC_2 SB_SRC_0# 39
+3VS_CLK 17 VDD_SRC VDD_SB_SRC 38 +3VS_CLK
+VDDCLK_IO 18 VDD_SRC_IO VDD_SB_SRC_IO 37 +VDDCLK_IO

VDD_ATIG_IO

VSS_SB_SRC
3 3

ATIGCLK_2#

ATIGCLK_1#

ATIGCLK_0#
CLKREQ_0#

SB_SRC_1#
ATIGCLK_2

ATIGCLK_1

ATIGCLK_0

SB_SRC_1
VDD_ATIG
VSS_ATIG
VSS_SRC
SRC_1#

SRC_0#
SRC_1

SRC_0

+3VS_CLK
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
2

SLG8SP626VTR_QFN72_10x10
R179
@ 8.2K_0402_5% OSC_14M_NB
RS880 1.1V 158R/90.9R
1

SEL_SATA +3VS_CLK
+3VS_CLK
+VDDCLK_IO
2

R181 NB CLOCK INPUT TABLE

NBGFX_CLK 12
8.2K_0402_5% R180 NB GFX
NBGFX_CLK# 12
8.2K_0402_5% NB CLOCKS RX881 RS880
1

HT_REFCLKP 100M DIFF 100M DIFF

1

27M_SEL 10/23 Delete for MiniCard1

HT_REFCLKN 100M DIFF 100M DIFF
MiniCard_1
REFCLK_P 14M SE (1.8V) 14M SE (1.1V)
1 configure as SATA output CLKREQ_LAN
CLKREQ_LAN 26
SEL_SATA 1 * configure as 27M and 27M_SS output REFCLK_N NC vref
CLK_PCIE_LAN 26
0 * configure as normal SRC(SRC_6) output 27M_SEL GLAN
CLK_PCIE_LAN# 26
* default 0 configure as SRC_7 output GFX_REFCLK 100M DIFF 100M DIFF(IN/OUT)*
* default
CLK_PCIE_NCARD 27
New Card GPP_REFCLK 100M DIFF NC or 100M DIFF OUTPUT
4 CLK_PCIE_NCARD# 27 4
GPPSB_REFCLK 100M DIFF 100M DIFF

Use voltage divider resistor R379 & R380 to pull low /

1 configure as single-ended 66MHz output

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
NB_OSC_14.318M
0* configure as differential 100MHz output
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
* default AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 16 of 45
A B C D E
 A B C D E

+5VS
< CRT CONNECTOR > D36 +R_CRT_VCC +CRT_VCC
2 F2
1 1 2 1.1A_6V_MINISMDC110F-2
3 1
C475
RB491D_SOT23-3 0.1U_0402_16V4Z
2

1
D35 D37 D34
@ DAN217_SC59 @ DAN217_SC59 @ DAN217_SC59
1 1
+3VS JCRT
6

3
6
11 11
RED_L 1 1
7 7
D_DDCDATA 12
L47 GREEN_L 12
2 2
12 UMA_CRT_R 1 2 NBQ100505T-800Y_0402 RED_L 8 8
HSYNC 13
L48 BLUE_L 13
3 3
12 UMA_CRT_G 1 2 NBQ100505T-800Y_0402 GREEN_L +CRT_VCC 9 9
VSYNC 14 16
L49 14 G
4 4 G 17
12 UMA_CRT_B 1 2 NBQ100505T-800Y_0402 BLUE_L 10 10
1 D_DDCCLK 15
C706 15
5 5
1 1 1 1 1 1
1

1
C471 C859 C469 C858 C476 C472 220P_0402_50V7K @ ALLTO_C10532-11505-L_15P-T
R214 R211 R217 6P_0402_50V8D 6P_0402_50V8D 6P_0402_50V8D 6P_0402_50V8D 6P_0402_50V8D 6P_0402_50V8D 2
140_0402_1% 150_0402_1% 150_0402_1%
2 2 2 2 2 2
2

2
RS780 use 140 ohm, check RS880 use what value

+CRT_VCC
2 R370 2
C473 1 2 0.1U_0402_16V4Z 1 2 10K_0402_5%

5
1
P
OE#
2 4 D_HSYNC L84 1 2 10_0402_5% HSYNC
12,15 UMA_CRT_HSYNC A Y

G
U14
SN74AHCT1G125GW_SOT353-5 < SYNC SIGNAL >

3
L83 1 2 10_0402_5% VSYNC

+CRT_VCC
1 1
R381 C474 C470
C477 1 2 0.1U_0402_16V4Z 1 2 10K_0402_5% @ 10P_0402_50V8J @ 10P_0402_50V8J

5
1
2 2

P
OE#
2 4 D_VSYNC
12,15 UMA_CRT_VSYNC A Y

G
U13
SN74AHCT1G125GW_SOT353-5

3 +CRT_VCC
+3VS
3 3
PM:VGA Board have pull high
1

R237 R238 +3VS

4.7K_0402_5% 4.7K_0402_5% R100 R218
6.8K_0402_5% 6.8K_0402_5%
5
2

Q10B
12 UMA_CRT_DATA 4 3 2N7002DW-7-F_SOT363-6 D_DDCDATA
1

C177
@ 33P_0402_50V8K
< Display Data Channel >
2

+3VS
2

Q10A
1 6 2N7002DW-7-F_SOT363-6 D_DDCCLK
12 UMA_CRT_CLK
1 1
1

C181 C857 C856

@ 33P_0402_50V8K @ 470P_0402_50V8J @ 470P_0402_50V8J
2

2 2
RS780 DAC_SCL & SDA is 5V tolerance

4
FOR EMI 4

/
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 12, 2009 Sheet 17 of 45
A B C D E
 A B C D E

< Int. Camera, USB port 9 >

< EMI require >

@ R103 1 2 0_0402_5%

1 CAM@ L60 1
1 1 2
USB20_N9_R
USB20_P9_R
2
USB20_N9 21 LCD/PANEL BD. Conn.
USB20_P9 21
4 4 3 3

WCM-2012-900T_0805
+LCD_VDD +3VS +3VS
@ R99 1 2 0_0402_5%

1
R142 R143

150_0603_5% 100K_0402_5% 2 W=60mils

C262

6 2

2
0.1U_0402_16V7K
Q1A 1

3
S
R140 G
2N7002DW-T/R7_SOT363-6 2 1 2 47K_0402_5% 2 Q2
1 +LCD_VDD
C195 D AO3413_SOT23

1
0.01U_0402_25V7K
W=60mils
2 Inrush current = 0A

3
1 1
C263 C264
R668 Q1B @
1 2 0_0402_5% ENVDD 5 4.7U_0805_10V4Z 0.1U_0402_16V7K
12 UMA_ENVDD 2 2
2N7002DW-T/R7_SOT363-6
2 2

4
1
R144
100K_0402_5%

@ R968

2
+5VALW 1 2 0_0603_5%
CAM@
CAM@ R967 C274
+5VS 1 2 0_0603_5% 1 2 0.1U_0402_16V7K

JLVDS
+5V_LVDS_CAM 2 1
USB20_P9_R 2 1
4 4 3 3 UMA_LCD_TXCLK_ACLK+ 12
USB20_N9_R 6 5
6 5 UMA_LCD_TXCLK_ACLK- 12
8 8 7 7
31 INT_MIC_R 10 10 9 9 DAC_BRIG 34
12 UMA_LCD_TXOUT0_A0+ 12 12 11 11 INVT_PWM 34
12 UMA_LCD_TXOUT0_A0- 14 14 13 13
12 UMA_LCD_TXOUT0_A1+ 16 16 15 15 UMA_LCD_TZCLK_BCLK+ 12
12 UMA_LCD_TXOUT0_A1- 18 18 17 17 UMA_LCD_TZCLK_BCLK- 12
12 UMA_LCD_TXOUT0_A2+ 20 20 19 19
22 21 LCD_EDID_CLK
12 UMA_LCD_TXOUT0_A2- 22 21 UMA_LCD_DDC_CLK 12
24 23 LCD_EDID_DATA UMA_LCD_DDC_DAT 12
24 23 +3VS
12 UMA_LCD_TZOUT0_B0+ 26 26 25 25
28 27 +LCDVDD_R
12 UMA_LCD_TZOUT0_B0- 28 27
12 UMA_LCD_TZOUT0_B1+ 30 30 29 29
12 UMA_LCD_TZOUT0_B1- 32 32 31 31 1 1
34 33 +LCD_INV C874 C267
12 UMA_LCD_TZOUT0_B2+ 34 33
12 UMA_LCD_TZOUT0_B2- 36 36 35 35
38 38 37 37 L12 Rated Current MAX:3000mA B+ 2
680P_0402_50V7K
2
0.1U_0402_16V7K
3 BKOFF# 3
34 BKOFF# 40 40 39 39 2 1 FBMA-L11-201209-221LMA30T_0805
42 GND GMD 41 1 1 1 < EMI require >
C268 C269 C875
2

@ ACES_87242-4001-09
R146 68P_0402_50V8J 0.1U_0402_25V4Z 680P_0402_50V7K
2 2 2
10K_0402_5%
< EMI require >
1

+3VS 1.5A
L8
R68 1 2 4.7K_0402_5% LCD_EDID_CLK +LCDVDD_R 2 1 0_0805_5% +LCD_VDD

1 1
R69 1 2 4.7K_0402_5% LCD_EDID_DATA C265 C266

0.1U_0402_16V7K 4.7U_0805_10V4Z
2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 18 of 45
A B C D E
 A B C D E
< Power, reset and crystal >
+HDMI_5V_OUT_M +HDMI_5V_OUT
< HDMI CEC Controller > H@
Vgs = 10V
U8 D18 Id = 6A
+5VL 2 1 RB161M-20_SOD123-2 Rds_on = 35m ohm
EC_SMB_CK1 1 11
34,38 EC_SMB_CK1 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 CEC_INT# 34
@ R169 Inrush current = 0A
+3VL 2 12 CEC_TEST 1 2 4.7K_0402_5%
P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# +3VL
H@
R182 @ R171 D19 H@ F3
@ 2 1 4.7K_0402_5% CEC_RST# 3 13 CEC_FSHUPD
1 2 4.7K_0402_5% +5VS 2 1 RB161M-20_SOD123-2 2 1 1.1A_6V_MINISMDC110F-2
RESET# P1_4/TXD0
1
R178 C258
@ 1 2 47K_0402_5% CEC_XOUT 4 14 CEC_FSHUPD (Pin13) Low= Force to update flash. H@
XOUT/P4_7 P1_3/KI3#/AN11/TZOUT C543 0.1U_0402_16V7K
1 @ 1 2 1
2 1U_0402_6.3V4Z
5 15 C257
VSS/AVSS P1_2/KI2#/AN10/CMP0_2 @ 1 2 0.1U_0402_16V7K
R177 < HDMI_CEC level shift > < Place MOSFET close to HDMI connector >
@ 1 2 47K_0402_5% CEC_XIN 6 16 +3VL
XIN/P4_6 P4_2/VREF +3VL +3VL

7 17 HDMI_CLK_CEC
VCC/AVCC P1_1/KI1#/AN9/CMP0_1

2
R183 @ R157 @ D13
@ 2 1 4.7K_0402_5% 8 18 HDMI_DATA_CEC 10K_0402_5% CH751H-40PT_SOD323-2
MODE P1_0/KI0#/AN8/CMP0_0
1

1 1
C256 HDMI_CECIN 9 19 HDMI_HPD_R
@ P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0 HDMI_CECIN
0.1U_0402_16V7K @ R583
2 HDMI_CECOUT 10 EC_SMB_DA1 27K_0402_5%
P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 20 EC_SMB_DA1 34,38

1
D
Q149 @ 2 HDMI_CEC

2
@ R5F211B4D33SP-PLSP0020JB-A G
2N7002_SOT23-3 S

3
SI:Add R616~R624 for EMI requset < HDMI Connector >

1
@ R163 D
H@ C189 1 2 0.1U_0402_16V7K HDMI_TX0+ JHDMI HDMI_CECOUT1 2 27K_0402_5% 2 @ Q150
11 HDMI_TXD0+
H@ C188 1 2 0.1U_0402_16V7K HDMI_TX0- HDMI_HPD 19 G
11 HDMI_TXD0- HP_DET
H@ C190 1 2 0.1U_0402_16V7K HDMI_TX1+ +HDMI_5V_OUT 18 S 2N7002_SOT23-3
11 HDMI_TXD1+

3
+5V

1
H@ C184 1 2 0.1U_0402_16V7K HDMI_TX1- 17
11 HDMI_TXD1- DDC/CEC_GND
H@ C187 1 2 0.1U_0402_16V7K HDMI_TX2+ HDMI_SDATA 16 @ R165
11 HDMI_TXD2+ SDA
H@ C191 1 2 0.1U_0402_16V7K HDMI_TX2- HDMI_SCLK 15 100K_0402_5%
11 HDMI_TXD2- SCL
14 Reserved
2 HDMI_CEC 2
13

2
H@ C185 1 CEC
11 HDMI_CLK0+ 2 0.1U_0402_16V7K HDMI_CLK+ HDMI_R_CK- 12 CK- GND 20
H@ C186 1 2 0.1U_0402_16V7K HDMI_CLK- 11 21
11 HDMI_CLK0- CK_shield GND
HDMI_R_CK+ 10 22
HDMI_R_D0- CK+ GND
9 D0- GND 23
8 D0_shield
HDMI_R_D0+ 7 < HDMI DDC channel to device > < Place MOSFET close to HDMI connector >
HDMI_R_D1- D0+
6 D1-
< EMI solution > 5 +3VL +3VL +HDMI_5V_OUT
HDMI_R_D1+ D1_shield
4 D1+
HDMI_R_D2- 3
R616 D2-
2 D2_shield

2
HDMI_CLK- @ 1 2 0_0402_5% HDMI_R_CK- HDMI_R_D2+ 1 D2+ @ @ H@ H@

2
@ TYCO_1939864-1_19P R210 R236 @ R188 R212

G
10K_0402_5% 10K_0402_5% Q33 2.2K_0402_5% 2.2K_0402_5%
H@ L85 BSH111_SOT23-3

1
1 1 2 HDMI_DATA_CEC 3 1 HDMI_SDATA
2

2
S

D
@

G
4 3 Q34
4 3 BSH111_SOT23-3
WCM-2012-900T_0805 < Termination resistor > HDMI_CLK_CEC 3 1 HDMI_SCLK

D
R617 < Place MOSFET close to HDMI connector >
HDMI_CLK+ @ 1 2 0_0402_5% HDMI_R_CK+ H@
R307 H@ Q136A
R618 HDMI_R_CK+ 1 2 715_0402_1% 6 1 +3VS +3VS
HDMI_TX0- @ 1 2 0_0402_5% HDMI_R_D0- 2N7002DW-7-F_SOT363-6
HDMI_R_CK- 1 2
715_0402_1%
2

2
R315 +5VS H@ H@
3 H@ WCM-2012-900T_0805 H@ R176 R209 3

2
4 4 4.7K_0402_5% 4.7K_0402_5% H@
3 3

G
Q139
+5VS BSH111_SOT23-3

1
1 2 3 1 HDMI_SDATA
1 2 12 HDMIDAT_UMA
5

H@
L86

D
R304 H@ Q136B
HDMI_R_D0- 1 2 715_0402_1% 3 4

2
R619 2N7002DW-7-F_SOT363-6 H@

G
HDMI_TX0+ @ 1 2 0_0402_5% HDMI_R_D0+ HDMI_R_D0+ 1 2 Q140
715_0402_1% BSH111_SOT23-3
R620 R172 3 1 HDMI_SCLK
HDMI_TX1- @ 0_0402_5% HDMI_R_D1- H@ 12 HDMICLK_UMA
1 2

D
H@ L87
1 1 2 H@ < Hot-plug detection & level shift > +5VL
2 R297 H@ Q137A
HDMI_R_D1- 1 2 715_0402_1% 6 1 HDMI_HPD
4 3 2N7002DW-7-F_SOT363-6 2
4 3 HDMI_R_D1+ C851
1 2

5
1

2
WCM-2012-900T_0805 715_0402_1% H@ 2
2

R173 0.1U_0402_16V4Z R628 C850

P
OE#
+5VS 1
R621 H@ 2 4 HDMI_HPD_R H@ H@
HDMI_TX1+ @ 0_0402_5% HDMI_R_D1+ A Y 100K_0402_5% 0.1U_0402_16V4Z
1 2

G
H@ U39 1

1
R623 +5VS SN74AHCT1G125GW_SOT353-5

3
HDMI_TX2- @ 1 2 0_0402_5% HDMI_R_D2-
5

H@ R588
R141 H@ Q137B H@ 2 1 2.2K_0402_5% +3VS
HDMI_R_D2+ 1 2 715_0402_1% 3 4 R589
4 H@ WCM-2012-900T_0805 2N7002DW-7-F_SOT363-6 +3VL H@ 2 1 100K_0402_5% 4
HPD 12,21
4 4 HDMI_R_D2-
3 3 1 2
715_0402_1% D57 R86
R139 HDMI_HPD_R H@ 1 2 CH751H-40PT_SOD323-2 2 1 100K_0402_5%
1 2 H@
1 2
L88

HDMI_TX2+ @
R624
0_0402_5% HDMI_R_D2+
Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 19 of 45
A B C D E
 A B C D E

+3VALW
+3VS
C506 R175
2 1 0.1U_0402_16V4Z U16 PCI_REQ#0 @ 1 2 8.2K_0402_5%
NC7SZ08P5X_NL_SC70-5

5
R303 C501
RN3 1 2 100K_0402_5% PLT_RST# 2 CLK_PCI_EC @ 1 2 100_0402_5% @ 1 2 100P_0402_50V8J

P
B PLT_RST#
Y 4 PLT_RST# 12,15,26,27,33,34
NB_RST#_R 1 R369 C503
A

G
CLK_PCI_SIO2 @ 1 2 100_0402_5% @ 1 2 100P_0402_50V8J

3
R312
@ 2 1 33_0402_5% U15A

1
N2
SB700 P4 R309 1
A_RST# PCICLK0
Part 1 of 5 PCICLK1 P3 1 2 22_0402_5% CLK_PCI_PCM 28

PCI CLKS
C492 1 2 0.1U_0402_16V7K SB_RX0P_C V23 P1
11 SB_RX0P PCIE_TX0P PCICLK2 PCI_CLK2 24
C493 1 2 0.1U_0402_16V7K SB_RX0N_C V22 P2
11 SB_RX0N PCIE_TX0N PCICLK3 PCI_CLK3 24
C494 1 2 0.1U_0402_16V7K SB_RX1P_C V24 T4
11 SB_RX1P PCIE_TX1P PCICLK4 PCI_CLK4 24
C495 1 2 0.1U_0402_16V7K SB_RX1N_C V25 T3
< x4 PCIE A-link To NB > 11 SB_RX1N
C496 1 2 0.1U_0402_16V7K SB_RX2P_C U25
PCIE_TX1N PCICLK5/GPIO41 PCI_CLK5 24
11 SB_RX2P PCIE_TX2P
C497 1 2 0.1U_0402_16V7K SB_RX2N_C U24
11 SB_RX2N PCIE_TX2N
C498 1 2 0.1U_0402_16V7K SB_RX3P_C T23 R313
11 SB_RX3P PCIE_TX3P
C499 1 2 0.1U_0402_16V7K SB_RX3N_C T22 N1 2 1 33_0402_5% PCI_RST# 28
11 SB_RX3N PCIE_TX3N PCIRST#

PCI EXPRESS INTERFACE

11 SB_TX0P U22 PCIE_RX0P PCI_AD[0..31] 24,28
11 SB_TX0N U21 U2 PCI_AD0
PCIE_RX0N AD0 PCI_AD1
11 SB_TX1P U19 PCIE_RX1P AD1 P7
PCI_AD2
< x4 PCIE A-link from NB > 11
11
SB_TX1N
SB_TX2P
V19
R20
PCIE_RX1N AD2 V4
T1 PCI_AD3
PCIE_RX2P AD3 PCI_AD4
11 SB_TX2N R21 PCIE_RX2N AD4 V3
11 SB_TX3P R18 U1 PCI_AD5
PCIE_RX3P AD5 PCI_AD6
11 SB_TX3N R17 PCIE_RX3N AD6 V1
V2 PCI_AD7
R305 AD7 PCI_AD8
2 1 562_0402_1% T25 PCIE_CALRP AD8 T2
+PCIE_VDDR R306 2 1 2.05K_0402_1% T24 W1 PCI_AD9
PCIE_CALRN AD9 PCI_AD10
AD10 T9
+1.2V_HT L53 1 2 BLM18PG121SN1D_0603 +SB_PCIEVDD P24 R6 PCI_AD11
PCIE_PVDD AD11 PCI_AD12
1 AD12 R7
C504 P25 R5 PCI_AD13
2.2U_0603_6.3V4Z PCIE_PVSS AD13 PCI_AD14
AD14 U8
U5 PCI_AD15
2 AD15 PCI_AD16
AD16 Y7
W8 PCI_AD17
AD17 PCI_AD18
AD18 V9
Y8 PCI_AD19
2 AD19 PCI_AD20 2
Close to SB AD20 AA8
Y4 PCI_AD21
AD21 PCI_AD22
AD22 Y3
Y2 PCI_AD23
AD23 PCI_AD24
AD24 AA2
AB4 PCI_AD25
AD25 PCI_AD26
16 CLK_SBSRC_BCLK N25 PCIE_RCLKP/NB_LNK_CLKP AD26 AA1
N24 AB3 PCI_AD27
16 CLK_SBSRC_BCLK# PCIE_RCLKN/NB_LNK_CLKN AD27
AB2 PCI_AD28
AD28 PCI_AD29
K23 NB_DISP_CLKP AD29 AC1
K22 AC2 PCI_AD30
NB_DISP_CLKN AD30 PCI_AD31
AD31 AD1
M24 W2 PCI_CBE#0

PCI INTERFACE
NB_HT_CLKP CBE0# PCI_CBE#0 28
M25 U7 PCI_CBE#1
NB_HT_CLKN CBE1# PCI_CBE#1 28
AA7 PCI_CBE#2
CBE2# PCI_CBE#2 28
P17 Y1 PCI_CBE#3
CPU_HT_CLKP CBE3# PCI_CBE#3 28
M18 CPU_HT_CLKN FRAME# AA6 PCI_FRAME# 28
DEVSEL# W5 PCI_DEVSEL# 28
M23 SLT_GFX_CLKP IRDY# AA5 PCI_IRDY# 28
M22 SLT_GFX_CLKN TRDY# Y5 PCI_TRDY# 28
PAR U6 PCI_PAR 28
J19 GPP_CLK0P STOP# W6 PCI_STOP# 28
J18 GPP_CLK0N PERR# W4
SERR# V7
L20 GPP_CLK1P REQ0# AC3 PCI_REQ#0 28
L19 GPP_CLK1N REQ1# AD4
REQ2# AB7
M19 GPP_CLK2P REQ3#/GPIO70 AE6
M20 AB6 PAD T15
GPP_CLK2N REQ4#/GPIO71
GNT0# AD2 PCI_GNT#0 28

CLOCK GENERATOR
N22 GPP_CLK3P GNT1# AE4
P22 GPP_CLK3N GNT2# AD5
3 3
GNT3#/GPIO72 AC6
L18 AE5 PAD T16
16 SB_14.318M 25M_48M_66M_OSC GNT4#/GPIO73
CLKRUN# AD6 CLKRUN# 28
LOCK# V5
J21 25M_X1
INTE#/GPIO33 AD3 PCI_PIRQA# 28
INTF#/GPIO34 AC4
INTG#/GPIO35 AE2
C643 Close to SB J20 AE3
25M_X2 INTH#/GPIO36
1 2 12P_0402_50V8J

Y3
LPCCLK0 G22 CLK_PCI_EC1 R308 1 2 22_0402_5% CLK_PCI_EC CLK_PCI_EC 24,34
1

4 OUT NC 3 LPCCLK1 E22 CLK_PCI_SIOC R310 1 2 22_0402_5% CLK_PCI_SIO2 24,33

R389 SB_32KHI A3 H24
X1 LAD0 LPC_AD0 33,34
20M_0603_5% 1 2 H23
IN NC LAD1 LPC_AD1 33,34
C652 32.768KHZ_12.5P_1TJS125BJ4A421P LAD2 J25
J24
LPC_AD2 33,34 EC & TPM &Debug

RTC XTAL
LPC_AD3 33,34
2

LAD3

LPC
1 2 12P_0402_50V8J SB_32KHO B3 X2 LFRAME# H25 D17 @ R965
H22 @ 1 2 CH751H-40PT_SOD323-2 2 1 300_0402_5% +3VS
LDRQ0#
LDRQ1#/GNT5#/GPIO68 AB8
AD7 R966 1 2 0_0402_5%
BMREQ#/REQ5#/GPIO65 LPC_FRAME# 33,34
SERIRQ V15
SERIRQ 28,33,34
CPU_LDT_REQ# F23
7,12 CPU_LDT_REQ# ALLOW_LDTSTP
+3VS R319 2 1 10K_0402_5% H_PROCHOT# H_PROCHOT# F24 C3 RTC_CLK 24 STRAP PIN
7 H_PROCHOT# PROCHOT# RTCCLK
H_PWRGD F22 C2
7,43 H_PWRGD LDT_PG CPU INTRUDER_ALERT#
7,12 LDT_STOP# G25 LDT_STP# VBAT B2 +SB_VBAT
7 LDT_RST# G24 LDT_RST#
RTC
SB710R1@ 218S7EALA11FG_BGA528_SB700
4 4
+SB_VBAT +RTCVCC +RTCBATT
D10
R316 R317 R184
1 2 120_0402_5% 1 2 120_0402_5% 2 1 1K_0402_5% 3
1 1 W=20mils
2

C509 1
C510 J1 1
Compal Electronics, Inc.
2

0.1U_0402_16V7K 1U_0402_6.3V4Z @ JUMP_43X39 C297 2

Security Classification Compal Secret Data
2 2
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
1

0.1U_0402_16V7K
2 BAS40-04_SOT23-3 Schematic, MB LA-5332P
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
+CHGRTC
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 20 of 45
A B C D E
 A B C D E

+3VALW
R320
@ 1 2 2.2K_0402_5% SB_TEST2

R321
@ 1 2 2.2K_0402_5% SB_TEST1

R322
@ 1 2 2.2K_0402_5% SB_TEST0

R561
Reserve for EMI request
2 1 1K_0402_5% EC_SWI_R# U15D R311 C617
1 2 100_0402_5% 1 2 100P_0402_50V8J
+3VS Part 4 of 5
1 R328 E1
SB700 1
1.2K_0402_5% SMB_CK_CLK0 PCI_PME#/GEVENT4#
1 2 demo circuit LID use RI# E2 RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC C8 CLK_48M_USB 16
<S0> H7 R323
R329 SLP_S2/GPM9# USB_RCOMP
34 PM_SLP_S3# F5 SLP_S3# USB_RCOMP G8 1 2 11.8K_0402_1%
1 2 1.2K_0402_5% SMB_CK_DAT0 G1
34 PM_SLP_S5# SLP_S5#

USB MISC
ACPI / WAKE UP EVENTS
34 PBTN_OUT# H2 PWR_BTN#
+3VALW H1
34,43 SB_PWRGD PWR_GOOD
R331 SUS_STAT# K3
12,15 SUS_STAT# SUS_STAT#
1 2 2.2K_0402_5% SMB_CK_CLK1 SB_TEST2 H5 E6
SB_TEST1 TEST2 USB_FSD13P
R332
< S0~ S5 ASF only > SB_TEST0
H4 TEST1 USB_FSD13N E7
H3 TEST0

USB 1.1
1 2 2.2K_0402_5% SMB_CK_DAT1 Y15 F7
34 GATEA20 GA20IN/GEVENT0# USB_FSD12P
34 KB_RST# W15 KBRST#/GEVENT1# USB_FSD12N E8

RN2
share with USB OC PIN 34 EC_SCI# K4 LPC_PME#/GEVENT3#
34 EC_SMI# K24 LPC_SMI#/EXTEVNT1# USB_HSD11P H11
1 2 100K_0402_5% EXP_CPPE# need always pull high F1 J10
S3_STATE/GEVENT5# USB_HSD11N
(For Express card ) EC_SWI_R#
J2 SYS_RESET#/GPM7#
27,34 EC_SWI_R# H6 WAKE#/GEVENT8# USB_HSD10P E11
F2 BLINK/GPM6# USB_HSD10N F11
H_THERMTRIP# J6
7 H_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2#
R327 W14 A11 USB20_P9
12 NB_PWRGD NB_PWRGD USB_HSD9P USB20_P9 18
2 1 100K_0402_5% EC_RSMRST# B11 USB20_N9 USB-9 Int Camera
USB_HSD9N USB20_N9 18
EC_RSMRST# D3
34 EC_RSMRST# RSMRST#
C10 USB20_P8
USB_HSD8P USB20_P8 27
D10 USB20_N8 USB-8 WLAN
USB_HSD8N USB20_N8 27
+3VS AE18 G11 USB20_P7
SATA_IS0#/GPIO10 USB_HSD7P USB20_P7 32
AD18 H12 USB20_N7 USB-7 FP
CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSD7N USB20_N7 32
R388 AA19
4.7K_0402_5% SUS_STAT# SMARTVOLT1/SATA_IS2#/GPIO4 USB20_P6
1 2 W17 CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSD6P E12 USB20_P6 32
V17 E14 USB20_N6 USB-6 Bluetooth
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSD6N USB20_N6 32
W20 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
2 USB20_P5 2
30 SB_SPKR W21 C12

USB 2.0
SPKR/GPIO2 USB_HSD5P USB20_P5 27
9,10,16,27 SMB_CK_CLK0 SMB_CK_CLK0 AA18 D12 USB20_N5 USB-5 New Card
SCL0/GPOC0# USB_HSD5N USB20_N5 27
9,10,16,27 SMB_CK_DAT0 SMB_CK_DAT0 W18
SMB_CK_CLK1 SDA0/GPOC1# USB20_P4
27 SMB_CK_CLK1 K1 SCL1/GPOC2# USB_HSD4P B12 USB20_P4 29
SMB_CK_DAT1 K2 A12 USB20_N4 USB-4 Card Reader (3 IN 1)
27 SMB_CK_DAT1 SDA1/GPOC3# USB_HSD4N USB20_N4 29
AA20 DDC1_SCL/GPIO9

GPIO
Y18 DDC1_SDA/GPIO8 USB_HSD3P G12
R400 C1 G14
@ 1 LLB#/GPIO66 USB_HSD3N
+3VS 2 4.7K_0402_5% Y19 SMARTVOLT2/SHUTDOWN#/GPIO5
G5 H14 USB20_P2
DDR3_RST#/GEVENT7# USB_HSD2P USB20_P2 25
R16 H15 USB20_N2 USB-2 USB/eSATA
USB_HSD2N USB20_N2 25
12,19 HPD 1 2 0_0402_5%
A13 USB20_P1
USB_HSD1P USB20_P1 32
B13 USB20_N1 USB-1 Right side
USB_HSD1N USB20_N1 32

Reserve for EMI request @ C618 B14 USB20_P0

USB_HSD0P USB20_P0 32
2 1 10P_0402_50V8J B9 A14 USB20_N0 USB-0 Right side
34 EC_LID_OUT# USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 32
Close to SB @ C619
27 EXP_CPPE# B8 USB_OC5#/IR_TX0/GPM5#
A8 A18

USB OC
25,34 USB_OC#2 USB_OC4#/IR_RX0/GPM4# IMC_GPIO8
2 1 10P_0402_50V8J 32,34 USB_OC#0 A9 B18
USB_OC3#/IR_RX1/GPM3# IMC_GPIO9
E5 USB_OC2#/GPM2# IMC_PWM0/IMC_GPIO10 F21
F8 USB_OC1#/GPM1# SCL2/IMC_GPIO11 D21
R333 1 2 33_0402_5% E4 F19
30 HDA_BITCLK_CODEC USB_OC0#/GPM0# SDA2/IMC_GPIO12
R334 1 2 33_0402_5% HDA_BITCLK E20
33 HDA_BITCLK_MDC SCL3_LV/IMC_GPIO13
R335 1 2 33_0402_5% M1 E21
33 HDA_SDOUT_MDC AZ_BITCLK SDA3_LV/IMC_GPIO14
R336 1 2 33_0402_5% HDA_SDOUT M2 E19
30 HDA_SDOUT_CODEC AZ_SDOUT IMC_PWM1/IMC_GPIO15
HDA_SDIN0 J7 D19 STRAP PIN
30 HDA_SDIN0 AZ_SDIN0/GPIO42 IMC_PWM2/IMC_GPO16 GPIO16 24
HDA_SDIN1 J8 E18 STRAP PIN
33 HDA_SDIN1 AZ_SDIN1/GPIO43 IMC_PWM3/IMC_GPO17 GPIO17 24
L8

HD AUDIO
AZ_SDIN2/GPIO44
M3 AZ_SDIN3/GPIO46 IMC_GPIO18 G20
R337 1 2 33_0402_5% HDA_SYNC L6 G21
33 HDA_SYNC_MDC AZ_SYNC IMC_GPIO19
R338 1 2 33_0402_5% M4 D25
3 30 HDA_SYNC_CODEC AZ_RST# IMC_GPIO20 3
L5 AZ_DOCK_RST#/GPM8# IMC_GPIO21 D24
R339 2 33_0402_5% HDARST#

INTEGRATED uC
30 HDA_RST#_CODEC 1 IMC_GPIO22 C25
R340 1 2 33_0402_5% C24
33 HDA_RST#_MDC IMC_GPIO23
STRAP PIN 24 HDARST# IMC_GPIO24 B25
IMC_GPIO25 C23

IMC_GPIO26 B24
IMC_GPIO27 B23
IMC_GPIO28 A23
IMC_GPIO29 C22
IMC_GPIO30 A22
IMC_GPIO31 B22
IMC_GPIO32 B21
IMC_GPIO33 A21
H19 IMC_GPIO0 IMC_GPIO34 D20
H20 IMC_GPIO1 IMC_GPIO35 C20

INTEGRATED uC
H21 SPI_CS2#/IMC_GPIO2 IMC_GPIO36 A20
F25 IDE_RST#/F_RST#/IMC_GPO3 IMC_GPIO37 B20
IMC_GPIO38 B19
D22 IMC_GPIO4 IMC_GPIO39 A19
E24 IMC_GPIO5 IMC_GPIO40 D18
E25 IMC_GPIO6 IMC_GPIO41 C18
D23 IMC_GPIO7

SB710R1@ 218S7EALA11FG_BGA528_SB700

4 4

/
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 21 of 45
A B C D E
 A B C D E

U15B

AD9
SB700 AA24
SATA_TX0P IDE_IORDY
AE9 SATA_TX0N Part 2 of 5 IDE_IRQ AA25
IDE_A0 Y22
AB10 SATA_RX0N IDE_A1 AB23
AC10 SATA_RX0P IDE_A2 Y23
IDE_DACK# AB24
SATA_STX_DRX_P1 AE10 AD25
25 SATA_STX_DRX_P1 SATA_TX1P IDE_DRQ
SATA_STX_DRX_N1 AD10 AC25
25 SATA_STX_DRX_N1 SATA_TX1N IDE_IOR#
HDD1 AD11
IDE_IOW# AC24
Y25
1 25 SATA_RXN1_C SATA_RX1N IDE_CS1# 1
25 SATA_RXP1_C AE11 SATA_RX1P IDE_CS3# Y24

SATA_STX_DRX_P2 AB12 AD24

25 SATA_STX_DRX_P2 SATA_TX2P IDE_D0/GPIO15
SATA_STX_DRX_N2 AC12 AD23
25 SATA_STX_DRX_N2 SATA_TX2N IDE_D1/GPIO16

ATA 66/100/133
eSATA AE12
IDE_D2/GPIO17 AE22
AC22
25 SATA_RXN2_C SATA_RX2N IDE_D3/GPIO18
25 SATA_RXP2_C AD12 SATA_RX2P IDE_D4/GPIO19 AD21
IDE_D5/GPIO20 AE20
SATA_STX_DRX_P3 AD13 AB20
25 SATA_STX_DRX_P3 SATA_TX3P IDE_D6/GPIO21
SATA_STX_DRX_N3 AE13 AD19
25 SATA_STX_DRX_N3 SATA_TX3N IDE_D7/GPIO22
AE19
ODD

SERIAL ATA
IDE_D8/GPIO23
25 SATA_RXN3_C AB14 SATA_RX3N IDE_D9/GPIO24 AC20
25 SATA_RXP3_C AC14 SATA_RX3P IDE_D10/GPIO25 AD20
IDE_D11/GPIO26 AE21
AE14 SATA_TX4P IDE_D12/GPIO27 AB22
AD14 SATA_TX4N IDE_D13/GPIO28 AD22
IDE_D14/GPIO29 AE23
AD15 SATA_RX4N IDE_D15/GPIO30 AC23
AE15 SATA_RX4P
AB16 SATA_TX5P
AC16 SATA_TX5N HDMI DISABLE HDMI ENABLE
SPI_DI/GPIO12 G6
AE16 SATA_RX5N SPI_DO/GPIO11 D2
AD16 SATA_RX5P SPI_CLK/GPIO47 D1 SIDE_PORT_EN# 0 1
R342 F4

SPI ROM
SPI_HOLD#/GPIO31
2 1 1K_0402_1% SATA_CAL V12 SATA_CAL SPI_CS1#/GPIO32 F3
GPIO48,GPIO49 GOT INTERNAL PU 8.2K TO S0
R343 SATA_X1 Y12 U15
SATA_X1 LAN_RST#/GPIO13
+3VS 1 2 10K_0402_5% ROM_RST#/GPIO14 J1
SATA_X2 AA12 H@ NHDMI@
SATA_X2 R195 R196
FANOUT0/GPIO3 M8
2 SIDE_PORT_EN# 10K_0402_5% SIDE_PORT_EN# 2
35 SATA_LED# W11 SATA_ACT#/GPIO67 FANOUT1/GPIO48 M5 +3VS 1 2 1 2 1K_0402_5%
M7 @R197
@ R197 1 2 10K_0402_5% +3VS
L54 FANOUT2/GPIO49

+1.2V_HT BLM18PG121SN1D_0603 2 1 +PLLVDD_SATA AA11 P5

PLLVDD_SATA FANIN0/GPIO50
2 2 FANIN1/GPIO51 P8
C522 C523 W12 XTLVDD_SATA SATA PWR FANIN2/GPIO52 R8

1U_0402_6.3V4Z 1U_0402_6.3V4Z C6
1 1 TEMP_COMM
TEMPIN0/GPIO61 B6
TEMPIN1/GPIO62 A6
A5 SPK_SEL
TEMPIN2/GPIO63 SPK_SEL 30 +3VALW
B5
HW MONITOR
TEMPIN3/TALERT#/GPIO64 EC_THERM# 34
D41 R571
A4 2 1 CH751H-40PT_SOD323-2 ACIN 34,35,37 SLP_CHG# 1 2 100K_0402_5%
L55 VIN0/GPIO53 BT_DET#
VIN1/GPIO54 B4 BT_DET# 32
+3VS BLM18PG121SN1D_0603
2 1 +XTLVDD_SATA C4 R572
VIN2/GPIO55 R562 SLP_CHG_M3
2 1 VIN3/GPIO56 D4 SLP_CHG# 25 1 2 100K_0402_5%
VIN4/GPIO57 D5 SLP_CHG_M3 25 1 2 150K_0402_5% +3VALW
C524 @ C625 D6 R582
VIN5/GPIO58 SLP_CHG_M4 25
1U_0402_6.3V4Z 0.1U_0402_16V4Z A7 LFB_ID0 SLP_CHG_M4 1 2 100K_0402_5%
1 2 VIN6/GPIO59 LFB_ID1
VIN7/GPIO60 B7

L56
F6 +SB_AVDD 2 1 0_0603_5% +3VALW
AVDD
1 1
G7 C525 C526
AVSS
0.1U_0402_16V4Z 2.2U_0603_6.3V4Z
SB710R1@ 2 2
218S7EALA11FG_BGA528_SB700

3 C516 3
10P_0402_50V8J 2 1 SATA_X1
1

Y4 R341
SA00002UH00 : Hynix
25MHz_20pF_6X25000017 10M_0402_5% LFB_ID1 LFB_ID0 SA000031O00 : Samsung
2

C517
2

10P_0402_50V8J 2 1 SATA_X2
Hynix 0 0 64M*16 DDR2 500MHZ

Samsung 0 1

1 0

1 1

LFB_ID0 to LFB_ID1 got internal PU 10K to S5.

@ R189 @ R192
+3VALW 1 2 10K_0402_5% LFB_ID1 1 2 1K_0402_5%

@ R191 @ R190
+3VALW 1 2 10K_0402_5% LFB_ID0 1 2 1K_0402_5%
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 22 of 45
A B C D E
 A B C D E

U15C U15E
R593
SB700 +1.2V_HT_R 0_0805_5%
+3VS L9
M9
VDDQ_1
Part 3 of 5
VDD_1 L15
M12
1 2 +1.2V_HT SB700 A2
@ C528 22U_0805_6.3V6M VDDQ_2 VDD_2 VSS_1
2 1 T15 VDDQ_3 VDD_3 M14 VSS_2 A25
U9 N13 B1

CORE S0
1 @ C531 1U_0402_6.3V4Z VDDQ_4 VDD_4 10U_0805_6.3V6M C529 VSS_3 1
1 2 U16 VDDQ_5 VDD_5 P12 1 2 VSS_4 D7
@ C530 1 2 1U_0402_6.3V4Z U17 P14 T10 F20
VDDQ_6 VDD_6 AVSS_SATA_1 VSS_5

PCI/GPIO I/O
@ C533 1 2 1U_0402_6.3V4Z V8 R11 1U_0402_6.3V4Z 2 1 C532 U10 G19
@ C536 1U_0402_6.3V4Z VDDQ_7 VDD_7 1U_0402_6.3V4Z C534 AVSS_SATA_2 VSS_6
1 2 W7 VDDQ_8 VDD_8 R15 2 1 U11 AVSS_SATA_3 VSS_7 H8
@ C535 1 2 1U_0402_6.3V4Z Y6 T16 1U_0402_6.3V4Z 2 1 C538 U12 K9
VDDQ_9 VDD_9 1U_0402_6.3V4Z C537 AVSS_SATA_4 VSS_8
AA4 VDDQ_10 2 1 V11 AVSS_SATA_5 VSS_9 K11
@ C539 1 2 0.1U_0402_16V4Z AB5 V14 K16
@ C541 0.1U_0402_16V4Z VDDQ_11 0.1U_0402_16V4Z C527 AVSS_SATA_6 VSS_10
1 2 AB21 VDDQ_12 2 1 W9 AVSS_SATA_7 VSS_11 L4
@ C542 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 1 C540 Y9 L7
AVSS_SATA_8 VSS_12
Y11 AVSS_SATA_9 VSS_13 L10
No IDE device unmount CAP Y14 AVSS_SATA_10 VSS_14 L11
Y17 AVSS_SATA_11 VSS_15 L12
+3VS Y20 L21 +1.2V_HT +1.2V_HT AA9 L14
VDD33_18_1 CKVDD_1.2V_1 AVSS_SATA_12 VSS_16
AA21 VDD33_18_2 CKVDD_1.2V_2 L22 AB9 AVSS_SATA_13 VSS_17 L16
AA22 L24 AB11 M6

IDE/FLSH I/O

CLKGEN I/O
VDD33_18_3 CKVDD_1.2V_3 AVSS_SATA_14 VSS_18
AE25 VDD33_18_4 CKVDD_1.2V_4 L25 AB13 AVSS_SATA_15 VSS_19 M10
AB15 AVSS_SATA_16 VSS_20 M11
+PCIE_VDDR AB17 M13
L61 AVSS_SATA_17 VSS_21
AC8 AVSS_SATA_18 VSS_22 M15
+1.2V_HT 2 1 0_0805_5% AD8 AVSS_SATA_19 VSS_23 N4
R564 AE8 N12
+S5_3V 0_0805_5% AVSS_SATA_20 VSS_24
1 2 +3VALW VSS_25 N14
C552 2 1 4.7U_0805_10V6K P6
POWER 22U_0805_6.3V6M 1 2 @
@C556
C556 VSS_26
VSS_27 P9
C553 1 2 @ 1U_0402_6.3V4Z P10
C555 1U_0402_6.3V4Z 2.2U_0603_6.3V4Z C559 VSS_28
1 2 2 1 A15 AVSS_USB_1 VSS_29 P11
C554 1 2 1U_0402_6.3V4Z P18 2.2U_0603_6.3V4Z 2 1 C561 B15 P13
C558 1U_0402_6.3V4Z PCIE_VDDR_1 AVSS_USB_2 VSS_30
1 2 P19 PCIE_VDDR_2 C14 AVSS_USB_3 VSS_31 P15
P20 1U_0402_6.3V4Z 2 1 C562 D8 R1
C557 1 0.1U_0402_16V4Z PCIE_VDDR_3 AVSS_USB_4 VSS_32
2 P21 A17 D9 R2

A-LINK I/O
C560 1 0.1U_0402_16V4Z PCIE_VDDR_4 S5_3.3V_1 0.1U_0402_16V4Z C563 AVSS_USB_5 VSS_33
2 R22 PCIE_VDDR_5 S5_3.3V_2 A24 2 1 D11 AVSS_USB_6 VSS_34 R4
R24 B17 0.1U_0402_16V4Z 2 1 C564 D13 R9
PCIE_VDDR_6 S5_3.3V_3 AVSS_USB_7 VSS_35

GROUND
2 0.1U_0402_16V4Z C565 2
R25 PCIE_VDDR_7 S5_3.3V_4 J4 2 1 D14 AVSS_USB_8 VSS_36 R10

3.3V_S5 I/O
S5_3.3V_5 J5 D15 AVSS_USB_9 VSS_37 R12
S5_3.3V_6 L1 E15 AVSS_USB_10 VSS_38 R14
S5_3.3V_7 L2 F12 AVSS_USB_11 VSS_39 T11
+1.2V_SATA L64 F14 T12
L63 +S5_1.2V 0_0603_5% AVSS_USB_12 VSS_40
+1.2VALW G9 AVSS_USB_13 VSS_41 T14
+1.2V_HT 2 1 0_0805_5% AA14 AVDD_SATA_1 H9 AVSS_USB_14 VSS_42 U4
AB18 1U_0402_6.3V4Z 2 1 C569 H17 U14
AVDD_SATA_4 1U_0402_6.3V4Z 2 C570 AVSS_USB_15 VSS_43
AA15 AVDD_SATA_2 1 J9 AVSS_USB_16 VSS_44 V6
2 1 AA17 G2 J11 Y21

CORE S5
AVDD_SATA_3 S5_1.2V_1 AVSS_USB_17 VSS_45

SATA I/O
C566 22U_0805_6.3V6M AC18 G4 J12 AB1
AVDD_SATA_5 S5_1.2V_2 L65 AVSS_USB_18 VSS_46
AD17 AVDD_SATA_6 J14 AVSS_USB_19 VSS_47 AB19
C567 1 2 1U_0402_6.3V4Z AE17 0_0603_5% +1.2VALW J15 AB25
C568 1 AVDD_SATA_7 AVSS_USB_20 VSS_48
2 1U_0402_6.3V4Z K10 AVSS_USB_21 VSS_49 AE1
A10 +1.2_USB 10U_0805_10V4Z 1 2 @
@C573
C573 K12 AE24
C571 1 USB_PHY_1.2V_1 AVSS_USB_22 VSS_50
2 0.1U_0402_16V4Z USB_PHY_1.2V_2 B10 K14 AVSS_USB_23
C572 1 2 0.1U_0402_16V4Z 1U_0402_6.3V4Z 2 1 C574 K15 AVSS_USB_24
PCIE_CK_VSS_9 P23
0.1U_0402_16V4Z 2 1 C575 R16
PCIE_CK_VSS_10
PCIE_CK_VSS_11 R19
+AVDD_USB T17
L66 R346 PCIE_CK_VSS_12
PCIE_CK_VSS_13 U18
+3VALW 2 1 0_0805_5% A16 AVDDTX_0 V5_VREF AE7 +V5_VREF 2 1 1K_0402_5% +5VS H18 PCIE_CK_VSS_1 PCIE_CK_VSS_14 U20
B16 AVDDTX_1 2 2 J17 PCIE_CK_VSS_2 PCIE_CK_VSS_15 V18
C16 J16 +AVDDCK_3.3V C578 C579 D14 J22 V20
C576 1 AVDDTX_2 AVDDCK_3.3V PCIE_CK_VSS_3 PCIE_CK_VSS_16
2 10U_0805_10V4Z D16 AVDDTX_3 1 2 CH751H-40PT_SOD323-2 +3VS K25 PCIE_CK_VSS_4 PCIE_CK_VSS_17 V21
C577 1 2 10U_0805_10V4Z D17 K17 +AVDDCK_1.2V 0.1U_0402_16V4Z 1U_0603_10V4Z M16 W19
PLL

AVDDTX_4 AVDDCK_1.2V 1 1 PCIE_CK_VSS_5 PCIE_CK_VSS_18

E17 AVDDTX_5 M17 PCIE_CK_VSS_6 PCIE_CK_VSS_19 W22
USB I/O

C580 1 2 1U_0402_6.3V4Z F15 E9 +AVDDC M21 W24

C581 1 AVDDRX_0 AVDDC PCIE_CK_VSS_7 PCIE_CK_VSS_20
2 1U_0402_6.3V4Z F17 AVDDRX_1 P16 PCIE_CK_VSS_8 PCIE_CK_VSS_21 W25
F18 L67
C583 1 AVDDRX_2
2 0.1U_0402_16V4Z G15 AVDDRX_3 2 1 0_0603_5% +3VALW F9 AVSSC AVSSCK L17
3 C582 1 3
2 0.1U_0402_16V4Z G17 AVDDRX_4 Part 5 of 5
C584 1 2 0.1U_0402_16V4Z G18 AVDDRX_5 2.2U_0603_6.3V4Z C585 SB710R1@ 218S7EALA11FG_BGA528_SB700
2 1

0.1U_0402_16V4Z 2 1 C586
SB710R1@ 218S7EALA11FG_BGA528_SB700

L68
+AVDDCK_1.2V 2 1 0_0603_5% +1.2V_HT

2.2U_0603_6.3V4Z 2 1 C587

0.1U_0402_16V4Z 2 1 C588

L69
+AVDDCK_3.3V 2 1 0_0603_5% +3VS

2.2U_0603_6.3V4Z 2 1 C589

0.1U_0402_16V4Z 2 1 C590

4 4

/
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 12, 2009 Sheet 23 of 45
A B C D E
 A B C D E

REQUIRED STRAPS NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 LPC_CLK0 LPC_CLK1 RTC_CLK AZ_RST_CD# GP17 GP16

PULL BOOTFAIL USE RESERVED RESERVED ENABLE PCI CLKGEN INTERNAL EC Internal pull up
HIGH TIMER DEBUG MEM BOOT ENABLED RTC ENABLED
H,H = Reserved
ENABLED STRAPS
1 DEFAULT 1
H,L = SPI ROM
EXT. RTC
PULL BOOTFAIL IGNORE DISABLE PCI CLKGEN (PD on X1, EC
LOW TIMER DEBUG MEM BOOT DISABLED apply DISABLED L,H = LPC ROM (Default)
DISABLED STRAPS 32KHz to DEFAULT L,L = FWH ROM
DEFAULT DEFAULT DEFAULT DEFAULT RTC_CLK)

+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW

1
R347 R348 R349 R350 R351 R352 R353 R354 R355 R356
@ @ @ @ @ @ @ @ @
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5%

2
SI2: mount 2.2K
20 PCI_CLK2
20 PCI_CLK3
20 PCI_CLK4
20 PCI_CLK5
20,34 CLK_PCI_EC
20,33 CLK_PCI_SIO2
20 RTC_CLK
21 HDARST#
2 21 GPIO17 2
21 GPIO16
1

1
R357 R358 @ R359 @ R360 R361 R362 R363 R364 R365 R366
@ @
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2.2K_0402_5% 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
2

2
Need to confirm if SB SPI ROM will mount

DEBUG STRAPS
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

USE USE PCI USE ACPI USE IDE USE DEFAULT RESERVED
PULL LONG PLL BCLK PLL PCIE STRAPS
HIGH RESET
3 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT 3

PULL USE BYPASS BYPASS BYPASS IDE USE EEPROM

LOW SHORT PCI PLL ACPI PLL PCIE STRAPS
RESET BCLK

20,28 PCI_AD28
20,28 PCI_AD27
20,28 PCI_AD26
20,28 PCI_AD25
20,28 PCI_AD24
20,28 PCI_AD23
1

R373 R374 R375 R376 R377 R378

@ @ @ @ @ @
2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 24 of 45
A B C D E
 A B C D E

+5VS
< SATA HDD1 Conn > < 16" SATA ODD Conn > 1.1A
JHDD JODD
1 1 1 1 1
1 1 C414 C415 C416 @ C417 C418
GND SATA_TXP1 C512 1 GND
A+ 2 2 0.01U_0402_25V7K SATA_STX_DRX_P1 22 A+ 2 SATA_STX_DRX_P3_16 16inch@ C427 1 2 0.01U_0402_25V7K SATA_STX_DRX_P3
3 SATA_TXN1 C513 1 2 0.01U_0402_25V7K 3 SATA_STX_DRX_N3_16 16inch@ C426 1 2 0.01U_0402_25V7K SATA_STX_DRX_N3 10U_0805_10V4Z 10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K
A- SATA_STX_DRX_N1 22 A- 2 2 2 2 2
GND 4 GND 4
5 SATA_IRX_DTX_N1 C410 1 2 0.01U_0402_25V7K 5 SATA_RXN3_C_16 16inch@ C545 1 2 0.01U_0402_25V7K SATA_RXN3_C
B- SATA_RXN1_C 22 B-
6 SATA_IRX_DTX_P1 C412 1 2 0.01U_0402_25V7K 6 SATA_RXP3_C_16 16inch@ C544 1 2 0.01U_0402_25V7K SATA_RXP3_C
B+ SATA_RXP1_C 22 B+
GND 7 GND 7 Place component's closely ODD CONN.

V33 8 +3VS DP 8
1 1
V33 9 +5V 9 +5VS
V33 10 +5V 10
GND 11 MD 11
GND 12 15 GND GND 12
GND 13 14 GND GND 13
V5 14 +5VS
V5 15
16 @ SANTA_206401-1_RV
V5
GND 17
Reserved 18
GND 19
V12 20
24 GND V12 21
23 GND V12 22

@ OCTEK_SAT-22SO1G_RV < 17" SATA ODD Conn >

+5VS
+5VS
1.2A Place closely JHDD SATA CONN. JODDB
1 1
1 1 1 1 2 2
C387 C388 C389 C390 3
3
4 4
10U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 5
2 2 2 2 5
6 6
7 SATA_IRX_DTX_P3 17inch@ C425 1 2 0.01U_0402_25V7K
7 SATA_RXP3_C 22
8 SATA_IRX_DTX_N3 17inch@ C424 1 2 0.01U_0402_25V7K
8 SATA_RXN3_C 22
9 9
+3VS 10 SATA_TXN3 17inch@ C519 1 2 0.01U_0402_25V7K
10 SATA_STX_DRX_N3 22
SSD HDD need 400mA for 3V(PHISON) +3VS rail reserve for SSD 11 SATA_TXP3 17inch@ C518 1 2 0.01U_0402_25V7K
2 11 SATA_STX_DRX_P3 22 2
12 12
1 1 1 1 GND 13
C336 @ C337 @ C338 @ C339 @ 14
GND
10U_0805_10V4Z 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
2 2 2 2 @ E&T_6905-E12N-00R

< eSATA/USB > 10/22 Add for USB Sleep & Charge M3/M4

+USB_VCCB +USB_VCCB
U47
1

1
1 +USB_VCCB
22 SLP_CHG_M3 1OE#
4 @ R960 @ R961
22 SLP_CHG_M4 10
2OE#
3OE#
75K_0402_1% 43K_0402_1% 1.4A W=60mils
13 U19
4OE# @ C367 1
1 8 2 4.7U_0805_10V4Z
2

USB20_P2_R_U USB20_P2_S_O GND VOUT

2 1A 1B 3 +5VALW 2 VIN VOUT 7
USB20_N2_R_U 5 6 USB20_N2_S_O 3 6
2A 2B @ R962 1 VIN VOUT
9 3A 3B 8 2 100_0402_5% 34 USB_CHG_EN# 4 EN FLG 5 R584 1 2 0_0402_5% USB_OC#2 21,34
1

12 4A 4B 11
@ R963 @ R964 RT9715BGS_SO8
+USB_VCCB 14 7 51K_0402_1% 51K_0402_1%
VCC GND
2
C872 @ SN74CBT3125CPWR_TSSOP14P
2

3 @ 0.1U_0402_16V4Z 3

+3VALW
Reserve for EMI request eSATA/USB Conn
@ R96 1 2 0_0402_5% +USB_VCCB
@ U48 W=60mils
C873
USB20_P2_R_U 1 10 @ 1 2 0.1U_0402_16V4Z 1
1D+ VCC L46 1 1
USB20_N2_R_U 2 9 SLP_CHG# USB20_P2_R 4 3 USB20_P2_R_S + C350 C352 C351
1D- S SLP_CHG# 22 4 3 @ D15
3 8 USB20_P2_R 2 220U_6.3V_M 0.1U_0402_16V7K 1000P_0402_50V7K
21 USB20_P2 2D+ D+ 2 2 2
USB20_N2_R 1 2 USB20_N2_R_S 1
USB20_N2_R 1 2
21 USB20_N2 4 2D- D- 7 3

5 6 WCM-2012-900T_0805 PJDLC05_SOT23-3
GND OE# JESATA
1 2 1 USB
USB20_N2_R_S VBUS
2 D-
@ R95 0_0402_5% USB20_P2_R_S 3
TS3USB221RSER_QFN10_2x1P5~D D+
4 GND
Unmount this C520 1
5 GND
22 SATA_STX_DRX_P2 2 0.01U_0402_25V7K SATA_TXP2 6 A+
C521 1 2 0.01U_0402_25V7K SATA_TXN2 7 ESATA
22 SATA_STX_DRX_N2 A-
8 GND SHIELD 12
C361 2 1 0.01U_0402_25V7K SATA_RXN2 9 13
R112 1 22 SATA_RXN2_C B- SHIELD
USB20_P2 2 0_0402_5% USB20_P2_R
22 SATA_RXP2_C
C357 2 1 0.01U_0402_25V7K SATA_RXP2 10 B+ SHIELD 14
11 GND SHIELD 15
USB20_N2 R113 1 2 0_0402_5% USB20_N2_R
4 @ FOX_3Q318111 4

Mount this to by pass USB switch

SLP_CHG_M3 SLP_CHG_M4 SLP_CHG# FUNCTION Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
Mode 3 HIGH LOW LOW D=1D Schematic, MB LA-5332P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Mode 4 Custom 401721 C
LOW HIGH HIGH D=2D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 25 of 45
A B C D E
 A B C D E

Place Close to Chip UL2 +LAN_VDD12

Close to Pin10,13,30,36
11 PCIE_PTX_C_IRX_P3 CL9 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_P3 20 33 LAN_DO T25 PAD
HSOP LED3/EEDO LAN_DI RL1
LED2/EEDI/AUX 34 1 2 3.6K_0402_5% +3V_LAN 2 2 2 2
11 PCIE_PTX_C_IRX_N3 CL8 1 2 0.1U_0402_16V7K PCIE_PTX_IRX_N3 21 HSON LED1/EESK 35 LAN_SK_LAN_LINK# CL2 CL3 CL4 CL5
32 LAN_CS RL2 2 1 1K_0402_5%
EECS 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
11 PCIE_ITX_C_PRX_P3 15 HSIP LAN_ACTIVITY# 1 1 1 1
LED0 38
11 PCIE_ITX_C_PRX_N3 16 HSIN
RTL8103EL-GR 2 LAN_MDI0+
MDIP0 LAN_MDI0-
16 CLK_PCIE_LAN 17 REFCLK_P MDIN0 3
18 5 LAN_MDI1+
16 CLK_PCIE_LAN# REFCLK_M MDIP1 +LAN_VDD12
6 LAN_MDI1-
MDIN1
16 CLKREQ_LAN 25 CLKREQB NC 8
1 1
NC 9 2
27 11 CL15
12,15,20,27,33,34 PLT_RST# PERSTB NC
NC 12 Close to Pin45
RL3 0.1U_0402_16V4Z
1
1 2 2.49K_0402_1% 46 RSET NC 4

LAN_WAKE_R# 26 48 VCTRL12
34 LAN_WAKE_R# LANWAKEB VCTRL12A
ISOLATEB 28 ISOLATEB +EVDD12
VDDTX 19 +EVDD12
LAN_X1 41 30 +LAN_VDD12 Close to Pin19
LAN_X2 CKXTAL1 DVDD12
42 CKXTAL2 DVDD12 36
DVDD12 13 2 2
10 CL13 CL14
DVDD12
+3V_LAN 39 1U_0402_6.3V4Z 1U_0402_6.3V4Z
@ RL4 NC 1 1
1 2 10K_0402_5% LAN_WAKE_R# 23 NC NC 44
24 NC VCTRL12D 45 +LAN_VDD12
7 GND VDD33 29 +3V_LAN
14 37 +3V_LAN
GND VDD33
31 GND Close to Pin1,37,29
47 GND AVDD33 1
+3VS 40
NC 2 2 2
22 43 CL10 CL11 CL12
GNDTX NC
1

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

RL5 RTL8103EL-GR_LQFP48_7X7 1 1 1

1K_0402_1%
YL1
2

ISOLATEB
2 LAN_X1 LAN_X2 2
2 1 Close to Pin48
1 1 VCTRL12
RL6 CL17 CL18 1 2
25MHz_20pF_6X25000017 CL6 CL7
15K_0402_5% 27P_0402_50V8J 27P_0402_50V8J @
2 2 10U_0805_10V4Z 0.1U_0402_16V4Z
2 1

Place these components 10/21 Add CL26, CL27

UL3
colsed to LAN chip for customer request
LAN_MDI0+ 1 16 RJ45_MIDI0+
CL20 LAN_MDI0- TD+ TX+ RJ45_MIDI0- CL26 RL8
2 TD- TX- 15
2 1 0.01U_0402_25V7K 3 14 1 2 1000P_0402_50V7K 1 2 75_0402_1%
CT CT
4 NC NC 13
CL21 5 12 CL27 RL9
0.01U_0402_25V7K NC NC
2 1 6 CT CT 11 1 2 1000P_0402_50V7K 1 2 75_0402_1% RJ45_GND
LAN_MDI1+ 7 10 RJ45_MIDI1+
LAN_MDI1- RD+ RX+ RJ45_MIDI1-
8 RD- RX- 9

LF-H1201P-2

Add RL11, RL12 for customer request 2

CL19
Change RL7, RL10 from 300 to 150
< LAN Conn >
3 68P_0402_50V8J 3
RL7 1 JLAN
LAN_ACTIVITY# 2 1 150_0402_1% 12
RL11 Yellow LED-

+3V_LAN 2 1 150_0402_1% 11 Yellow LED+

8 PR4-
7 PR4+
RJ45_MIDI1- 6 PR2-
5 PR3-
4 PR3+
RJ45_MIDI1+ 3 PR2+
2
CL22 RJ45_MIDI0- 2 PR1-
SHLD2 14
68P_0402_50V8J RJ45_MIDI0+ 1
RL10 1 PR1+
SHLD1 13
LAN_SK_LAN_LINK#2 1 150_0402_1% 10
RL12 Green LED-
2 1 150_0402_1% 9
+3V_LAN Green LED+
@ TYCO_2068888-1_12P-T
CL23
RJ45_GND 1 2 1000P_1808_3KV7K LANGND
1 1
CL24 CL25

4 0.1U_0402_16V4Z 4.7U_0603_6.3V6K 4
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 26 of 45
A B C D E
 A B C D E

< PCIe Mini Card for WLAN >

+1.5VS +3VS

1 1 1 1 1 1
CM20 CM21 CM22 CM17 CM18 CM19
WLAN@ WLAN@ WLAN@ WLAN@ WLAN@ WLAN@
0.01U_0402_25V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.01U_0402_25V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 2 2 2 2 2

+1.5VS +3VS
1 JWLAN 1
1 1 2 2
3 3 4 4
5 5 6 6
16 CLKREQ_MCARD2# 7 7 8 8
9 9 10 10
16 CLK_PCIE_MCARD2# 11 11 12 12
16 CLK_PCIE_MCARD2 13 13 14 14
15 15 16 16
17 17 18 18
19 19 20 20 WL_OFF# 34
21 22 PLT_RST#
21 22 PLT_RST# 12,15,20,26,33,34
11 PCIE_PTX_C_IRX_N2 23 23 24 24
11 PCIE_PTX_C_IRX_P2 25 25 26 26
27 27 28 28
29 30 SMB_CK_CLK1
29 30 SMB_CK_CLK1 21
31 32 SMB_CK_DAT1 SMB_CK_DAT1 21
11 PCIE_ITX_C_PRX_N2 31 32
11 PCIE_ITX_C_PRX_P2 33 33 34 34
35 36 USB20_N8 USB20_N8 21
35 36 USB20_P8
37 37 38 38 USB20_P8 21
+3VS 39 39 40 40
41 41 42 42
43 43 44 44
45 45 46 46
47 47 48 48
E51_TXD RM6 1 2 0_0402_5% E51_TXD_R 49 50
34 E51_TXD E51_RXD RM7 1 49 50
34 E51_RXD 2 0_0402_5% E51_RXD_R 51 51 52 52
2

53 GND1 GND2 54
RM8
100K_0402_5%
@ FOX_AS0B226-S40N-7F
2 2
1

UN1 +1.5VS_CARD
60mils
+1.5VS 12 1.5Vin 1.5Vout 11 +1.5VS_CARD Imax = 0.75A
14 1.5Vin 1.5Vout 13
1 1
+3VALW 40mils CN5 CN6
+3VS 2 3 +3VS_CARD EXPCARD@ EXPCARD@
EXPCARD@ RN1 CP_USB# 3.3Vin 3.3Vout
1 2 100K_0402_5% 4 3.3Vin 3.3Vout 5 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2
40mils
+3VALW 17 AUX_IN AUX_OUT 15 +3VALW_CARD
PLT_RST# 6 19
SYSRST# OC#
20 8 PERST# +3VS_CARD
34,36,42 SYSON SHDN# PERST#
Imax = 1.35A
30,34,36,39,41 SUSP# 1 STBY# NC 16
1 1
EXP_CPPE# 10 7 CN3 CN4
CPPE# GND EXPCARD@ EXPCARD@
CP_USB# 9 21 10U_0805_10V4Z 0.1U_0402_16V4Z
CPUSB# Thermal_Pad 2 2
RCLKEN 18 RCLKEN
EXPCARD@ TPS2231MRGPR-2

+3VALW_CARD
3 3
Imax = 0.275A
+3VS +3VS +3VS JEXP 1 1
CN1 CN2
1 EXPCARD@ EXPCARD@
GND
1

1 2 10U_0805_10V4Z 0.1U_0402_16V4Z
21 USB20_N5 USB_D- 2 2
@ RN5 @ RN4 CN7 3
21 USB20_P5 USB_D+
@ CP_USB# 4
10K_0402_5% 10K_0402_5% 0.1U_0402_16V4Z CPUSB#
5 RSV
2
6
2

SMB_CK_CLK0 RSV
9,10,16,21 SMB_CK_CLK0 7 SMB_CLK
SMB_CK_DAT0 8
9,10,16,21 SMB_CK_DAT0 SMB_DATA
+1.5VS_CARD 9 +1.5V
10 +1.5V
EC_SWI_R# 11
21,34 EC_SWI_R# WAKE#
5

@ +3VALW_CARD 12
CLKREQ# PERST# +3.3VAUX
2 13
G Vcc

B CLKREQ_NCARD# PERST#
Y 4 CLKREQ_NCARD# 16 +3VS_CARD 14 +3.3V
1 A 15 +3.3V
UN2 CLKREQ# 16
NC7SZ32P5X_NL_SC70-5 EXP_CPPE# CLKREQ#
21 EXP_CPPE# 17
3

CPPE#
1

D @
16 CLK_PCIE_NCARD# 18 REFCLK- GND 31
RCLKEN 2 19 32
16 CLK_PCIE_NCARD REFCLK+ GND
G Q21 20
2N7002_SOT23-3 GND
S 11 PCIE_PTX_C_IRX_N0 21
3

PERn0
11 PCIE_PTX_C_IRX_P0 22 PERp0
23 GND GND 29
11 PCIE_ITX_C_PRX_N0 24 PETn0 GND 30
11 PCIE_ITX_C_PRX_P0 25 PETp0
26 GND
27 GND
4 4
28 GND
< Reserve for test > SANTA_130812-3_LT
@
EXPCARD@ RN6
CLKREQ# 1 2 0_0402_5% CLKREQ_NCARD#

/
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 27 of 45
A B C D E
 A B C D

22K TO 47K PULL-UPS MUST BE PLACED 20,24 PCI_AD[0..31] PCI_AD[0..31]

+S1_VCC +3VS +5VS
ON INTA#, PME#, SERIRQ# & CLKRUN#.

+3VS 20 PCI_CBE#[0..3] PCI_CBE#[0..3] 1 1 1 1 1 1

RB22 CB11 CB12 CB1 CB2 CB3 CB4
1 2 33K_0402_5% CLKRUN# 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z
PCMCIA@ PCMCIA@ PCMCIA@ PCMCIA@ PCMCIA@ PCMCIA@
RB23 2 2 2 2 2 2
1 2 33K_0402_5% SERIRQ

RB24
1 1 2 33K_0402_5% PCI_PIRQA# 1

IDSEL SELECT POWER-ON-STRAPPING +S1_VCC

For EMI UB2
(SEE NOTE & TABLE FOR OPTIONS)
5 VCC/VPP +3.3V 1
CLK_PCI_PCM 6 2
PCMCIA@ RB16 1 VCC/VPP +3.3V
+3VS 2 33K_0402_5% 7 VCC5# +5V 3
2

1 1 1 1 8 VCC3# GND 4
@ RB21 CB5 CB6 CB7 CB8 PCMCIA@ RB17 1 2 33K_0402_5%
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z UB1 OZ2210GN-B1_SO8
10_0402_5% PCMCIA@ PCMCIA@ PCMCIA@ PCMCIA@ PCMCIA@
2 2 2 2
64 124 PCMCIA Socket
1

CORE_VCC VCC5#/VCCD0#/SDATA
1 77 CORE_VCC VCC3#/VCCD1#/SCLK 125
@ CB14 97 123 JPCM
CORE_VCC VPP_PGM/VPPD0/SLATCH
115 CORE_VCC 1 GND
10P_0402_50V8J 35
2 S1_D10 S1_D3 GND
+3VS 1 PCI_VCC D10/CAD31 103 2 DATA3
1 1 1 20 102 S1_D9 S1_CD1# 36
CB9 CB10 CB13 PCI_VCC D9/CAD30 S1_D1 S1_D4 CD1#
33 PCI_VCC D1/CAD29 101 3 DATA4
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 100 S1_D8 S1_D11 37
PCMCIA@ PCMCIA@ PCMCIA@ PCI_AD31 D8/CAD28 S1_D0 S1_D5 DATA11
NOTE: IDSEL SELECTION! 2 2 2
4 AD31 D0/CAD27 99 4 DATA5
PCI_AD30 5 110 S1_A0 S1_D12 38
PCI_AD29 AD30 A0/CAD26 S1_A1 S1_D6 DATA12
6 AD29 A1/CAD25 109 5 DATA6
THIS DEVICE UTILIZES A "SELECTABLE IDSEL" SCHEME. PCI_AD28 7 108 S1_A2 S1_D13 39
PCI_AD27 AD28 A2/CAD24 S1_A3 S1_D7 DATA13
8 AD27 A3/CAD23 106 6 DATA7
PCI_AD26 9 105 S1_A4 S1_D14 40
IDSEL CAN BE CONNECTED INTERNALLY TO ONE OF THREE PCI_AD25 AD26 A4/CAD22 S1_A5 S1_CE1# DATA14
10 AD25 A5/CAD21 104 7 CE1#
PCI AD LINES OR EXTERNAL IDSEL SIGNAL. PCI_AD24 13 118 S1_A6 S1_D15 41
PCI_AD23 AD24 A6/CAD20 S1_A25 S1_A10 DATA15
2 14 AD23 A25/CAD19 95 8 ADD10
2

22K TO 47K PULL-UP & PULL-DOWN RESISTORS ARE PCI_AD22 15 94 S1_A7 S1_CE2# 42
PCI_AD21 AD22 A7/CAD18 S1_A24 S1_OE# CE2#
16 93 9
REQUIRED TO BE CONNECTED TO PINS 123 & 124 TO PCI_AD20 17
AD21 A24/CAD17
75 S1_A17 S1_VS1 43
OE#
SELECT ONE OF THE 4 POSSIBLE IDSEL CONNECTIONS. PCI_AD19 AD20 A17/CAD16 S1_IOWR# S1_A11 VS1#
18 AD19 IOW#/CAD15 73 10 ADD11
PCI_AD18 19 74 S1_A9 S1_IORD# 44
PCI_AD17 AD18 A9/CAD14 S1_IORD# S1_A9 IORD#
THE TABLE BELOW SHOWS THE 4 POSSIBLE COMBINATIONS. 21 AD17 IORD#/CAD13 71 11 ADD9
PCI_AD16 22 72 S1_A11 S1_IOWR# 45
PCI_AD15 AD16 A11/CAD12 S1_OE# S1_A8 IOWR#
28 AD15 OE#/CAD11 70 12 ADD8
CONFIGURING IDSEL TO BE INTERNALLY CONNECTED ALLOWS PCI_AD14 29 69 S1_CE2# S1_A17 46
PCI_AD13 AD14 CE2#/CAD10 S1_A10 S1_A13 ADD17
FOR A FULL PARALLEL POWER MODE. IF AN EXTERNALLY 30 AD13 A10/CAD9 68 13 ADD13
PCI_AD12 31 85 S1_D15 S1_A18 47
CONNECTED IDSEL IS REQUIRED THEN AN INVERTER MUST PCI_AD11 AD12 D15/CAD8 S1_D7 S1_A14 ADD18
34 AD11 D7/CAD7 84 14 ADD14
BE CONNECTED TO VPP_PGM TO CREATE VPP_VCC. PCI_AD10 35 82 S1_D13 S1_A19 48
PCI_AD9 AD10 D13/CAD6 S1_D6 S1_WE# ADD19
36 AD9 D6/CAD5 83 15 WE#
PCI_AD8 37 80 S1_D12 S1_A20 49
PCI_AD7 AD8 D12/CAD4 S1_D5 S1_RDY# ADD20
38 AD7 D5/CAD3 81 16 READY
PCI_AD6 39 78 S1_D11 S1_A21 50
PCI_AD5 AD6 D11/CAD2 S1_D4 ADD21
VCC5# VPP_PGM IDSEL SELECT 40 AD5 D4/CAD1 79 +S1_VCC 17 VCC
PCI_AD4 41 76 S1_D3 51
PCI_AD3 AD4 D3/CAD0 VCC
(124) (123) 42 AD3 18 VPP
PCI_AD2 43 RB18 52
PCI_AD1 AD2 S1_A16 PCMCIA@ 1 VPP
44 AD1 A16/CCLK 107 2 33_0402_5% S1_A16_R 19 ADD16
DOWN DOWN AD18 RB19 PCI_AD0 46 114 S1_A23 S1_A22 53
PCI_AD20 PCMCIA@ 1 AD0 A23/CFRAME# ADD22
2 100_0402_5% IDSEL 127 VPP_VCC/VPPD1/IDSEL A15/CIRDY# 117 S1_A15 S1_A15 20 ADD15
PCI_CBE#3 11 116 S1_A22 S1_A23 54
PCI_CBE#2 C/BE3# A22/CTRDY# S1_A21 S1_A12 ADD23
DOWN UP AD20 12 C/BE2# A21/CDEVSEL# 113 21 ADD12
PCI_CBE#1 49 61 S1_A20 S1_A24 55
PCI_CBE#0 C/BE1# A20/CSTOP# S1_A13 S1_A7 ADD24
50 C/BE0# A13/CPAR 58 22 ADD7
3
UP DOWN AD25 60 S1_A14 S1_A25 56 3
A14/CPERR# S1_WAIT# S1_A6 ADD25
20 CLK_PCI_PCM 26 PCI_CLK WAIT#/CSERR# 91 23 ADD6
27 89 S1_INPACK# S1_VS2 57
20 PCI_DEVSEL# DEVSEL# INPACK#/CREQ# VS2#
UP UP PIN 127 ball F4 20 PCI_FRAME# 23 62 S1_WE# S1_A5 24
FRAME# WE#/CGNT# S1_RDY# S1_RST ADD5
20 PCI_IRDY# 24 IRDY# RDY/IREQ#/CINT# 88 58 RESET
20 PCI_TRDY# 25 59 S1_A19 S1_A4 25
TRDY# A19/CBLOCK# S1_WP S1_WAIT# ADD4
20 PCI_STOP# 47 STOP# WP/CCLKRUN# 87 59 WAIT#
must check IDSEL, PCI_PIRQ#, 20 PCI_PAR 48 119 S1_RST S1_A3 26
PAR RESET/CRST# S1_D2 S1_INPACK# ADD3
D2/RFU 98 60 INPACK#
PCM_SPK# 51 86 S1_D14 S1_A2 27
30 PCM_SPK# PERR#/SPKR_OUT D14/RFU ADD2
63 S1_A18 S1_REG# 61
A18/RFU S1_VS1 S1_A1 REG#
20 PCI_REQ#0 2 REQ# VS1/CVS1 57 28 ADD1
3 121 S1_VS2 S1_BVD2 62
20 PCI_GNT#0 GNT# VS2/CVS2 BVD2
56 S1_CD1# S1_A0 29
CD1#/CCD1# S1_CD2# S1_BVD1 ADD0
20 PCI_RST# 126 RST# CD2#/CCD2# 122 63 BVD1
120 92 S1_BVD2 S1_D0 30
RB20 PME#/RI_OUT# BVD2/LED/CAUDIO S1_BVD1 S1_D8 DATA0
BVD1/STSCHG#/RI#/CSTSCHG 90 64 DATA8
CLKRUN# @ 2 1 0_0402_5% 55 S1_D1 31
20 CLKRUN# MF6 S1_REG# S1_D9 DATA1
54 MF4 REG#CCBE3# 111 65 DATA9 GND 69
53 112 S1_A12 S1_D2 32 70
20,33,34 SERIRQ MF3 A12/CCBE2# DATA2 GND
52 66 S1_A8 S1_D10 66 71
20 PCI_PIRQA# MF0 A8/CCBE1# DATA10 GND
67 S1_CE1# S1_WP 33 72
CE1/CCBE0# S1_CD2# WP GND
67
GND
GND
GND
GND
GND

CD2#
34 GND
68 GND
PCMCIA@ OZ601TN_TQFP128~D
32
45
65
96
128

@ SANTA_130625-3_LT

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401721
Date: Wednesday, February 24, 2010 Sheet 28 of 45
A B C D
 5 4 3 2 1

CC6 RC7
CARD@ 2 1 0.1U_0402_16V4Z CARD@ 2 1 0_0402_5%

UC2

CC4 1
CARD@ 2 AV_PLL
1 0.1U_0402_16V4Z 3 NC
7 NC
+3VS_CR 9
+VCC_3IN1 CARD_3V3
RC2 11
CARD@ 1 D3V3
+3VS 2 0_0603_5% +3VS_CR 33 D3V3 VREG 10
1 1 MS_D4 22 1
CC1 CC5 30 CC7
CARD@ CARD@ NC CARD@
8 3V3_IN 1U_0402_6.3V4Z
D 0.1U_0402_16V4Z 1U_0402_6.3V4Z RST#_R D
44 RST#
RC4 2 2 MODE SEL 2
45 MODE_SEL
+3VALW @ 1 2 0_0603_5% XTLO 47 43
XTLI XTLO XD_CLE_SP19
48 XTLI XD_CE#_SP18 42
XD_ALE_SP17 41
USB20_N4 4 40 SD_DATA2
21 USB20_N4 DM SD_DAT2/XD_RE#_SP16
USB20_P4 5 39 SD_DATA3 RC11 RC18 CC15
21 USB20_P4 DP SD_DAT3/XD_WE#_SP15
confirm that whether can be removed CR_LED# 14 38 CARD@ 1 2 22_0402_5% SDCLK @ 1 2 10_0402_5% @ 10P_0402_50V8J
GPIO0 XD_RDY_SP14
SD_DAT4/XD_WP#/MS_D7_SP13 37
35 RC12 RC17 CC14
SD_DAT5/XD_D0/MS_D6_SP12 SD_MS_CLK
SD_CLK/XD_D1/MS_CLK_SP11 34 CARD@ 1 2 22_0402_5% MSCLK @ 1 2 10_0402_5% @ 10P_0402_50V8J
31 MS_DATA3_SD_DATA6
+3VS_CR SD_DAT6/XD_D7/MS_D3_SP10 MSCD#
MS_INS#_SP9 29
28 MS_DATA2_SD_DATA7
SD_DAT7/XD_D2/MS_D2_SP8 SD_MS_DATA0
SD_DAT0/XD_D6/MS_D0_SP7 27
2

26 MS_DATA1
RC8 SD_DAT1/XD_D3/MS_D1_SP6 MSBS
XD_D5_SP5 25
CARD@ 23 SD_DATA1
100K_0402_5% XD_D4/SD_DAT1_SP4 SDCD#
SD_CD#_SP3 21
RC10 20 SDWP#
1

RST# CARD@ RST#_R SD_WP_SP2

2 1 0_0402_5% XD_CD#_SP1 19
1 EEDI 18
CC8
CARD@ 2 13 XTAL_CTR
1U_0402_6.3V4Z RREF XTAL_CTR
MS_D5 24
2
12 DGND
32 DGND EEDO 15
EECS 16
MODE SEL 6 17
AGND EESK SDCMD
46 AGND SD_CMD 36
1

2
CC13 RC16
C @ 0.1U_0402_16V4Z CARD@ RC14 RC15 C
0_0402_5%
CARD@ CARD@ CARD@ RTS5159-VDD-GR
2 6.19K_0402_1% 0_0402_5%
2

1
< Card Reader LED >
< 3 in 1 Card Reader >
JREAD
1 SDWP#
SD-WP SD_DATA1
SD-DAT1 2
+3VS 3 SD_MS_DATA0
SD-DAT0
SD-GND 4
MS-GND 5
1

6 MSBS
RC13 MS-BS SDCLK
SD-CLK 7
CARD@ 8 MS_DATA1
120_0402_5% MS-DAT1 SD_MS_DATA0
MS-DAT0 9
10 +VCC_3IN1
22

SD-VCC MS_DATA2_SD_DATA7
MS-DAT2 11
DC1 12 1 CARD@ 1 CARD@
CARD@ HT-110UYG-CT_YEL/GRN SD-GND MSCD# CC11 CC10
Vf=2.0V(typ),2.4V(max) MS-INS 13
MS_DATA3_SD_DATA6
MS-DAT3 14
15 SDCMD 0.1U_0402_16V4Z 1U_0402_6.3V4Z
SD-CMD MSCLK 2 2
16
1

MS-SCLK
MS-VCC 17
B SD_DATA3 B
SD-DAT3 18
CR_LED# 19
MS-GND SD_DATA2
22 GND1 SD-DAT2 20
23 21 SDCD#
GND2 SD-CD
CR_LED: Low when card reader is being accessed. @ TAITW_R009-125-LR_RV

< 48MHz > Cost-down option

R C USB AUTO DE-LINK MS FORMATTER Description
RC19 0 NC YES Recommended
CARD@ 1 2 0_0402_5% XTLI
16 CLK_48M_CR
NC 47P YES YES
RC20
+3VS_CR CARD@ 1 2 0_0402_5% XTAL_CTR NC NC Compatible with RTS5158E
NC 680P YES LED ON
< 12MHz >
10K 180P LED ON
CC9
A @ 6P_0402_50V8D XTLI A
10K 680P YES
1

@ YC1
12MHZ_16P_6X12000012
2

CC12
@ 6P_0402_50V8D XTLO Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 12, 2009 Sheet 29 of 45
5 4 3 2 1
 A B C D E

+5VS +VDDA +AVDD +3VS_DVDD

RA1
30mil 2 1 0_0603_5% +3VS

2
1 1
+5VALW @ J2 CA1 CA2

2
JUMP_43X39
0.1U_0402_16V4Z 10U_0805_10V4Z
2 2

1
UA1
2
CA9 4.75V RA3 40mil

1
@ 1 5 2 2 1 0_0603_5%
1U_0402_6.3V4Z VIN VOUT
1 1 1 1 1 2
2 @ CA10 CA3 CA4 CA5 CA6 CA53
GND @ CA11
1 1U_0402_6.3V4Z 1 1 2
27,34,36,39,41 SUSP# 3 SHDN# BP 4 2 1 0.22U_0402_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 100P_0402_50V8J CA7 CA8 CA52
2 2 2 2 1
1 0.1U_0402_16V4Z 10U_0805_10V4Z 100P_0402_50V8J 1
@ APL5151-475BC-TRL_SOT23-5 2 2 1

25

38

9
UA2

DVDD
AVDD1

AVDD2

DVDD_IO
14 LINE2-L LOUT1_L 35 AMP_SPK_L 31
CA45 1 2 100P_0402_50V8J 15 36
LINE2-R LOUT1_R AMP_SPK_R 31

31 MIC2_L 16 MIC2_L LOUT2_L 39

Int. Mic 17 41
31 MIC2_R MIC2_R LOUT2_R
CA46 1 2 100P_0402_50V8J 23 48
LINE1_L SPDIFO1
CA47 1 2 100P_0402_50V8J 24 45
LINE1_R SPDIFO2
21 33 HPL RA5 1 2 63.4_0402_1%
31 MIC1_C_L MIC1_L HPOUT_L HP_L 31
Ext. Mic 22 32 HPR RA6 1 2 63.4_0402_1%
31 MIC1_C_R MIC1_R HPOUT_R HP_R 31
CA14 CA48 1 2 100P_0402_50V8J
1 2 100P_0402_50V8J MONO_IN 12 37
BEEP_IN MONO_OUT

21 HDA_BITCLK_CODEC 6 BITCLK DMIC_CLK1/2 46

2

5 44 CA51
21 HDA_SDOUT_CODEC SDATA_OUT DMIC_CLK3/4
RA31 RA7 2 1 1U_0402_6.3V4Z
2 HDA_SDIN0_R 2
21 HDA_SDIN0 2 1 33_0402_5% 8 SDATA_IN LINE2_VREFO 20
10_0402_5% +MIC1_VREFO
< EMI require > 11 18
1

RESET# LINE1_VREFO CA12

1
CA34 10 28
10mil 2 1 1U_0402_6.3V4Z
21 HDA_SYNC_CODEC SYNC MIC1_VREFO
10P_0402_50V8J 19
10mil
2 MIC2_VREFO +MIC2_VREFO
2 CA16
22 SPK_SEL GPIO0/DMIC_DATA1/2
CPVREF 31 1 2 2.2U_0603_6.3V6K
3 GPIO1/DMIC_DATA3/4
27 AC_VREF
+3VS SENSE_A VREF
13 SENSE A
40 AC_JDREF 1 1 2
SENSE_B JDREF CA18 CA19 CA50
34 SENSE B
1

1
30 CA17 1 2 2
@ RA37 MUTE# RA4 CBN
31 MUTE# 1 2 0_0402_5% 47 EAPD
RA10 CA49 10U_0805_10V4Z 0.1U_0402_16V4Z 100P_0402_50V8J
2.2U_0603_6.3V6K 2 2 1
< EMI require > CBP 29

20K_0402_1%

100P_0402_50V8J
4.7K_0402_5% 1 43
@ NC 1
2

2
CA58 4 26
21 HDA_RST#_CODEC DVSS AVSS1
2 GPIO0-->SPK_SEL HIGH: HARMAN 10P_0402_50V8J 7 42
CA42 2 DVSS AVSS2
@
LOW: NO-BRAND
0.01U_0402_25V7K ALC272-GR_LQFP48
1 DGND need to re-link ALC272 AGND
Reserve for EMI require A2 version
CA54 1 2 0.1U_0603_50V7K

CA55 1 2 0.1U_0603_50V7K
3 CA56 3
1 2 0.1U_0603_50V7K

CA57 1 2 0.1U_0603_50V7K

RA15 2 0_0603_5%
< SENSE_A & SENSE_B, place close to chip > 1

RA18
31 MIC_SENSE 1 2 20K_0402_1% SENSE_A

RA16
1 2 5.1K_0402_1% SENSE_B
31 NBA_PLUG < MONO_IN SOURCE >
RA17
MIC@ 1 2 20K_0402_1%

RA8
EC Beep 34 EC_BEEP 1 2 47K_0402_5%

RA9 CA15
Sense Pin Impedance Codec Signals Function PCI Beep 21 1 2 47K_0402_5% 1 2 0.1U_0402_16V4Z MONO_IN
SB_SPKR
39.2K PORT-A (PIN 39, 41) RA19
CardBus Beep 28 PCMCIA@ 1 2 47K_0402_5%
PCM_SPK#

1
20K PORT-B (PIN 21, 22) Ext. MIC RA11
1
CA20
SENSE A 10K_0402_5% 0.1U_0402_16V4Z
10K PORT-C (PIN 23, 24) FM tuner 2

2
4 4

5.1K PORT-D (PIN 35, 36) SPK out

39.2K PORT-E (PIN 14, 15)

20K PORT-F (PIN 16, 17) /

Int. MIC Security Classification Compal Secret Data Compal Electronics, Inc.
SENSE B
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
10K PORT-H (PIN 37) Schematic, MB LA-5332P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
5.1K PORT-I (PIN 32, 33) Custom 401721 C
Headphone out DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 30 of 45
A B C D E
 A B C D E

< TPA6017 Medium Range Amplifier > < Ext. Mic >
+5VS RA20 DA1
2 1 4.7K_0402_5% 1 2 CH751H-40PT_SOD323-2 +MIC1_VREFO
RA21
1 1 1 CA21 2 1 4.7U_0805_10V4Z 2 1 1K_0402_5% MIC1_L
30 MIC1_C_L
CA23 CA24 CA25
CA22 2 1 4.7U_0805_10V4Z 2 1 1K_0402_5% MIC1_R
30 MIC1_C_R
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z RA22 RA23 DA2
2 2 2
2 1 4.7K_0402_5% 1 2 CH751H-40PT_SOD323-2 +MIC1_VREFO

10 dB MIC@ RA24 1 4.7K_0402_5%

< Int. Mic > 2 +MIC2_VREFO
1 +5VS 1

16
15
6

1
UA3
RA27 RA28 close to JLVDS

VDD
PVDD1
PVDD2
@ @
100K_0402_5% 100K_0402_5% RA38
CA29 1 2 0_0402_5% INT_MIC_R 18

2
0.033U_0402_16V7K 7 2
RIN+ GAIN0

GAIN1 3
CA30
30 AMP_SPK_R 0.033U_0402_16V7K LINE_C_OUTR 17
RIN-

1
18 SPKR+ close to JMIC
ROUT+ @ RA29 RA30 DA3
PACDN042Y3R_SOT23-3
CA31 14 SPKR- 100K_0402_5% 100K_0402_5% 3
0.033U_0402_16V7K ROUT-
9 1

2
LIN+
2
4 SPKL+
CA32 LOUT+ MIC@ MIC@
30 AMP_SPK_L 0.033U_0402_16V7K LINE_C_OUTL 5 CA26 RA25 @ JMIC
LIN- SPKL- INT_MIC
LOUT- 8 30 MIC2_L 2 1 1U_0402_6.3V4Z 2 1 1K_0402_5% 1 1 NC1 3
2 2 NC2 4

CA27 @ J3 ACES_85204-0200N
30 MIC2_R 2 1 1U_0402_6.3V4Z 2 1 1K_0402_5% 1 2 220P_0402_50V7K 2 2 1 1
12 Keep 10 mil width CA28 RA26
NC MIC@ MIC@
AMP_BYPASS JUMP_43X39
BYPASS 10
30 MUTE# 19 SHUTDOWN close to Codec
2
CA33
GND5
GND1
GND2
GND3
GND4

2 0.47U_0603_10V7K 2
1
TPA6017A2_TSSOP20
21
20
13
11
1

< Speaker Connector >

DA4
GAIN0 GAIN1 Av(db) Rin(ohm) PACDN042Y3R_SOT23-3
2
0 0 6 90K 1
3
0 1 10 70K JSPK
SPKL+ LA3 1 2 FBMA-L11-160808-800LMT_0603 SPK_L1 1
SPKL- LA4 1 FBMA-L11-160808-800LMT_0603 SPK_L2 1
1 0 15.6 45K 2 2 2
SPKR+ LA5 1 2 FBMA-L11-160808-800LMT_0603 SPK_R1 3
SPKR- LA6 1 FBMA-L11-160808-800LMT_0603 SPK_R2 3
1 1 21.6 25K 2 4 4
3 @ ACES_85204-0400N
1
2
< Volume Control > DA5
PACDN042Y3R_SOT23-3
+3VS
1

RA32 < HeadPhone JACK > 1

100K_0402_5% CA43 0.1U_0402_16V4Z JLINE
< EMI require > 5
2

2
1 30 NBA_PLUG 4
3 3
CA36 LA7 1 2 KC FBM-L11-160808-121LMT 0603 HP_R_L 3
0.1U_0402_16V4Z 30 HP_R
6
+3VS 2 LA8 1 HP_L_L
30 HP_L 2 KC FBM-L11-160808-121LMT 0603 2
1

CA35 @ FOX_JA6333L-B3T0-7F
1

0.1U_0402_16V4Z 3
RA33 RA34 +3VS 1 2 1
5

SW2 2
10K_0402_5% 10K_0402_5%
DIP

UA4 +3VS @DA6

@ DA6
2

RA35 PACDN042Y3R_SOT23-3
P

NC

A 2 1 2 10K_0402_5% 2 A Y 4
G

74LVC1G14GW_SOT353-5 UA5
1 1 14
< Ext.MIC/LINE IN JACK >
3

COM CD1# VCC

2 D1 CD2# 13
RA36 3 12 1
CP1 D2
B 3 1 2 10K_0402_5% 4 SD1# CP2 11
5 10 CA44 0.1U_0402_16V4Z JEXMIC
Q1 SD2#
1 1 6 Q1# Q2 09 1 2
< EMI require > 5
DIP

CA37 CA38 7 08 CA39

GND Q2# 0.1U_0402_16V4Z
30 MIC_SENSE 4
SW_XRE094_3P 0.01U_0402_25V7K 0.01U_0402_25V7K 74LCX74MTC_TSSOP14
4

2 2 2 MIC1_R LA9 1 2 KC FBM-L11-160808-121LMT 0603 MIC1_L_R 3

6
MIC1_L LA10 1 2 KC FBM-L11-160808-121LMT 0603 MIC1_L_L 2
ENCODER_DIR 34 1
ENCODER_PULSE 34
@ FOX_JA6333L-B3T0-7F
3 1 1
4 CA40 CA41 4
1
2 @ 100P_0402_50V8J @ 100P_0402_50V8J

@ DA7 2 2
PACDN042Y3R_SOT23-3

/
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 31 of 45
A B C D E
 A B C D E

< USB Right-side Board, USB port 0,1 > < BlueTooth Interface, USB port6 >

+5VALW +USB_VCCA +3VS +3VS

1.4A W=60mils

2
U25 2
1 8 C438 1 2 4.7U_0805_10V4Z R432 C481 C482
GND VOUT BT@ BT@ BT@
2 VIN VOUT 7
3 6 100K_0402_5% 0.1U_0402_16V7K 0.1U_0402_16V4Z
USB_EN# VIN VOUT R422 1 1
34 USB_EN# 4 5 2 0_0402_5% USB_OC#0 21,34

1
EN FLG

3
S
1 R441 BT@ 1
G
RT9715BGS_SO8 34 BT_PWR# BT@ 1 2 47K_0402_5% 2
1 Q25
C196 AO3413_SOT23
<
R
e
s
e
r
v
e
f
o
r
E
M
I
r
e
q
u
e
s
t
>
D

1
BT@
0.01U_0402_25V7K
2
+BT_VCC

+USB_VCCA Inrush current = 0A

@R107
@ R107
1 2 0_0402_5% W=60mils JUSBB
1 1
2
3
2
3
< Bluetooth Connector > JBT
4 4 12 GND2
L50 5 11
5 GND1
21 USB20_N0 1 1 2 2 6 6
USB20_N0_R 7
USB20_P0_R 7
8 8
21 USB20_P0 4 4 3 3 9 9 10 10
USB20_N1_R 10 USB20_P6 9
10 21 USB20_P6 9
WCM-2012-900T_0805 USB20_P1_R 11 USB20_N6 8
11 21 USB20_N6 8
12 12 7 7
13 BT@ R440 22 BT_DET# BT@ R437 1 2 0_0402_5% 6
@R108
@ R108 GND BT_RESET# 6
14 GND 34 BT_RST# 1 2 0_0402_5% 5 5
1 2 0_0402_5% 4
@ E&T_6905-E12N-00R 4
+BT_VCC 3 3
(MAX=200mA) +3VS @ R438 1 2 4.7K_0402_5% 2
@R109
@ R109 2
1 1

2
1 2 0_0402_5% 1
C480 C483 C479 BT@ R439 @ ACES_87213-1000G
2 @ BT@ BT@ 2
0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7K_0402_5%
2

1
L51
21 USB20_N1 1 1 2 2

21 USB20_P1 4 4 3 3

WCM-2012-900T_0805

@R110
@ R110
1 2 0_0402_5%

3 3

< Finger Printer, USB port 7 >

R119 C468
+3VS FP@ 1 2 0_0603_5% +3VS_FP FP@ 1 2 0.1U_0402_16V4Z

JFP
4 4
1 1
USB20_N7 2
21 USB20_N7 2
USB20_P7 3 5
21 USB20_P7 3 GND
FP@ R118 1 2 0_0603_5% 4 6
4 GND
@ ACES_85201-04051

/
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 32 of 45
A B C D E
 <
S
P
I
F
l
a
s
h
8
M
b
*
1
>
A B C D E

< MDC 1.5 Conn >

+3VL
20mils U46
8 VCC VSS 4
1 1 1
C786 C607 C608 3
@ @ W
0.1U_0402_16V4Z 10P_0402_50V8J 10P_0402_50V8J 7
2 2 2 HOLD
SPI_CS# 1
34 SPI_CS# S
EC_SPICLK 6
1 34 SPI_CLK C 1

34 EC_SO_SPI_SI 5 D Q 2 EC_SI_SPI_SO 34
JMDC
MX25L8005M2C-15G
1 GND1 RES0 2 +3VALW
21 HDA_SDOUT_MDC HDA_SDOUT_MDC 3 4
IAC_SDATA_OUT RES1
5 GND2 3.3V 6 +3VALW
R518 C606 21 HDA_SYNC_MDC HDA_SYNC_MDC 7 8
EC_SPICLK 1 IAC_SYNC GND3
2 10_0402_5% 1 2 10P_0402_50V8J 21 HDA_SDIN1 MDC@ R495 1 2 33_0402_5% HDA_SDIN1_MDC 9
IAC_SDATA_IN GND4 10
21 HDA_RST#_MDC 11 IAC_RESET# IAC_BITCLK 12 HDA_BITCLK_MDC 21

1
R496

GND
GND
GND
GND
GND
GND
@
10_0402_5%
MDC@ ACES_88018-124G

13
14
15
16
17
18

2
< LPC Debug Port > Connector for MDC Rev1.5 @
2
C777

Please place the PAD under DDR DIMM. 10P_0402_50V8J

1

+3VS H1

6 5

R622
SERIRQ 1 2 0_0402_5% 7 4 PLT_RST# +3VALW
20,28,34 SERIRQ PLT_RST# 12,15,20,26,27,34

LPC_AD3 8 3 LPC_AD2 1 1 1
2 20,34 LPC_AD3 LPC_AD2 20,34 2
MDC@ MDC@ MDC@
C778 C779 C780
LPC_AD1 9 2 LPC_AD0 1000P_0402_50V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z
20,34 LPC_AD1 LPC_AD0 20,34 2 2 2

LPC_FRAME# 10 1
20,34 LPC_FRAME# CLK_PCI_SIO2 20,24
2

R634
@ DEBUG_PAD
22_0402_5%
1

2
C639

22P_0402_50V8J
1

< KEYBOARD CONN 16" > < KEYBOARD CONN 17" > < For EMI >
KSO2 C725 1 2 100P_0402_50V8J
KSO1 C717 1 2 100P_0402_50V8J
JKB1 R502 JKB2 KSO0 C721 1 2 100P_0402_50V8J
1 2 +3VS KSO4 C609 1 2 100P_0402_50V8J
34 KSO16 34 KSO16 KSO3 C724 100P_0402_50V8J
33 33 1 2
300_0402_5% 1 1 1 KSO5 C728 1 2 100P_0402_50V8J
32 KSO17 C781 C782 C783 32 KSO17 KSO14 C730 100P_0402_50V8J
31 31 1 2
3 KSO6 C715 100P_0402_50V8J 3
30 30 1 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z KSO7 C732 1 2 100P_0402_50V8J
29 KSO2 2 2 2 29 KSO2 KSO13 C733 100P_0402_50V8J
28 28 1 2
KSO1 KSO1 KSO8 C740 1 2 100P_0402_50V8J
27 KSO0 27 KSO0 KSO9 C737 100P_0402_50V8J
26 26 1 2
KSO4 KSO4 KSO10 C729 1 2 100P_0402_50V8J
25
24
KSO3
KSO5
< For EMI > 25
24
KSO3
KSO5
KSO11
KSO12
C738
C718
1 2 100P_0402_50V8J
100P_0402_50V8J
23 23 1 2
KSO14 KSO14 KSO15 C736 1 2 100P_0402_50V8J
22 KSO6 22 KSO6 KSI7 C716 100P_0402_50V8J
21 21 1 2
KSO7 KSO7 KSI2 C741 1 2 100P_0402_50V8J
20 KSO13 20 KSO13 KSI3 C726 100P_0402_50V8J
19 19 1 2
KSO8 KSO8 KSI4 C723 1 2 100P_0402_50V8J
18 KSO9 18 KSO9 KSI0 C731 100P_0402_50V8J
17 17 1 2
KSO10 KSO10 KSI5 C739 1 2 100P_0402_50V8J
16 KSO11 16 KSO11 KSI6 C735 100P_0402_50V8J
15 15 1 2
KSO12 KSO12 KSI1 C734 1 2 100P_0402_50V8J
14 KSO15 14 KSO15 CAPS_LED# C722 100P_0402_50V8J
13 13 1 2
KSI7 KSI7 NUM_LED# C714 1 2 100P_0402_50V8J
12 KSI2 12 KSI2
11 KSI3 11 KSI3
10 KSI4 10 KSI4
9 KSI0 9 KSI0
8 KSI5 8 KSI5
7 KSI6 7 KSI6 KSO16 C870 1
6 6 2 100P_0402_50V8J
KSI1 R509 KSI1 KSO17 C871 1 2 100P_0402_50V8J
5 5
4 2 1 +3VS 4 CAPS_LED#
3 CAPS_LED# 34 3
300_0402_5%
2 2 NUM_LED#
1 NUM_LED# 34 1
@ ACES_88170-3400 @ ACES_88170-3400
4 4

KSI[0..7]
KSI[0..7] 34,35
KSO[0..17] /
KSO[0..17] 34,35 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 33 of 45
A B C D E
 A B C D E

+3VL +3VL_EC +EC_AVCC

L25
2 1 0_0603_5%

111
125
22
33
96

67
9
U33

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
GATEA20 1 21 INVT_PWM
21 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM 18
Reserve for EMI request KB_RST# 2 23
1 21 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_BEEP 30 1
SERIRQ 3 26
20,28,33 SERIRQ SERIRQ# FANPWM1/GPIO12
LPC_FRAME# 4 27 ACOFF C812
20,33 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 39
@ C810
@C810 @ R530 20,33 LPC_AD3 LPC_AD3 5 1 2 100P_0402_50V8J ECAGND
LAD3
1 2 15P_0402_50V8J1 2 33_0402_5% 20,33 LPC_AD2 LPC_AD2 7 LAD2 PWM Output
20,33 LPC_AD1 LPC_AD1 8 63 BATT_TEMPA
LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMPA 38
LPC_AD0 R145
20,33 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I/AD2/GPIO3A 65 1 2 100K_0402_5% ADP_I 39
CLK_PCI_EC 12 AD Input 66
20,24 CLK_PCI_EC PCICLK AD3/GPIO3B ADP_V 39
PLT_RST# 13 75 C154
12,15,20,26,27,33 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
+3VL R533 1 2 47K_0402_5% ECRST# 37 76 1 2 0.22U_0603_16V4Z
EC_SCI# ECRST# SELIO2#/AD5/GPIO43
21 EC_SCI# 20 SCI#/GPIO0E
35 WL_BT_LED# WL_BT_LED# 38 CLKRUN#/GPIO1D
DAC_BRIG/DA0/GPIO3C 68 DAC_BRIG 18
C811 2 1 0.1U_0402_16V4Z 70 EN_DFAN1
EN_DFAN1/DA1/GPIO3D EN_DFAN1 5
DA Output 71 IREF
IREF/DA2/GPIO3E IREF 39
KSI0 55 72 CHGVADJ
KSI0/GPIO30 DA3/GPIO3F CHGVADJ 39
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
KSI3 58 83
KSI3/GPIO33 PSCLK1/GPIO4A USB_CHG_EN# 25
KSI4 59 84
KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# 32
KSI5 60 85 ENCODER_DIR
KSI5/GPIO35 PSCLK2/GPIO4C ENCODER_DIR 31
KSI6 61 PS2 Interface 86 ENCODER_PULSE
KSI6/GPIO36 PSDAT2/GPIO4D ENCODER_PULSE 31
KSI7 62 87 TP_CLK
KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK 35
39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA 35
KSO1 40
KSI[0..7] KSO2 KSO1/GPIO21
33,35 KSI[0..7] 41 KSO2/GPIO22
KSO3 42 97 BT_RST#
KSO[0..17] KSO3/GPIO23 SDICS#/GPXOA00 BT_RST# 32
KSO4 43 98 WOL_EN#
33,35 KSO[0..17] KSO4/GPIO24 SDICLK/GPXOA01 WOL_EN# 36
KSO5 USB_OC#2
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 USB_OC#2 21,25
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 VGATE 43
KSO7 46 SPI Device Interface
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
2 KSO9 2
48 KSO9/GPIO29 SPIDI/RD# 119 EC_SI_SPI_SO 33
KSO10 49 120
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 33
KSO11 50 SPI Flash ROM 126
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK 33
KSO12 51 128
KSO12/GPIO2C SPICS# SPI_CS# 33
KSO13 52
EC_SMB_DA2 R330 1 KSO14 KSO13/GPIO2D
2 2.2K_0402_5% +3VS 53 KSO14/GPIO2E
KSO15 54 73
KSO16 KSO15/GPIO2F CIR_RX/GPIO40 CEC_INT#
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 CEC_INT# 19
EC_SMB_CK2 R326 1 2 2.2K_0402_5% KSO17 82 89 FSTCHG
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 39
90 BATT_FULL_LED#
BATT_CHGI_LED#/GPIO52 BATT_FULL_LED# 35
CAPS_LED#/GPIO53 91 CAPS_LED# 33
EC_SMB_DA1 R70 1 2 2.2K_0402_5% +3VL EC_SMB_CK1 77 GPIO 92 BATT_LOW_LED#
19,38 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_LOW_LED# 35
EC_SMB_DA1 78 93 PWR_ON_LED#
19,38 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_ON_LED# 35
EC_SMB_CK2 79 SM Bus 95 SYSON
7,35 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 27,36,42
EC_SMB_CK1 R77 1 2 2.2K_0402_5% EC_SMB_DA2 80 121 VR_ON
7,35 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 43
127 ACIN_D
AC_IN/GPIO59 R541
CEC_INT# R563 2 1 100K_0402_5% 2 1 10K_0402_5%
PM_SLP_S3# 6 100 EC_RSMRST#
21 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 21
PM_SLP_S5# 14 101
21 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 21
EC_SMI# 15 102
21 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 35,36
TP_CLK R534 1 2 4.7K_0402_5% +5VS LID_SW# 16 103 EC_SWI#
35 LID_SW# LID_SW#/GPIO0A EC_SWI#/GPXO06
17 104 SB_PWRGD
SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# SB_PWRGD 21,43
18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# 18
TP_DATA R535 1 2 4.7K_0402_5% BT_PWR# 19 GPIO 106 WL_OFF#
32 BT_PWR# EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# 27
25 EC_THERM#/GPIO11 GPXO10 107 HDPINT 35
FAN_SPEED1 28 108
5 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11
36 VLDT_EN 29 FANFB2/GPIO15
E51_TXD 30
27 E51_TXD E51_RXD EC_TX/GPIO16
27 E51_RXD 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 HDPACT 35
SYSON R539 1 2 10K_0402_5% ON/OFFBTN# 32 112 ENBKL
35 ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXID2 UMA_ENBKL 12
PWR_SUSP_LED# 34 114 HDPLOC HDPLOC 35
3 35 PWR_SUSP_LED# NUM_LED# PWR_LED#/GPIO19 GPXID3 3
33 NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115 EC_THERM# 22
SUSP# R536 1 2 10K_0402_5% 116 SUSP#
GPXID5 SUSP# 27,30,36,39,41
117 PBTN_OUT#
GPXID6 PBTN_OUT# 21
C813 118 LAN_WAKE#
LID_SW# R538 2 GPXID7
1 100K_0402_5% +3VALW 1 2 15P_0402_50V8J CRY1 122 XCLK1
123 XCLK0 V18R 124 C814 2 1 4.7U_0805_10V4Z
1

AGND
Y7
GND
GND
GND
GND
GND
ON/OFFBTN# R513 2 1 100K_0402_5% +3VL 2 1 @ R24
NC OSC @ R545 LAN_WAKE# 0_0402_5% LAN_WAKE_R#
1 2 LAN_WAKE_R# 26
3 4 20M_0402_5% KB926QFD3_LQFP128_14X14
11
24
35
94
113

69
KSO1 R947 NC OSC
2 1 47K_0402_5% @ R33
2

32.768KHZ_12.5PF_9H03200413 EC_SWI# 1 2 0_0402_5% EC_SWI_R#

EC_SWI_R# 21,27
C815
ECAGND

KSO2 R948 2 1 47K_0402_5% 1 2 15P_0402_50V8J CRY2

Add for KB926D2 issue. Please refer to KB926D-AN1-100 for detail +3VL_EC L80 1 2 0_0603_5%
R34
C816 LAN_WAKE_R# 1 2 0_0402_5% EC_SWI_R#
+EC_AVCC 1 2 0.1U_0402_16V4Z L81 2 1 0_0603_5%

R35
+3VL_EC LAN_WAKE# 1 2 0_0402_5%
USB_OC#0 21,32

1 1 1 1 1
C805 C806 C807 C808 C809
4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z 1000P_0402_50V7K 4
R560 2 2 2 2 2
1 2 150K_0402_5% +3VL

ACIN_D 2 1 D33 /
CH751H-40PT_SOD323-2
ACIN 22,35,37 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

C326
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
2 1 100P_0402_50V8J AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 34 of 45
A B C D E
 A B C D E

< G - Sensor > @R689

@ R689 2 1 0_0603_5%
< Power Button for Debug > < Screw Hole > +5VS
+3VS +3VS_HDP
+3VS_HDP
DG1
debug phase using H15 H16 H17 H18 H19 H20 G@ 1 2 CH751H-40PT_SOD323-2
2 2
CG12 CG13
@ SW5 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 G@ G@

1
1 3 ON/OFFBTN# @ @ @ @ @ @ 1U_0402_6.3V4Z G@ 1U_0402_6.3V4Z
ON/OFFBTN# 34 1 UG3 1
TOP side
2 4 1 IN OUT 5
H21 H22 H23 H24 H25 H26
SMT1-05-A_4P 2

6
5
GND CG14
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 +5VS 3 4 @ 2 1 0.22U_0402_10V4Z

1
@ @ @ @ @ @ SHDN# BYP
1 G9191-330T1U_SOT23-5 1

H27 H28 H29 H30 H31 H32

G_1st@ UG1
H_3P0 H_3P0 H_3P1N H_3P2 H_3P2 H_3P7 +3VS_HDP 2 Vdd1 3 VOUTX G_1st@ CG1 1 2 0.033U_0402_16V7K

1
@ @ @ @ @ @ Voutx VOUTY G_1st@ CG2
12 Vdd2 Vouty 5 1 2 0.033U_0402_16V7K
7 VOUTZ G_1st@ CG3 1 2 0.033U_0402_16V7K
Voutz
H33 H34 H35 H36 H37 SELF_TEST 4 10
ST NC1
51_ON# 37 6 PD NC2 11
8 FS NC3 14
1

D H_3P7 H_3P7 H_3P7 H_3P7 H_3P7 15

1
Q19 @ @ @ @ @ NC4
34,36 EC_ON 2 NC5 16
G
2

S 2N7002_SOT23-3 +3VS_HDP 9 1
3

R514 H40 H41 H42 H47 Rev GND1

GND2 13

10K_0402_5% TSH35TR_LGA16
H_3P1X4P1N H_3P0N H_3P0 H_3P0
1

1
@ @ @ @
G_2nd@ UG4
G_2nd@ CG649 2 1 0.1U_0402_16V4Z VOUTX 2 XOUT 6 +3VS_HDP
VDD
G_2nd@ CG642 2 1 0.1U_0402_16V4Z VOUTY 3 YOUT
PCB Fedical Mark PAD NC 1
G_2nd@ CG641 2 1 0.1U_0402_16V4Z VOUTZ 4 8
FD1 FD2 FD3 FD4 ZOUT NC
11
< DC-IN LED > MDC: H30, H31 9
NC
12
@ @ @ @ 0G-DET NC
ACIN 22,34,37 VGA: H38, H39 14
NC
CPU: H32, H33, H34, H35 +3VS_HDP 7

1
SLEEP#
2

D54
G

Mini Card : H36, H37 10

2 R515 SELF_TEST G-SELECT 2
Others: H15, H16, H17, H18, H19, H20, H21, H22, 13 ST VSS 5
+3VALW 1 2 120_0402_5% 2 1 1 3 H23, H24, H25, H26, H27, H28, H29, H40, H47
MMA7360LR2_LGA14
D

HT-110UYG-CT_YEL/GRN
2N7002_SOT23-3
Vf=2.0V (typ), 2.4 V (max), If = 30mA (max) Q20
< LID Switch > G@ UG2
HDPACT 34

2
17inch@ U34 1 11
+3VALW 7,34 EC_SMB_CK2 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01
APX9132ATI-TRL_SOT23-3 G@ RG9
Remove WiMAX LED control circuit 47K_0402_5%
2 3 SELF_TEST 2 12

GND
LID_SW# 34

1
VDD VOUT P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11#
G@ RG3
1 1 2 1 4.7K_0402_5% 3 13 HDPLOC 34

1
C645 17inch@ 17inch@ C647 RESET# P1_4/TXD0

2
G@ RG4
0.1U_0402_16V4Z 10P_0402_50V8J 2 1 4.7K_0402_5% 4 14
2 2 XOUT/P4_7 P1_3/KI3#/AN11/TZOUT G@ RG10
47K_0402_5%
5 15 VOUTZ

1
VSS/AVSS P1_2/KI2#/AN10/CMP0_2
G@ RG5
16inch@ U36 +3VS_HDP 2 1 4.7K_0402_5% 6 16
+3VALW XIN/P4_6 P4_2/VREF +3VS_HDP
APX9132ATI-TRL_SOT23-3 1

2 3 7 17 VOUTX G@ CG6
GND

VDD VOUT VCC/AVCC P1_1/KI1#/AN9/CMP0_1 0.1U_0402_16V4Z

1 1 2
G@ G@ G@ RG6
1 1 CG7 CG8 2 1 4.7K_0402_5% 8 18 VOUTY
1

C646 16inch@ 16inch@ C648 0.1U_0402_16V4Z 0.1U_0402_16V4Z MODE P1_0/KI0#/AN8/CMP0_0

2 2 G@ RG7
0.1U_0402_16V4Z 10P_0402_50V8J HDPINT 2 1 1K_0402_5% 9 19
3 2 2 34 HDPINT P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0 3

10 P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 20 EC_SMB_DA2 7,34

< HDD LED > R5F211B4D34SP

SATA_LED# 22
2

R546
+3VS 2 1 10K_0402_5% 6 1
< EMI reserve > 1.C199 : U19 < Touch/B Connector > < For EMI > C686
ON/OFFBTN# @ 1 2 220P_0402_50V7K
2.C200 : PU5
5

Q18A +5VS
R548 2N7002DW-T/R7_SOT363-6 C199 1 2 0.22U_0603_16V4Z 3.Top side of PU12 for noise bounce. JTOUCH C699
+5VALW
+3VS 1 2 120_0402_5%2 1 3 4 4.C202 : U25 1 EC_REVBTN# @ 1 2 220P_0402_50V7K
C200 1 1
2 0.22U_0603_16V4Z 5.C203 : PU9 34 TP_CLK 2 2
D46 Q18B 3 C702
34 TP_DATA 3
HT-110UYG-CT_YEL/GRN 2N7002DW-T/R7_SOT363-6 C201 1 2 0.22U_0603_16V4Z 1.U25 4 EC_FRDBTN# @ 1 2 220P_0402_50V7K
4
C202 1
2.Botton side of JWLAN for keep noise return path.
2 0.22U_0603_16V4Z @ ACES_85201-04051 C705
3.Top side of PU12 for noise bounce. EC_PLAYBTN# @ 1 2 220P_0402_50V7K
< WL&BT LED > C203 1 2 0.22U_0603_16V4Z 4.Top side of PU5 for noise bounce.
WLAN@ D50 C708
R550
5.U19 < SW/B Connector > EC_MUTEBTN# @ 1 2 220P_0402_50V7K
+3VS WLAN@ 1 2 120_0402_5% 2 1 JPOWER
WL_BT_LED# 34
ON/OFFBTN#
HT-110UD_1204_AMBER < BATT CHARGE/FULL LED > 1 1 KSO0
D70 < Ultra Bright Amber > 2 2 EC_PLAYBTN# KSO0 33,34
3 3 EC_REVBTN# KSI1 33,34
4 4 EC_FRDBTN# KSI3 33,34
3 BATT_FULL_LED# 34 5 5 KSI5 33,34
R773 EC_MUTEBTN#
< POWER-ON & SUSPEND LED > 1 2 120_0402_5% 1
6 6 KSI2 33,34
+3VALW 7 7
4 8 8 4
2 BATT_LOW_LED# 34 9 9
D68 < Ultra Bright Amber >
10 10
< Ultra Bright Yellow Green > GND 11
3 PWR_ON_LED# 34 GND 12
+3VALW R770 1 2 120_0402_5% 1 HT-210UD/UYG_AMB/GRN @ ACES_85201-1005N

2 PWR_SUSP_LED# 34 Security Classification Compal Secret Data Compal Electronics, Inc.

Vf=1.9V(typ),2.4V(max) for amber Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
< Ultra Bright Yellow Green >
Vf=2.0V(typ),2.4V(max) for green
If=30mA(max) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
HT-210UD/UYG_AMB/GRN AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 12, 2009 Sheet 35 of 45
A B C D E
 A B C D E

< +5VALW TO +5VS > < close to PQ20, must EMI confirm > < +1.8V TO +1.8VS >
+5VALW
+1.8V +1.8VS
+5VALW +5VS Q4
IRF8113PBF_SO8
Q35
1
C204
Inrush current = 0A
Inrush current = 0A 8 1
8 D S 1 7 2 1 2
7 2 1 1 0.1U_0402_16V7K 6 3 C848 C841
D S C833 C835 2
6 D S 3 5
5 4 RUNON 1 1U_0402_6.3V4Z 10U_0805_10V4Z
D G 1U_0402_6.3V4Z 4.7U_0805_10V4Z C842 2 1
1

4
C864 SI4800BDY_SO8 2 2 +3VS
4.7U_0805_10V4Z
1 4.7U_0805_10V4Z 2 R138 1
2 1.8VS_ENABLE 750K_0402_1%
1 2 +VSB

1
1

1
R809 C849 D
2 SUSP
10M_0402_5% 0.01U_0402_25V7K G
< +3VALW TO +3VS > < close to PQ20, must EMI confirm > 2 S Q13

3
2N7002_SOT23-3
+3VS

+3VALW +3VS 1
C197
Q14 Inrush current = 0A
8 1 0.1U_0402_16V7K < +1.2VALW TO +1.2V_HT >
D S 2
7 D S 2 1 1
6 3 C839 C838
D S +1.2VALW
5 D G 4
1 1U_0402_6.3V4Z 4.7U_0805_10V4Z
C840 SI4800BDY_SO8 2 2 Q11 +1.2V_HT
IRF8113PBF_SO8
4.7U_0805_10V4Z
Inrush current = 0A
8 1 1
2 R152 7 2 1 1
RUNON 2 1 750K_0402_1% 6 3 C846 C862 + C876
+VSB
5
1

1 1U_0402_6.3V4Z 4.7U_0805_10V4Z 330U_D2E_2.5VM

1

C834 @ R556 D 2 2 2

4
1
2 SUSP 1
0.01U_0402_25V7K 10M_0402_5% G C847 R367
2 S Q17 R233
2

2N7002_SOT23-3 4.7U_0805_10V4Z 1K_0402_5% 2 1 330K_0402_5% +VSB

2

1
2 2
1

6
R808 C837

10M_0402_5% 0.01U_0402_25V7K
< +3VALW TO +3V_LAN > 2
2 VLDT_EN#

2
+3VALW +3VALW +3V_LAN
Vgs=-4.5V, Id=3A Q12A

1
2N7002DW-T/R7_SOT363-6

Rds<97m ohm
< Inversion of SYSON, SUSP#, VLDT_EN, EC_ON >
2

R17 2
100K_0402_5% C194 +5VL +5VL +5VL +5VL
2

0.1U_0402_16V7K
1

1
S
R19 @ PJ29
2

1
G
WOL_EN# 1 2 47K_0402_5% 2 JUMP_43X79
34 WOL_EN#
1 Q38 R595 R596 R598
1

C182 D AO3413_SOT23 R597 100K_0402_5%

1

100K_0402_5% 100K_0402_5% 100K_0402_5%

1

0.01U_0402_25V7K

2
2
1 1 SYSON# SUSP VLDT_EN# EC_ON#
42 SYSON# SUSP 42
C679 Inrush current = 0A C680

3
@

6
4.7U_0805_10V4Z 1U_0402_6.3V4Z Q143B
2 2 Q142B Q142A 2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6 2N7002DW-7-F_SOT363-6 VLDT_EN 2 5
34 VLDT_EN EC_ON 34,35
5 2 Q143A
27,34,42 SYSON SUSP# 27,30,34,39,41
2N7002DW-7-F_SOT363-6

4
4

1
3 3

< Discharge circuit >

+5VS +1.8VS +1.2V_HT +1.8V +1.2VALW +3VS +0.9V +1.5VS +1.1VS

2

2
R239 R279 R280
R284 R368 R288 R292 R293 R294
470_0805_5% 470_0805_5% 470_0805_5% @
470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5% 470_0805_5%
1

3 1

1
Q12B
1

1
D D D D D D D D
SUSP 2 Q46 SUSP 2 Q48 VLDT_EN# 5 2N7002DW-T/R7_SOT363-6 SYSON# 2 Q41 EC_ON# 2 @ Q42 SUSP 2 Q47 SYSON# 2 Q49 SUSP 2 Q50 SUSP 2 Q52
G G G G G G G G
S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3 S 2N7002_SOT23-3
3

3
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 12, 2009 Sheet 36 of 45
A B C D E
 A B C D

VS
VIN PR1
VIN 1M_0402_1%
PL1
PF1
DC301001M80 DC_IN_S1 1 2 DC_IN_S2 1 2
1 2

1
1
PJP1 SMB3025500YA_2P N1 PR2
1 10A_125V_451010MRL PR3 5.6K_0402_5% PR4
+ 84.5K_0402_1% 10K_0402_1%

1
2 1 2

2
+ PC1 PC2 PC3 PC4 PR5 ACIN 22,34,35

8
3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 22K_0402_1% PU1A

2
1
- 1

1 2 3

P
+ PACIN
- 4 O 1
2 PACIN 39
-

G
@ SINGA_2DW-0005-B03

1
PR6 LM393DG_SO8

4
PC5 20K_0402_1% PC6 PD1 PR7
0.068U_0402_10V6K .1U_0402_16V7K GLZ4.3B_LL34-2 10K_0402_1%

2
2

2
2 1 RTCVREF
PR8
VIN 10K_0402_1%
3.3V Vin Detector

2
PD2
High 18.384 17.901 17.430
RLS4148_LL34-2 Low 17.728 17.257 16.976

1
PD3
BATT+ 2 1

1
RLS4148_LL34-2 PR9 PR10
68_1206_5% 68_1206_5%
PQ1
PR11 TP0610K-T1-E3_SOT23-3

2
200_0603_5%
CHGRTCP 1 2 N1 3 1 VS
1

2 2
1

1
PC8 PR12 1K_1206_5%
PR13 0.1U_0603_25V7K 1 2
100K_0402_1% PC7
2

2
0.22U_1206_25V7K PD4 PR14 1K_1206_5%
2

2 1 N3 1 2
35 51_ON# 1 2
VIN B+
PR15 RLS4148_LL34-2 PR16 1K_1206_5%
22K_0402_1% 1 2
RTC Battery

1
RTCVREF
1

PR19 PR20
PR18
200_0603_5%
- PBJ1 + VL
100K_0402_1%
1 2
2.2M_0402_5%
2 1
PR17
499K_0402_1%
PR21 PR22 PU2 G920AT24U_SOT89-3 2 1 +RTCBATT
3.3V +RTCBATT

2
560_0603_5% 560_0603_5%
2

1 2 1 2 3 2 N2
+CHGRTC OUT IN PD5

8
@ MAXEL_ML1220T10 RB715F_SOT323-3 PU1B
1

GND
2 5

P
PC9 PC10 7,40 EN0 1 7
+
10U_0805_10V4Z 1 O
3 6 2 1 RTCVREF
39 ACON
2

1
G
1U_0805_25V4Z
SP093MX0000

1
LM393DG_SO8 PR23 PR24 PC11

1
10K_0402_1% 499K_0402_1% 1000P_0402_50V7K

1
PC12 PR26

2
PC13 @ PR25
@PR25 191K_0402_1%

2
1000P_0402_50V7K 1000P_0402_50V7K 66.5K_0402_1%

2
3 3

PR27

1
D 47K_0402_1%
PJ2 2 2 1 PACIN
2 1 G
2 1 PQ2
S

3
@ JUMP_43X118 SSM3K7002FU_SC70-3
PJ23
PJ1 PJ3 PJ10

1
+3VALWP 2 2 1 1 +3VALW +1.8VP 2 2 1 1 +1.8V +3VLP 2 2 1 1 +3VL +VDDNBP 2 2 1 1 +VDDNB
@ JUMP_43X118 @ JUMP_43X118 @ JUMP_43X39 @ JUMP_43X79
(5A,200mils ,Via NO.= 10) (8A,320mils ,Via NO.= 16) (100mA,40mils ,Via NO.= 2) (4A, 160mils, Via NO.= 8)
2 +5VALWP
OCP(min) = 7.7A OCP(min) = 8.87A
PQ3
DTC115EUA_SC70-3
PJ4

3
PJ5 PJ6
+5VALWP 2 2 1 1 +5VALW +NB_COREP 2 2 1 1 +NB_CORE VL 2 2 1 1 +5VL
@ JUMP_43X118 @ JUMP_43X118 @ JUMP_43X39
(5A,200mils ,Via NO.= 10) ( 7A, 280mils , Via NO.=14 ) (100mA,40mils ,Via NO.= 2)
OCP(min) = 7.9A OCP(min) = 8.45A
Precharge detector
PJ8 PJ7
PJ9
2 1 2 1 2 1
15.97V/14.84V FOR
+VSBP 2 1 +VSB +1.2VALWP 2 1 +1.2VALW +2.5VSP 2 1 +2.5VS
4

@ JUMP_43X39 @ JUMP_43X118 @ JUMP_43X39

ADAPTOR 4

(5A,200mils ,Via NO.=10) (0.5A,20mils ,Via NO.= 1)

(120mA,40mils ,Via NO.= 1)
OCP(min) = 8.51A

PJ11 PJ12
Security Classification Compal Secret Data Compal Electronics, Inc.
+0.9VP 2 1 +0.9V +1.5VSP 2 1 +1.5VS Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
2 1 2 1
@ JUMP_43X79 @ JUMP_43X79 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
(2A,80mils ,Via NO.= 4) (2A,80mils ,Via NO.=4) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401721
Date: Wednesday, February 24, 2010 Sheet 37 of 45
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 95 degree C
Recovery at 57 degree C
VMB
1
Liverpool PF2 PL2 VL VL ENTRIP1 40
1

PJP2 15A_65V_451015MRL SMB3025500YA_2P VL

1 BATT_S1 1 2 1 2
1 BATT+
2 2

2
3 BATT_P3 1 2 1 2
3 +3VLP
4 BATT_P4 PR28 PR29 PR30
4

1
BATT_P5 1K_0402_1% 47K_0402_1% 47K_0402_1% D
5 5
10 6 EC_SMDA PC14 PC15 PH1 PC16 2 PQ4
GND 6 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7K 100K_0402_1%_NCP15WF104F03RC 0.1U_0603_25V7K PR31 G SSM3K7002FU_SC70-3
11 7

1
GND 7 47K_0402_1%
12 8 S

3
GND 8

1
13 9 1 2

2
GND 9 PR32 PR33

8
SUYIN_200045MR009G171ZR 1K_0402_1% 13.7K_0402_1% PU3A
@ 1 2 3 PD6

P
+
1 2 1

2
O

1
@PD16
@ PD16 TM_REF1 2 ENTRIP2 7,40
-

G
RLS4148_LL34-2

0.22U_0805_16V7K
PJSOT24C_SOT23-3 LM393DG_SO8

4
1000P_0402_50V7K
15K_0402_1%
1
Sunderland

1
PC17

PR36
@PD15
@ PD15
2

1
D

PC18
PJP3 2 1 VL
1 BATT_S1 2 2 PQ5

2
1 PR38 G SSM3K7002FU_SC70-3
2 1

2
2

1
3 BATT_P3 3 100K_0402_1% S

3
3 BATT_P4
4 4
5 BATT_P5 PR40
5 EC_SMDA PJSOT24C_SOT23-3 100K_0402_1%
10 GND 6 6
11 7 EC_SMCA

2
GND 7
12 GND 8 8
13 9 PR37
GND 9
2

2
6.49K_0402_1% 2

SUYIN_200045MR009G171ZR PR34 PR35 2 1 +3VLP

@ 100_0402_1% 100_0402_1%
1

PR39
1K_0402_1%
2

BATT_TEMPA 34 PH2 near main Battery CONN :

BAT. thermal protection at 98 degree C
EC_SMB_DA1 19,34 Recovery at 60 degree C
EC_SMB_CK1 19,34 VL
PH2 for Liverpool
PH3 for Sunderland VL

1
PQ6 @ PH3 PH2

2
TP0610K-T1-E3_SOT23-3 100K_0402_1%_NCP15WF104F03RC 100K_0402_1%_NCP15WF104F03RC
PR41
47K_0402_1%

2
B+ 3 1 +VSBP PR42
47K_0402_1%

1
100K_0402_1%

0.1U_0603_25V7K 1 2
1

3 3
1

1
PR43

@ PC20

PR44

8
14K_0402_1% PU3B
@ PC19
@PC19 1 2 5 PD7

P
2

PR45 0.22U_1206_25V7K +
7 2 1
2

22K_0402_1% TM_REF1 O
6 -

G
VL 1 2 RLS4148_LL34-2

1
LM393DG_SO8

4
PC21 PR46
2

0.22U_0805_16V7K 13.7K_0402_1%

2
PR47

2
100K_0402_1%

PR48
1

0_0402_5% D
1 2 2 PQ7
40,41 POK
G SSM3K7002FU_SC70-3
.1U_0402_16V7K

S
3
1

@ PC22
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401721
Date: Wednesday, February 24, 2010 Sheet 38 of 45
A B C D
 A B C D

PQ10
AO4435_SO8
1 8 75W 4435*1
2 7
P2 3 6
PQ8
AO4435_SO8
PQ9
AO4407A_SO8 P3 PR49
B+ PL17 CHG_B+
5

8 1 1 8 0.02_2512_1% HCB4532KF-800T90_1812

4
VIN 7 2 2 7 1 4 1 2 @PQ45
@ PQ45
6 3 3 6 AO4435_SO8
5 5 2 3 CSIN 1 8
2 7
3 6

10U_1206_25V6M

10U_1206_25V6M
CSIP 5

1
1 1

PR203

1
PQ11 TP0610K-T1-E3_SOT23-3 10_0603_5%

4
PC23

PC24
PR50 1 2 DCIN

2
PQ12 200K_0402_1% 3 1

2
DTA144EUA_SC70-3 PC26 P3 PR51

2
1

1
5600P_0402_25V7K PQ13 47K_0402_1%

1
2 PC27 PR54 DTC115EUA_SC70-3 1 2
PR53 0.1U_0603_25V7K 100K_0402_1% VIN

2
47K_0402_1% PD9
PR56 2 FSTCHG
2

2
100K_0402_1% 2 1

2
1

PD10 2 1 3 PR52 PD8

1

1SS355_SOD323-2 SUSP# 27,30,34,36,41 10K_0402_1% 1 2 ACOFF

1 2 6251VDD RB715F_SOT323-3

2.2U_0603_6.3V6K
1SS355_SOD323-2

1
PC28
2 PR57 PR55

1
PQ15 10K_0402_1% 200K_0402_1%

1
DTC115EUA_SC70-3 2 1 PU4 PC30 1 2 VIN
34 FSTCHG 0.1U_0603_25V7K

2
1

100K_0402_1%
1 2 1 24 DCIN 2 1
3

VDD DCIN
1

1
2 PQ16 PQ14 PD11

PR59
G SSM3K7002FU_SC70-3 PC29 DTC115EUA_SC70-3 2 1 2
S PR58 .1U_0402_16V7K 2 23
3

150K_0402_1% ACSET ACPRN PR60 1SS355_SOD323-2

20_0603_5%
2

2
6251_EN 3 22 1 2 CSON

3
EN CSON

1
PC33 PC32 D

5
6
7
8

1
@ 680P_0402_50V7K 0.047U_0603_16V7K PC31 2 PACIN
CSON 1 2 4 21 1 2 CSOP 0.1U_0603_25V7K G

1
CELLS CSOP PR61 PQ18 PQ17
S

3
PC34 6800P_0402_25V7K 20_0603_5% AO4466_SO8 SSM3K7002FU_SC70-3
2 2
1 2 5 ICOMP CSIN 20 2 1
1

2
D PR62 4
2 PQ19 PC36 PR63 6.81K_0402_1% PC35 20_0603_5%
G SSM3K7002FU_SC70-3 1 2 1 2 6 19 0.1U_0603_25V7K
1 2 PL3

1
PR65 VCOMP CSIP 10U_LF919AS-100M-P3_4.5A_20% PR66
S
3

0.01U_0402_25V7K 2 1 47K_0402_1% PR64 0.02_2512_1% BATT+

3
2
1
PR67 PC37 1 2 7 18 LX_CHG 2.2_0603_5% 1 2CHG 1 4
22K_0402_5% @ 100P_0402_50V8J ICM PHASE

5
6
7
8

1
PACIN 1 2 1 2 2 3
37 PACIN

10U_1206_25V6M

10U_1206_25V6M
6251VREF 8 17 DH_CHG PR170
PC38 .1U_0402_16V7K VREF UGATE PR69 PC39 4.7_1206_5%
37 ACON
PR68 2.2_0603_5% 0.1U_0603_25V7K
34 ADP_I

1
PC40

PC41
154K_0402_1% 9 16 BST_CHG 1 2 BST_CHGA 2 1

1 2
CHLIM BOOT
1

1
PQ21 2 1 4 PQ20
34 IREF
0.01U_0402_25V7K

DTC115EUA_SC70-3 PR70 PD12 AO4466_SO8 PC129

2
24K_0402_1% 10 15 6251VDDP RB751V-40TE17_SOD323-2 680P_0603_50V7K
ACLIM VDDP
1

6251VREF 1 2 6251aclim

2
1
PC42

ACOFF 2 PR71 1 26251VDD

34 ACOFF

3
2
1
1
120K_0402_1% 11 14 DL_CHG
VADJ LGATE

2
PR73 PR72
2

20K_0402_1% 4.7_0603_5%
2

12 13 PC43
3

1
GND PGND 4.7U_0805_6.3V6K
2

ISL6251AHAZ-T_QSOP24

PR74
15.4K_0402_1%
1 2
34 CHGVADJ
1

3 3

PR75
Iada=0~3.421A(65W) CP=3.15A PR49=0.02, PR70=75k, PR73=20k 31.6K_0402_1%

Iada=0~3.947A(75W) CP=3.63A PR49=0.02, PR70=24k, PR73=20k

2

VIN
Iada=0~4.737A(90W) CP=4.36A PR49=0.015, PR70=53.6k, PR73=20k
Iada=0~6.316A(120W) CP=5.81A PR49=0.015, PR70=8.25k, PR73=26.7k

1
CP= 92%*Iada
PR171
309K_0402_1%
CP mode
Vaclim=2.39*(Rb//152K/(Rt//152K+Rb//152K)) PR202

2
10K_0402_1%
Iinput=(1/PR49)((0.05*Vaclm)/2.39+0.05) 1 2
ADP_V 34
where Vaclm=1.09986V, Iinput=3.65A
Vaclm=0.7717V, Iinput=4.41A
1

1
Vaclm=0.4204V, Iinput=5.88A @ PD14 PR172
GLZ4.3B_LL34-2 47K_0402_1% PC130
2 .1U_0402_16V7K
2

CC=0.25A~3A CHGVADJ=(Vcell-4)/0.10627
IREF=1.016*Icharge Vcell CHGVADJ
IREF=0.254V~3.048V 4V 0V
4
VCHLIM need over 95mV 4.2V 1.882V 4

4.35V 3.2935V

CELLS VDD GND Float

CELL number 4 3
- 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401721
Date: Wednesday, February 24, 2010 Sheet 39 of 45
A B C D
 5 4 3 2 1

AO4712 Rds(on) = 15/18

2VREF_51125

0.22U_0603_10V7K
Ipeak = 5A

1
PC44
D Imax = 3.5A Ipeak = 5A D

2
F = 305K Imax = 3.5A
F = 245K
PR76 PR77
13K_0402_1% 30K_0402_1%
1 2 1 2

PR78 PR79
B++
20K_0402_1% 19.1K_0402_1%
1 2 1 2 B++
PL18
HCB4532KF-800T90_1812

ENTRIP2
B+ 1 2 +3VLP

ENTRIP1

4.7U_1206_25V6K

4.7U_1206_25V6K
2200P_0402_50V7K
PR80 PR81

1
2200P_0402_50V7K

4.7U_1206_25V6K

4.7U_1206_25V6K

150K_0402_1% 150K_0402_1%
1

PC45

PC46

PC47
4.7U_0805_10V6K
1 2 1 2

5
6
7
8
PC48

PC49

PC50

PC51
2

8
7
6
5

1
PQ22
AO4466_SO8

2
PQ23

1
AO4466_SO8 PU5 4
C 4 C

VREF
ENTRIP2

VFB2

TONSEL

VFB1

ENTRIP1
25 P PAD
POK 38,41

3
2
1
7 24
1
2
3 VO2 VO1
PL5 PC52 8 23 PC53 PL6
4.7U_LF919AS-4R7M-P3_5.2A_20% 0.1U_0402_16V7K PR82 VREG3 PGOOD PR83 0.1U_0402_16V7K 4.7U_LF919AS-4R7M-P3_5.2A_20%
1 2 1 21 2 BST_3V 9 22 BST_5V 1 2 1 2 1 2
+3VALWP 0_0603_5% VBST2 VBST1 0_0603_5%
UG_3V 10 21 UG_5V +5VALWP
DRVH2 DRVH1
8
7
6
5

5
6
7
8
1

1
PQ24 LX_3V 11 20 LX_5V
LL2 LL1

220U_6.3VM_R15
@ PR84 AO4712_SO8 @ PR85
220U_6.3VM_R15

1 4.7_1206_5% LG_3V 12 19 LG_5V PQ25 4.7_1206_5% 1

DRVL2 DRVL1 AO4712_SO8

SKIPSEL
+ +
PC54

PC55
4 4

VREG5
1 2

1 2
VCLK
GND
EN0

VIN
@ PC56
2 680P_0603_50V7K @ PC57 2
7,37 EN0 TPS51125RGER_QFN24_4X4 680P_0603_50V7K
ESR=15m
2

1
2
3

13

14

15

16

17

18

3
2
1

2
ESR=15m PR86
499K_0402_1%
B+ 1 2

1
100K_0402_1%

1U_0402_6.3V6K
1
1 2 VL
PR87

@ PC180

1
B ENTRIP1 38 ENTRIP2 7,38 B

PC58
4.7U_0805_10V6K
PR88

2
@ 0_0402_5%
2

2
B++
1

1
D D

0.1U_0603_25V7K
PQ26 2 2 PQ27
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3

2
PC59
S S
3

2VREF_51125

VL 2 1

PR89
100K_0402_1%
1

VS 1 2 2 PQ28
G SSM3K7002FU_SC70-3
PR90 S
3
1

100K_0402_1%
PR91
49.9K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401721
Date: Wednesday, February 24, 2010 Sheet 40 of 45
5 4 3 2 1
 5 4 3 2 1

PL19
HCB4532KF-800T90_1812
NB_B+ 1 2 B+

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PC60

PC61
Ipeak = 7A

5
6
7
8

2
D
PQ29
AO4466_SO8
Imax = 4.9A D
F = 315K
PR92
255K_0402_1% 4
1 2
PR93 PR94
33K_0402_1% 0_0603_5%
1 2 1 2
Total capacitor 550uF
27,30,34,36,39 SUSP#

3
2
1
ESR = 7.5mohm

1
PL7 +1.1V

15

14
PC63

1
PC62 PU6 1.8UH_SIL104R-1R8PF_9.5A_30%
.1U_0402_16V7K BST_NB 1 2 1 2

EN_PSV

TP

VBST
+NB_COREP

2
2 13 DH_NB 0.1U_0603_25V7K
TON DRVH

4.7_1206_5%
PR96 3 12 LX_NB
VOUT LL

5
6
7
8

PR95
100_0603_1% 1

220U_6.3VM_R15
+5VALW 1 2 4 11 1 2 +5VALW PQ30
V5FILT TRIP +

PC64
PR97 AO4712_SO8

2
5 10 15.4K_0402_1%
VFB V5DRV
1

1
DL_NB 2
6 PGOOD DRVL 9 4

PGND

680P_0603_50V7K
PC65

GND

PC66
4.7U_0603_6.3V6K @ PC68
2

2
47P_0402_50V8J PC67
1 2 TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_10V6K

3
2
1
PR98
9.53K_0402_1%
C C
1 2
1

PR99
20.5K_0402_1%
2

PL20
HCB4532KF-800T90_1812
1.2V_B+ 1 2 B+

4.7U_0805_25V6-K

4.7U_0805_25V6-K

100U_25V_M
1

1
PC69

PC70

PC173
+

5
6
7
8

2
PQ31 2
AO4466_SO8
Ipeak = 5A
PR100
255K_0402_1%
Imax = 3.5A
4
1 2 F = 315K
PR102
PR101
0_0603_5%
38,40 POK 1 2 1 2

3
2
1
B B
0_0402_5% Total capacitor 220uF
1

PL8
15

14

PC72
1

@PC71
@PC71
.1U_0402_16V7K
PU7 2.2UH_PCMC063T-2R2MN_8A_20% ESR = 15mohm
BST_1.2V 1 2 1 2
EN_PSV

TP

VBST

+1.2VALWP
2

2 13 DH_1.2V 0.1U_0603_25V7K
TON DRVH

1
PR104 3 12 LX_1.2V PR103
VOUT LL

5
6
7
8
100_0603_1% 4.7_1206_5% 1

220U_6.3VM_R15
+5VALW 1 2 4 11 1 2 +5VALW PQ32
V5FILT TRIP +

PC73
PR105 AO4712_SO8

2
5 10 15.4K_0402_1%
VFB V5DRV
1

1
DL_1.2V 2
6 PGOOD DRVL 9 4
PGND

680P_0603_50V7K
PC74
GND

PC75
4.7U_0603_6.3V6K @PC77
@ PC77
2

2
47P_0402_50V8J PC76
1 2 TPS51117RGYR_QFN14_3.5x3.5 4.7U_0805_10V6K
7

3
2
PR106 1
12.1K_0402_1%
1 2
1

PR107
20.5K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401721
Date: Wednesday, February 24, 2010 Sheet 41 of 45
5 4 3 2 1
 5 4 3 2 1

PL21
HCB4532KF-800T90_1812
51117_B+ 1 2 B+

4.7U_1206_25V6K

4.7U_1206_25V6K
1

1
PC78

PC79
Ipeak = 8A

5
6
7
8
Imax = 5.6A

2
PQ33
AO4466_SO8 F = 315K
PR108
255K_0402_1% 4
D D
1 2
PR109 PR110
0_0402_5% 0_0603_5%
Total capacitor 220uF
27,34,36 SYSON 1 2 1 2 ESR = 15mohm

3
2
1
1
PL9

15

14
PC81

1
@ PC80 PU8 1.8UH_SIL104R-1R8PF_9.5A_30%
.1U_0402_16V7K BST_1.8VP 1 2 1 2

EN_PSV

TP

VBST
+1.8VP

2
2 13 DH_1.8VP 0.1U_0603_25V7K
TON DRVH

4.7_1206_5%
PR111
PR112 3 12 LX_1.8VP
VOUT LL

5
6
7
8
100_0603_1% 1

220U_6.3VM_R15
+5VALW 1 2 4 11 1 2 +5VALW PQ34
V5FILT TRIP

PC82
PR113 AO4712_SO8 +

2
5 10 15.4K_0402_1%
VFB V5DRV

1
2

680P_0603_50V7K
6 9 DL_1.8VP 4
PGOOD DRVL

PGND

PC84
PC83

GND
4.7U_0603_6.3V6K @ PC85

2
1
47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 PC86

3
2
1
4.7U_0805_10V6K

2
PR114
28.7K_0402_1%
1 2

1
C PR115 C
20.5K_0402_1%

+3VS +1.8V
1

1
PJ17
1

@ JUMP_43X79 PJ18

1
@ JUMP_43X79
2

2
PU9
2

1 6 +5VALW PU10

2
VIN VCNTL
1 VIN VCNTL 6 +3VALW
2 GND NC 5
2

1
2 GND NC 5
1

1
PC87 3 7 PC88 PC89
VREF NC

1
4.7U_0805_6.3V6K 1U_0603_6.3V6M 4.7U_0805_6.3V6K 3 7 PC90
1

PR116 PR117 VREF NC 1U_0603_6.3V6M

4 8

2
1.2K_0402_1% VOUT NC 1K_0402_1% 4 VOUT NC 8
9
2

TP
9

2
B APL5331KAC-TRL_SO8 TP B
APL5331KAC-TRL_SO8
+1.5VSP
1

1
PR120 PR118 PR121 +0.9VP
1

1
0_0402_5% D 1K_0402_1% 0_0402_5% D PR119
1

SUSP 1 2 2 1 2 2 1K_0402_1% PC91

36 SUSP 36 SYSON#

1
G PC92 PC93 G .1U_0402_16V7K

2
1

1
S PQ35 .1U_0402_16V7K 10U_0805_6.3V6M S PQ36 PC94
3

2
@ PC95 SSM3K7002FU_SC70-3 @PC96
@ PC96 SSM3K7002FU_SC70-3 10U_0805_6.3V6M

2
.1U_0402_16V7K .1U_0402_16V7K
2

2
PU11
APL5508-25DC-TRL_SOT89-3
PJ19
+3VS
1 1 2 2 2 IN OUT 3 +2.5VSP
@ JUMP_43X39
GND
1

PC97 1 PC98
A 1U_0603_10V6K 4.7U_0805_6.3V6K A
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401721
Date: Wednesday, February 24, 2010 Sheet 42 of 45
5 4 3 2 1
 A B C D E

CPU_B+ PL10
HCB4532KF-800T90_1812
PC99 1 2 B+

10U_1206_25V6M

0.1U_0402_25V4K

0.1U_0402_25V4K

0.1U_0402_25V4K

0.1U_0402_25V4K

0.1U_0402_25V4K

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
33P_0402_50V8K

220U_25V_M

@ 220U_25V_M
2 1 1 1

5
6
7
8

1
PC103

PC100
+

PC101
+

PC131

PC132

PC133

PC134

PC135

PC136

PC137

PC138
2 1 2 1

2
PR122 PC102 2 2
44.2K_0402_1% 1000P_0402_50V7K UGATE_NB 4 PQ37
PR123 AO4466_SO8
2_0603_5%
+5VS 1 2 PC104 PL11 EMC
1 1000P_0402_50V7K 4.7U_LF919AS-4R7M-P3_5.2A_20% 1

3
2
1
2 1 PHASE_NB 1 2 +VDDNBP
PR124
Ipeak = 36A

5
6
7
8

1
PC105 PR126 2.2_0603_1%
0.1U_0603_16V7K 22K_0402_1% BOOT_NB 1 2 1 2 PR125
4.7_1206_5%
Imax = 25.2A
2 1 1

2
PC106
+
F = 300K
0.22U_0603_10V7K PQ38 PC107

1 2
LGATE_NB 4 AO4712_SO8 220U_D2_4VM
CPU_B+ 1 2 PR129 PC108
0_0402_5% 680P_0603_50V7K 2
PR128 2 1 CPU_VDDNB_RUN_FB_H 7 Total capacitor 1320uF

2
2_0603_5% PR130

3
2
1
+5VS +3VS 11K_0402_1% ESR = 1.5mohm
2 1 PHASE_NB

LGATE_NB

1
PC109 CPU_B+
0.1U_0603_25V7K PHASE_NB
1

2
PR131 PR132 UGATE_NB

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
0_0402_5% @ 105K_0402_1%

5
2 1 CPU_VDDNB_RUN_FB_L 7
PR133 PQ39
2

2
1

1
PC110

PC111

PC169

PC170
0_0402_5%
PR135
PR134 @ 10K_0402_1%

2
105K_0402_1% UGATE0 4
1

48

47

46

45

44

43

42

41

40

39

38

37
2

PR137 PU12
@ 105K_0402_1% PHASE0 PL12

FB_NB

COMP_NB

FSET_NB

VSEN_NB

RTN_NB

OCSET_NB

PGND_NB

LGATE_NB

PHASE_NB

UGATE_NB
VIN

VCC
PR138 TPCA8030-H_SOP-ADV8-5 0.36UH_PCMC104T-R36MN1R17_30A_20%

3
2
1
2 0_0603_5% 2
2

34 VGATE 1 36 BOOT_NB BOOT0 1 2 1 2 1 4 +CPU_CORE_0

OFS/VFIXEN BOOT_NB
1 2
7,20 H_PWRGD @ PR139 0_0402_5% BOOT0 PC112

TPCA8028-H_SOP-ADVANCE8-5

TPCA8028-H_SOP-ADVANCE8-5
2 PGOOD BOOT0 35 2 3

5
1 2 0.22U_0603_10V7K

1
21,34 SB_PWRGD PR140 0_0402_5% ISL6265_PWROK 3 34 UGATE0
PWROK UGATE0

2
PR141
7 CPU_SVD 2 1 4 33 PHASE0 4.7_1206_5% PR143
7 CPU_SVC SVD PHASE0

@ PQ40

PQ41
PR142 16.5K_0402_1%
0_0402_5%2 1 5 32 4 4

1 2
34 VR_ON PR144 SVC PGND0 +5VS

1
PR145 PR146 0_0402_5% 6 31 LGATE0 PC113 PC114
21.5K_0402_1% 95.3K_0402_1% ENABLE LGATE0 680P_0603_50V7K 2 1
2 1 2 1 7 30

3
2
1

3
2
1

2
RBIAS ISL6265HRTZ-T_QFN48_6X6 PVCC 0.1U_0603_16V7K
8 29 LGATE1
OCSET LGATE1

1
PC115 2 1
9 28 1U_0603_10V6K
VDIFF0 PGND1 LGATE0 PR147

ISN0
ISP0
10 27 PHASE1 4.02K_0402_1%
FB0 PHASE1
11 26 UGATE1
COMP0 UGATE1 CPU_B+
12 25 BOOT1 PJ20
VW0 BOOT1
COMP1
2 1
VDIFF1
VSEN0

VSEN1

2 1
RTN0

RTN1
ISN0

ISN1
ISP0

VW1

ISP1
FB1

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
@ JUMP_43X118

TP

5
+CPU_CORE_0 +CPU_CORE_1
PQ42
13

14

15

16

17

18

19

20

21

22

23

24

49

1
PC116

PC117

PC171

PC172
PJ21
ISP0 2 1
ISN0 2 1
PR149

2
ISN1
ISP1

3 0_0402_5% UGATE1 @ JUMP_43X118 3

4
2 1 VSEN0
7 CPU_VDD0_RUN_FB_H 0_0402_5%
2 PR150 1 RTN0 PHASE1 PL13
7 CPU_VDD0_RUN_FB_L PR152 TPCA8030-H_SOP-ADV8-5 0.36UH_PCMC104T-R36MN1R17_30A_20%

3
2
1
2 1RTN1 0_0603_5%
7 CPU_VDD1_RUN_FB_L BOOT1 1 2 1 2 1 4 +CPU_CORE_1
PR151 0_0402_5%
2
1K_0402_1%

PC118

TPCA8028-H_SOP-ADVANCE8-5

@ TPCA8028-H_SOP-ADVANCE8-5
2 3

5
@ PR173

0.22U_0603_10V7K

2
PR155
4.7_1206_5% PR156
1

PQ43

PQ44
+1.8V 16.5K_0402_1%
PR157 4 4

1 2
0_0402_5%

1
7 CPU_VDD1_RUN_FB_H 2 1 VSEN1 PC119 PC120
680P_0603_50V7K 2 1

3
2
1

3
2
1

2
0.1U_0603_16V7K

DIFF_0 VW0 DIFF_1 VW1 2 1

PR160 PC121 @PR161

@PR161 @ PC124 LGATE1 PR159

ISN1
ISP1
255_0402_1% 4700P_0402_25V7K 255_0402_1% 4700P_0402_25V7K 4.02K_0402_1%
2 1 2 1 FB_0 2 1 COMP0 2 1 2 1 2 1 FB_1 2 1 COMP1 2 1

PC122 PC123 @ PC125 @ PC126

@PC126
180P_0402_50V8J 1000P_0402_50V7K 180P_0402_50V8J 1000P_0402_50V7K

PR162 PR164 @PR165

@ PR165 @ PR167
1K_0402_5% PR163 PC127 6.81K_0402_1% 1K_0402_5% @ PR166 @ PC128
@PC128 6.81K_0402_1%
4 4
2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1

54.9K_0402_1% 1200P_0402_50V7K 54.9K_0402_1% 1200P_0402_50V7K

1

PR168 PR169
@ 36.5K_0402_1% @ 36.5K_0402_1%
Security Classification Compal Secret Data Compal Electronics, Inc.
2

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401721
Date: Wednesday, February 24, 2010 Sheet 43 of 45
A B C D E
 A B C D E

Version Change List ( P. I. R. List ) for Circuit

Item Page# Title Date Request Rev.
Owner Issue Description Solution Description
1
1. 2009/02/26 --> Change D36 from ROHM to PANJI 55. 2009/11/24 --> Modify R195, R195 BOM structure for RS880M UMA with non-HDMI function 1

2. 2009/02/26 --> Remove H38, H39

3. 2009/02/27 --> Change the footprint of T9, T10, T11, T12, T19, T20 from TPC12 to TPC24
4. 2009/02/27 --> Change 5V power of LCD connector
5. 2009/03/02 --> Unmount D17, R965 and mount R966
6. 2009/03/02 --> Unmount R556
7. 2009/03/05 --> Change side-port memory to Hynix SA00002UH00
8. 2009/03/05 --> Change RA16 from 5% to 1%
9. 2009/03/10 --> Change R146 from 100k ohm to 10k ohm
10. 2009/03/10 --> Change Y2 from SJ114P3M730 to SJ114P3MG00
11. 2009/03/11 --> Change C686, C699, C702, C705, C706, C708, CA27 from SE074221K00SE to SE074221K80 for Green part
12. 2009/03/11 -->Change LAN_WAKE# & EC_SWI#
13. 2009/03/12 --> Unmount USB sleep & charge, add R112 & R113
14. 2009/03/12 --> Unmount HDMI CEC controller and related components.
15. 2009/03/12 --> Connect USB_OC#0 to LAN_WAKE# through 0 ohm
16. 2009/03/12 --> Change H42 from NPH to PH
2
17. 2009/03/24 --> Change F2 footprint to F_MINISMDC110F-2 2

18. 2009/03/24 --> Add R370 & R381

19. 2009/03/24 --> Change R557’s BOM structure from H@ to @
20. 2009/03/24 --> Change R440 from 0 ohm to 100k ohm
21. 2009/04/06 --> Remove PCMCIA page and function
22. 2009/04/06 --> Add RM8 100K ohm
23. 2009/04/06 --> Change R440 from 100K ohm to 0 ohm for Askey BT module
24. 2009/04/06 --> Change C480's BOM structure from BT@ to @
25. 2009/04/10 --> Add C876 for power noise issue
26. 2009/04/10 --> Add D20 for power noise issue
27. 2009/04/10 --> Replace PJ13, PJ30, PJ14, PJ15, PJ16 by PL17, PL18, PL19, PL20, PL21
28. 2009/04/20 --> Change D12's BOM structure to @
29. 2009/04/22 --> Change C876 & C234 PN from 330u to 470u (SGA00001U00) for Power noise issue
30. 2009/04/28 --> Add PCMCIA function on page 27
31. 2009/04/29 --> Change R42's BOM structure to @
32. 2009/05/06 --> Change C876 & C234 from 470u to 330u for COST reduce
3
33. 2009/05/07 --> Mount R367 for can't power on issue (AMD SB leakage) 3

34. 2009/05/18 --> Change RA38's BOM structure from LVDSSET@ to @

35. 2009/05/19 --> Change C876 from SGA00001Q80 to SGA19331D00
36. 2009/05/19 --> Add C618 & C619 for EMI request
37. 2009/06/03 --> Change PJP9 to L90 (SM010024220) for EMI request
38. 2009/06/03 --> Add C120 for EMI request
39. 2009/06/03 --> Add C618, C619 for EMI reserve
40. 2009/06/03 --> Combine camera with LVDS
Delete R430, R428, R20, R18, C744, JCAM
41. 2009/06/03 --> Change BOM structure of RA31 and CA34 from @ to mount for EMI require
42. 2009/06/03 --> Add CA58 for EMI reserve
43. 2009/06/03 --> Delete JPWR1 for ME portion
44. 2009/06/04 --> Change UL3 from SP050005V00 to SP050005W00 (for AP issue)
45. 2009/06/10 --> Change R125 and R625 BOM Structure from @ to NSIDE@
46. 2009/07/07 --> Change C643 and C652 value from 18P to 12P
47. 2009/07/07 --> Change C350 from SF22001M200 to SF000001H00 as main source
4
48. 2009/08/06 --> Change Y7 from SJ100003D00 to SJ132P7KW10 for green review 4

49. 2009/08/11 --> Change RN3 BOM Structure from EXPCARD@ to always mount on and relocated to SB side (Page 20).
50. 2009/09/21 --> Change CL26, CL27 from SE00000H180 to SE074102K80, due to shortage
51. 2009/09/21 --> Change C9, C13, C70, C71, C83, C84, C95, C104, C120 from SE068102J80 to SE074102K80, due to main source shortage
52. 2009/09/21 --> Change U34, U36 from SA00001WP00 to SA00003GI00, due to main source E3 code Security Classification Compal Secret Data Compal Electronics, Inc.
53. 2009/10/02 --> Delete RN2's BOM structure and move to SB side (Page 21). Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title

54. 2009/10/12 --> Change Q13,Q17 PN to SB770020010 for common use THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Schematic, MB LA-5332P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401721 C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, February 24, 2010 Sheet 44 of 45
A B C D E
 5 4 3 2 1

HW4 Product Improvement Record (P.I.R.)

< Tigris >
D D
< R1 for customer BOM STRUCTURE > < R3 for mass production BOM STRUCTURE >

U3

RS880M RS880M
RS880MR3@ RS880M R3

U3
U3

RS880MC RS880MC
RS880MCR3@ RS880MC R3
RS880MCR1@ RS880MC R1

U15

SB710 SB710
SB710R3@ SB710 R3

C C

< DC Jack >

PJP1

DC-IN

16inch_45@ PJP1

PJP1

DC-IN

17inch_45@ PJP1

B
< PCB > B

ZZZ

PCB

PCB 093 LA-5332P REV1.0 M/B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009-02-12 Deciphered Date 2009-02-12 Title
Schematic, MB LA-5332P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401721
Date: Wednesday, February 24, 2010 Sheet 45 of 45
5 4 3 2 1