1618 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO.
6, JUNE 2014
CMOS Startup Charge Pump With Body Bias and
Backward Control for Energy Harvesting
Step-Up Converters
Huan Peng, Nghia Tang, Youngoo Yang, Member, IEEE, and Deukhyoun Heo, Senior Member, IEEE
Abstract—A new low voltage charge pump is developed to help
start up a step-up converter in energy harvesting applications. The
proposed charge pump is the first to utilize both backward control
scheme and two branches of charge transfer switches (CTSs) to
direct charge flow. The backward control scheme uses the internal
boosted voltage to dynamically control the CTSs’ gate, and the
two branches utilize both NMOS and PMOS to implement their
switching structure. The combination of backward control scheme
and two-branch operation allows the CTSs to be completely
turned on and off. Thus, the reverse charge sharing phenomenon
and switching loss are significantly reduced, which effectively
improves pumping efficiency. The last stage is specially designed
to improve the charge pump’s charge and capacitance drivability.
Using subthreshold operation and body-bias technique, the charge
pump and its clock generator can operate under a low voltage
supply. The proposed charge pump circuit is designed in a stan-
dard 0.18 m CMOS process. It consists of 6 stages, each with
a 24 pF pumping capacitor (total 288 pF pumping capacitance
area). Under a 320 mV supply, the measured output voltage of
the proposed charge pump can rise from 0 to 2.04 V within 0.1
milliseconds.
Index Terms—Body bias, energy harvesting, low voltage, startup
charge pump, step-up converter, subthreshold operation.
I. INTRODUCTION
I N remote sensing applications, energy harvesting is often
utilized to provide a renewable power source for sensor
nodes [1]. Some energy harvesting sources are characterized
with very low voltage output, which prevents their immediate
usage. For example, to generate maximum power, sediment
microbial fuel cells are operated between 300 mV and 500 mV
Manuscript received May 16, 2013; revised September 01, 2013; accepted
October 07, 2013. Date of publication January 17, 2014; date of current version
May 23, 2014. This work was supported in part by the NSF Center for Design of
Analog-Digital Integrated Circuits (CDADIC), the Korean Government under
Grant NRF-2011-220-D00084, , the KFRI u-food project, and the National Sci-
ence Foundation under Grant EECS-0845849. This paper was recommended by
Associate Editor H. S. Chung.
H. Peng is with the Electrical Engineering and Computer Science De-
partment, Washington State University, Pullman, WA 99164 USA (e-mail:
hpeng@eecs.wsu.edu).
N. Tang is with the Electrical Engineering and Computer Science De-
partment, Washington State University, Pullman, WA 99164 USA (e-mail:
ntang@eecs.wsu.edu).
Y. Yang is with the School of Electronic and Electrical Engineering,
Sungkyunkwan University, Suwon, Korea (e-mail: yang09@skku.edu).
D. Heo is with the Electrical Engineering and Computer Science Department,
Washington State University, Pullman, WA 99164 USA (e-mail: dheo@eecs.
wsu.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2013.2290823
1549-8328 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA. Downloaded on November 03,2023 at 08:57:17 UTC from IEEE Xplore. Restrictions apply.
output voltage [2], [3]. Meanwhile, most sensors require high
operating voltage in several volts. To solve this problem, a
step-up converter can be used to boost a low voltage source
and to provide a high voltage output to power a load. However,
operating a step-up converter under a low voltage supply is
challenging [4]. In steady state operation, a step-up converter
can use its own high voltage output to power the control
circuitry (self-sustained condition), but initially, a sufficiently
high voltage must be applied to start up the system. For ex-
ample, the S8353D (Seiko Instruments Inc.), tested with a
capacitive load, was found to require a startup supply voltage
of 520 mV for 1.7 ms. After startup, the minimum supply
voltage required to maintain normal operation is 320 mV. In
[5] and [6], the reported energy harvesting systems can operate
from dozens of millivolts, but they need external high voltage
sources or expensive mechanical active devices to start up the
system, which limits their practical application. Apparently, a
better approach is to build an integrated startup charge pump,
which can generate a high-voltage pulse to bootstrap a step-up
converter from a low voltage input [7].
In this paper, a startup charge pump is proposed for low
voltage operation. The charge pump with an integrated ring
oscillator utilizes subthreshold operation [8] and body bias
technique to enable startup and operation under a low voltage
supply. With a special structure and control mechanism, the
charge pump obtains performance improvement in some of
the key specifications. Unlike traditional charge pumps, a
startup charge pump only works during the startup period of
a step-up converter, and it only supports a capacitive load [4].
Therefore, the critical specifications of a startup charge pump
are input voltage level, pumping efficiency (
is the real output voltage of charge pump, and is the
ideal output voltage of charge pump), charge transferability
(ramp-up current), and capacitance drivability.
The rest of the paper is organized as follows. Section II sur-
veys all of the previous works with cons and pros. Section III
describes a ring oscillator, which is a key component of the
proposed startup charge pump. Section IV describes the charge
pump’s structure and operation. Section V demonstrates the per-
formance of the proposed charge pump prototype, implemented
in a 0.18 m standard CMOS process. Measurement results
show that the charge pump can operate under a 320 mV supply
and generate an output of 2.04 V in 0.1 milliseconds. Compared
with previous charge pumps designed in similar CMOS pro-
cesses, the proposed charge pump offers the best performance
 PENG et al.: CMOS STARTUP CHARGE PUMP WITH BODY BIAS AND BACKWARD CONTROL 1619

in terms of measured minimum supply voltage, pumping ef-

ficiency charge transferability, and capacitance drivability. Fi-
nally, conclusions are provided in Section VI.

II. PREVIOUS WORK

Previously, most CMOS charge pumps used two out-of-phase
clock signals to gradually accumulate and push the charge for- Fig. 1. Six-stage Dickson charge pump.
ward in each pumping capacitor along only one branch, such as
Dickson charge pump depicted in Fig. 1. The voltage fluctua- Fewer series stages are needed to achieve the same output
tion at each pumping node (i.e., each pumping capacitor) voltage. However, generating a higher clock voltage re-
of Dickson charge pump can be expressed as quires a complex clock generator, which consumes more
power.
(1) Static charge transfer switches (CTSs) refers to a type of
charge pump that uses dynamic feedback control to eliminate
voltage loss resulted from drop [9]. By using the predicted
where is the voltage amplitude of the clock signals,
high voltage in the later stages to control the earlier stages of
is the pumping capacitor, is the parasitic capacitance at
CTSs, the switches can be turned on/off more effectively, which
each pumping node, is the output current, and is the clock
addresses the third observation above.
frequency. If and are small enough, is large
Wu and Chang’s charge pump [11], shown in Fig. 2, has a
enough, and is the same as the supply voltage, (1) can be
modified CTSs structure for low voltage operation, and it offers
simplified as
a better voltage pumping gain than the Dickson charge pump.
The corresponding waveform of each node is also shown in
(2)
Fig. 2. During the time interval T1, the voltage at node 1 is
1 VDD, and the voltage at node 2 is 3 VDD. Thus, MN1 is
However, the diode-connected MOSFETs need to be turned on
off, and MP1 is on. The high voltage from node 2 is borrowed
for the Dickson charge pump to function, and thus must be
to completely turn on switch MS1, which transfers the charge
larger than the MOSFETs’ threshold voltage . The voltage
from the power supply (VDD) to node 1.
pumping gain for each stage is defined as
During the time interval T2, the voltage at node 1 increases
to 2 VDD, and the voltage at node 2 decreases to 2 VDD.
(3)
Thus, MN1 is turned on, MP1 is turned off, and MS1 can be
completely turned off to prevent the reverse charge sharing phe-
The following observations are made from the Dickson charge
nomenon between node 1 and the power supply VDD. Suc-
pump’s structure [9]:
ceeding stages of the charge pump operate similarly. Although
1. In every clock cycle, due to drop, there is a remaining
this charge pump offers some pumping efficiency improvement,
charge given by that cannot be trans-
it is not optimal for low voltage operation for the following
ferred from one stage to the next stage. Because the bulk
reasons:
terminals of the diode-connected MOSFETs are normally
1. Since charge from the power source is pushed into one
connected to ground (GND), this loss gets worse at later
CTSs branch, the “redistribution loss” [12] between the last
stages due to body effect, especially when the number of
stage and the output capacitor, i.e., between C6 and ,
stages increases. Hence, a scheme to eliminate drops
is not negligible. For example, during T2 the output ca-
would allow a nearly full charge transfer in each clock
pacitor might be discharged far below 7 VDD by a load;
cycle and improve charge pump efficiency.
when T3 occurs, the voltage at node 6 is much higher than
2. Each diode-connected switch device has an equivalent
the output voltage, which will cause non-negligible “redis-
drain-to-source resistance [12] estimated by
tribution loss” from the last stage to the output capacitor.
2. When a CTS is turned on, there is conduction loss
(4) in the channel. Increasing the turn-on gate-source voltage
and the device width can reduce the conduction loss [12].
where is the gate-source voltage, is the threshold Although in this charge pump, the CTSs can be turned on
voltage, L is the length, and W is the width. causes by a gate-source voltage of 2 VDD, if the supply voltage
conduction loss, which degrades pumping efficiency and is very low, 2 VDD may not be sufficient. Meanwhile,
charge transferability. A wider diode-connected switch de- increasing the width of a transistor also increases its abso-
vice with a shorter channel length can be used to reduce lute threshold voltage, e.g., in a 0.18 m standard CMOS
, but it will increase in a modern standard CMOS process [10], which is not good for low voltage operation.
process [10]. 3. When the CTSs are turned off, the reverse charge sharing
3. A higher clock voltage can transfer more charge in each phenomenon may not be completely eliminated [12]. If
clock cycle and more effectively turn on/off the switches the device length in the CTSs is short, reverse leakage
to decrease and the charge sharing phenomenon [9]. can occur between adjacent nodes. So, to reduce leakage,
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA. Downloaded on November 03,2023 at 08:57:17 UTC from IEEE Xplore. Restrictions apply.
 1620 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 6, JUNE 2014
Fig. 2. Circuit and corresponding voltage waveforms of the six-stage Wu and Chang charge pump [11].
Fig. 3. Six-stage linear charge pump circuit with all PMOS switches [13].
longer channel length can be used, but the redistribution of
MOSFETs’ channel charge would also decrease the charge
pumping efficiency.
4. The diode-connected MDO of the last stage still suffers
from body effect and threshold voltage loss.
In [13], the author proposed a six-stage linear charge pump
(LCP), shown in Fig. 3, which was modified from Wu and
Chang’s charge pump. With PMOS CTSs, the circuit utilizes
a systematic gate control method to achieve high pumping
efficiency. To avoid the body effect, all the bulks of PMOSs
and NMOSs (in deep n-well technology) are connected to the
corresponding sources. Several improvements are made in this
design. First, NMOSs in the branch of CTSs are replaced by
PMOSs, which reduces reverse charge sharing due to the lower
mobility of charge carriers, which are holes in PMOS channel.
Second, PMOS size has less impact on the absolute threshold
voltage than NMOS, and thus, wider devices can be used to
reduce conduction loss. Third, when VDD is low, the auxiliary
P7 cannot be turned on effectively if it is connected in the
same way as PMOSs in the earlier inverters. Thus, P7’s gate
is connected to M6’s gate to guarantee a sufficient gate-source
voltage to turn on. As a result, a diode connected NMOS (e.g.,
MDO in Wu and Chang’s charge pump) is not needed at the
last stage. Therefore, the LCP addresses problems 2, 3, and 4
of Wu and Chang’s charge pump. But if VDD is lower than
threshold voltage, LCP cannot turn on/off switches effectively.
In [14], a two-branch charge pump (TBCP) was implemented
with two CTS branches and a compensated structure in each
stage, as shown in Fig. 4, which solves problems 1 and 3 of Wu
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA. Downloaded on November 03,2023 at 08:57:17 UTC from IEEE Xplore. Restrictions apply.
and Chang’s charge pump. The control signals of branches A
and B are intertwined, and their clock signals are out of phase.
Using deep n-well technology, the bulk of an NMOS can be
connected to the source to avoid the body effect. During the time
interval T1, the voltage difference between node 1 and node
7 is VDD, and between node 2 and node 8 is 1 VDD.
Therefore, transistors MP7 and MN8 are turned on to transfer
charge from node 7 to node 8, but transistors MP1 and MN2 are
turned off to cut off the path from node 2 back to node 1. The
operation in the time interval T2 is similar to T1. Branches A
and B can be seen as two independent charge pump circuits, and
their output nodes are connected together to drive a capacitive
load. The voltage waveforms of nodes 1–6 and those of nodes
7–12 are out of phase, as shown in Fig. 4. Three advantages of
using this architecture are:
1. Using two compensated branches to transfer charge sig-
nificantly improves pumping efficiency and reduces output
ripples. Because two pumping branches can provide better
charge transferability, very large devices are not needed to
build the CTSs, which can lower the effect of the device
size on the threshold voltage. Meanwhile, the redistribu-
tion loss between the last stage and the output capacitor
can be reduced, since one of the two branches always pro-
vides current to keep the output voltage stable.
2. Compared to Wu and Chang’s charge pump, the CTSs in
the TBCP can achieve lower reverse charge sharing. For
example, during T1, MP1 and MN2 are turned off to block
the path of the charge reverse transferring from node 2
(higher voltage) to node 1 (lower voltage). So, the charge
in node 2 has to cross two MOSFETs to reach node 1,
significantly decreasing the reverse charge sharing.
3. The channel charge existing in adjacent PMOS and NMOS
can be mitigated when they are turned off. For example, if
MP1 and MN2 are large, then their channel charge cannot
be neglected. Because the charge is positive in MP1 and
negative in MN2, it will be neutralized when MP1 and
MN2 are turned off simultaneously. Thus, pumping effi-
ciency is improved.
 PENG et al.: CMOS STARTUP CHARGE PUMP WITH BODY BIAS AND BACKWARD CONTROL 1621

Fig. 4. Circuit structure and corresponding voltage waveforms of the six-stage two-branch charge pump [14].

Although the TBCP has many advantages, it is still not suit-

able for low voltage applications. If VDD is only several hun-
dred millivolts, the CTSs cannot be completely turned on. In re-
ality, the voltages of the last pumping nodes, i.e., nodes 6 and 12,
may not be VDD higher than the previous stage or VDD lower
than the next stage, and the charge transfer switches, MN6,
MP6, MN12, and MP12, cannot be effectively turned on.

III. SUBTHRESHOLD AND BODY-BIAS RING OSCILLATOR

When a charge pump is designed for low voltage power
supply applications, the first challenge is to build a ring os-
cillator, which can generate out-of-phase clock signals. The
oscillator must be able to work under a voltage supply of
several hundred millivolts. It should have a rail-to-rail output
swing, and the output current drivability (ability to drive the
pumping capacitors of the charge pump) should be as large
as possible. Since in the CMOS 0.18 m process the absolute
threshold voltage of a transistor is around 500 mV, if the
voltage supply is around 0.3 V, the device must operate in
the subthreshold region. However, a device operating in the
subthreshold region only permits a very small current flow due
to a weak inversion channel between its source and drain. This
reduces the oscillator’s drivability.
Body biasing a MOSFET can decrease its threshold voltage
and increase its inversion area, which then effectively increases
the device’s transient response and current drivability. For ex-
ample, the threshold voltage of an NMOS is expressed as
(5)
where is the gate voltage for which the channel is “as much
n-type as the substrate is p-type” [15], is the body-effect co-
efficient, is the strong inversion surface potential [16], and
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA. Downloaded on November 03,2023 at 08:57:17 UTC from IEEE Xplore. Restrictions apply.
Fig. 5. Five-stage subthreshold and body bias ring oscillator with two parallel
buffer stages.
is the voltage difference between the device’s source and
bulk.
If the voltage difference is decreased to a negative value,
the threshold voltage will decrease to below . A similar situ-
ation also occurs in PMOS when its bulk is connected to a lower
voltage than its source voltage. Therefore, implementing body
bias technique in deep n-well process can allow standard CMOS
devices to function under a low voltage supply. However, a body
bias voltage needs to be carefully chosen to effectively decrease
threshold voltage and properly improve current drivability. If
the body bias voltage of an NMOS is too large, a strong current
would flow from the bulk to the source, which can cause a se-
rious functional problem for the device. Normally, the typical
body bias voltage for an NMOS in a standard CMOS process
 1622 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 6, JUNE 2014

Fig. 6. (a) Circuit and (b) corresponding waveforms of the proposed six-stage charge pump.

is between 100 mV and 300 mV, and it decreases the threshold
voltage by approximately 20%.
The designed subthreshold and body-bias ring oscillator is
shown in Fig. 5. Clk and clkb are two out of phase clock sig-
nals. The oscillator has five stages of inverters operating in the
subthreshold region. The W/L size ratio of the devices is kept
small to lower the [10]. Two phase shifting circuits with
large size buffers are used to improve the clock output swing and
the current drivability because the clock generator has to drive
a total pumping capacitance of around 288 pF. Also, the buffers
help reduce glitches in the rising/falling edges of the clock out-
puts. If the signal clkb was generated by adding a large size in-
verter after buffer 1, there would be a time delay between clk and
clkb. Thus, two buffers are needed in parallel. Body-bias is ap-
plied to the MOSFETs constructing the inverters, phase shifters,
and buffers to lower the threshold voltage . The body bias
voltage can be generated by a simple resistor voltage divider.
NMOS EN is used to disable/enable the oscillator. The control
signal Vstart can come from the output of a step-up converter.
During the startup period of the step-up converter, Vstart is low,
which enables and initializes the ring oscillator. After startup,
the step-up converter can use its own high output voltage (sev-
eral volts) to power itself, and the high Vstart disables the ring
oscillator to save power. During the disabled period, because of
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA. Downloaded on November 03,2023 at 08:57:17 UTC from IEEE Xplore. Restrictions apply.
the small W/L size ratio of the inverters, the current flow through
the subthreshold PMOS in inverter 1 is negligible.
IV. PROPOSED SIX-STAGE CHARGE PUMP
The proposed six-stage charge pump circuit and the corre-
sponding voltage waveforms are illustrated in Fig. 6(a) and (b).
The clock signals clk and clkb are generated by the clock gener-
ator, as discussed above. Both have peak-to-peak amplitude of
VDD.
As shown in Fig. 6(a), branches A and B employ inter-
nally-boosted high voltages for backward dynamic control
(all the NMOS’s bulks are connected to the sources in deep
n-well, except MN6 and MN12). Branch A consists of NMOSs
MN1–MN6, PMOSs MP1–MP6, capacitors C1–C6, inverters
Inv1–Inv5, and output control stage N1 and P1. Branch B con-
sists of NMOSs MN7–MN12, PMOSs MP7–MP12, capacitors
C7–C12, inverters Inv6–Inv10, and output control stage N2
and P2. The bulks of all devices constructing the inverters are
connected to their sources. Through the inverter structure, the
control signal of each stage in branches A and B is “borrowed”
from the already established high voltages of the later stages.
For example, in branch B, the gate control signal of the seventh
stage is “borrowed” from the established voltages at nodes 3
and 1 through inverter Inv1. The “ ” sign indicates the high
 PENG et al.: CMOS STARTUP CHARGE PUMP WITH BODY BIAS AND BACKWARD CONTROL 1623

voltage node of the inverter, and the “ ” sign indicates the low
voltage node. The clock signals of branch A and branch B are
intertwined. The operation of the proposed charge pump circuit
is described in detail below.

A. The First and Second Pumping Stages

As shown in Fig. 6(a), the gates of inverters Inv6 and Inv7 are
controlled by node 8 and node 9 of the eighth and ninth stages of
branch B, and the inverters’ outputs are used to control the first
and second stages of branch A. In the time interval T1, the clock
signal clk is low and clkb is high. The voltage levels of node 1,
node 2, node 3, and node 4 are VDD, 3 VDD, 3 VDD, and
5 VDD, respectively, and the voltage levels of node 7, node
8, node 9 and node 10 are 2 VDD, 2 VDD, 4 VDD, and
4 VDD, respectively. The output of inverter Inv6 is pulled up
to node 9 (4 VDD), and the output of inverter Inv7 is pulled
down to node 8 (2 VDD). The gate-source voltage of MP1,
i.e., between the gate of MP1 and node 1, is 3 VDD. The
gate-source voltage of MN2, i.e., between the gate of MN2 and
node 2, is VDD. So, both MP1 and MN2 are tightly turned
off, and there is no chance for the charge to be reversely trans-
ferred from the high voltage of node 2 to the low voltage of
node 1. At the same time, the gate-source voltage of MN1 is
3 VDD, which can strongly turn on MN1 even under a low
voltage supply, and the charge can be directly transferred from
the power supply to capacitor C1.
Similarly, during the time interval T1, the output of inverter
Inv1 is pulled down to node 1 (VDD), and the output of inverter
Inv2 is pulled up to node 4 (5 VDD). The gate-source voltages
of MP7 and MN8 are VDD and 3 VDD, respectively,
and so the charge transfer switch MN8 can be turned on even
under a very low voltage supply VDD. However, because the
gate-source voltage of MP7 is only VDD, the body-bias
technique should be applied on MP7 to decrease its threshold
voltage for operation at low voltage.
For example, in our process, the threshold voltage of PMOSs
is about 400–500 mV, and the supply voltage VDD can get
as low as 320 mV. Thus, the size of this PMOS and its bias
level must be chosen carefully, depending on the process. In the
proposed charge pump, the bulk of MP7 can be connected to
node 1 as shown in Fig. 7, which can provide an approximate
body biasing voltage of VDD to reduce the threshold voltage
in the time interval T1. All the bulks (notated as letter b in
Fig. 6) of the other PMOSs in the two branches are biased in
the same way. Compared to TBCP, this structure can transfer
charge through PMOSs and NMOSs more efficiently under low
voltage supply due to the reduced PMOSs’ threshold voltage
and the lower equivalent drain-to-source on-resistance of both
PMOSs and NMOSs. First, the threshold voltage of PMOSs is
reduced by body biasing to turn on easier, which effectively re-
duces the equivalent drain-to-source on-resistance for the same
gate-source voltage. Second, from (4), the equivalent drain-to-
source on-resistance of NMOSs in the proposed charge pump
is lower because they have a higher gate-source voltage com-
pared to NMOSs in TBCP which has only gate-source
voltage. Thus, when the PMOS and NMOS switches turn on,
the total on-resistance is lower.
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA. Downloaded on November 03,2023 at 08:57:17 UTC from IEEE Xplore. Restrictions apply.
Fig. 7. Bulk connections of PMOS in the two branches of the proposed charge
pump.
Meanwhile, the bulk voltage of MP1, as shown in Fig. 7,
is higher than the source voltage by 1 VDD, which means
that the threshold voltage of MP1 is increased by body biasing,
assisting MP1 to turn off so as to reduce the reverse charge
sharing. The gate-source voltage of MN7, i.e., between the gate
of MN7 and power supply VDD, is 0 V, and thus MN7 can be
completely turned off, which prevents the charge from flowing
back to the power supply. During the time interval T2, the cir-
cuit’s operation is similar to that of operation in the time interval
T1.
As illustrated in Fig. 6(a), the third stage in branch A is
controlled by inverters Inv3 and Inv8. In the time interval T1,
the voltage levels of node 2, node 3, node 4, and node 5 are
3 VDD, 3 VDD, 5 VDD, and 5 VDD, respectively,
and the voltage levels of node 8, node 9, node 10 and node
11 are 2 VDD, 4 VDD, 4 VDD, and 6 VDD, respec-
tively. Therefore, the output of Inv3 is pulled down to node
3 (3 VDD), and the output of Inv8 is pulled up to node 11
(6 VDD). The gate-source voltage of MP2 is VDD, and
the gate-source voltage of MN3 is 3 VDD. Hence, the charge
can be transferred from node 2 to node 3. This operation is very
similar to that of the second stage in branch B. In the same way,
the operation of the third stage in branch B is similar to that of
the second stage in branch A.
The operations of the fourth and fifth stages are similar to
the third stage. The compensated structures of branch A and
branch B alternatively turn on and turn off the charge transfer
switches. Thus, in any time interval, charge is always pumped to
the output by one of the branches, and the output voltage ripples
are reduced.
 1624 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 6, JUNE 2014

B. The Last Stage and Initial Voltage Startup which can transfer more charge and decrease the redistri-
bution loss.
The last stage includes the 6th stage in branch A and the 12th
Third, body biasing is only applied to PMOS and the last
stage in branch B. Their gate control signals come from the in-
stage NMOS to lower the , which can reduce the body
verters N1-P1 and N2-P2. In the preceding stages, the inverters
leakage current.
borrow voltages of later stages to supply their plus terminals, and
Fourth, the two branches utilizing both NMOS and PMOS
so they have 2 VDD between their plus and minus terminals
can reduce the reverse charge sharing loss.
to operate. However, the last stage has no next stage from which
Finally, all previous designs barely described how to gen-
to borrow a high voltage. So, if VDD is low, the inverters do
erate the two out-of-phase clock signals under low voltage
not have enough overdrive voltage to turn on N1/N2 and P1/P2.
supply with a standard CMOS process. Actually, this is a
Therefore, the connection of the last stage’s inverters is modi-
very important part in startup charge pump design. In this
fied, as shown in Fig. 6(a). During the time interval T1, the gate
work, a low voltage ring oscillator is presented and de-
voltage and source voltage (node ) of P1 are 5 VDD and
scribed in detail.
7 VDD, respectively, and the gate voltage and source voltage
of N1 are both 6 VDD. Thus, P1 is turned on, N1 is turned off,
V. VERIFICATION AND DISCUSSION
and the gate of the 12th stage is pulled up to 7 VDD. A similar
situation occurs with N2 and P2 in branch A, and the gate voltage A. Simulation and Comparisons
of the sixth stage is pulled down to 5 VDD. The operation in
A startup charge pump only works in the startup period of
the time interval T2 is similar, which guarantees enough voltage
an energy harvesting step-up converter. Its main function is to
to turn on/off MP6 and MP12 to reduce the redistribution loss be-
transfer the charge to a startup capacitor [4], [6]. Therefore, the
tween the last stage and the output capacitor. However, during
ramp-up time and capacitance drivability are important design
T1, the gate-source voltage of MN12 is only 1 VDD, and so
specifications. The pumping capacitors of a startup charge pump
cross-coupling the bulk of MN12 to node 6 is implemented to
play an important part in the charge pump’s performance and oc-
reduce its , as shown in Fig. 6(a). Also, the size of MN12
cupy a large silicon area [14]. Thus, choosing a proper capacitor
and MN6 is larger than that of previous stage switches, in order
size is very important to compare the startup performance of dif-
to improve their charge transferability.
ferent charge pumps under a low voltage supply. Generally, for
In time interval T1, MP6 is turned on to transfer the charge
charge pumps, the charge transferability to a capacitor decreases
from node 6 to the output node, but MP12 is turned off to cut off
linearly with increased output voltage, and so does its pumping
the path from the output node back to node 12. Similarly, during
efficiency [9]. To achieve higher charge transfer-
time interval T2, MP6 is turned off, and MP12 is turned on.
ability at a fixed output voltage, the pumping capacitor’s size
Therefore, in both T1 and T2, output capacitive load is driven
should be as large as possible. For a fair comparison between
by either of the two branches alternatively, which effectively
different charge pumps, they must have the same total pumping
lowers output voltage ripple and improves pumping efficiency.
capacitance [14]. Hence, the total pumping capacitance in the
Also, when output current increases, degradation of the output
proposed charge pump, the linear charge pump (LCP), and the
voltage is less severe than it would be if only one charge trans-
two-branch charge pump (TBCP) is set to 24 pF, 48 pF (24 2),
ferring branch is used.
and 24 pF, respectively. All of these charge pumps consist of six
When the charge pump starts up, the voltage in each pumping
stages.
node is not established; initially, most of the devices work in the
Higher output charge transferability results in a faster output
subthreshold region. To help establish the initial state, rather than
ramp-up time for a specified load capacitance [4]. Thus, we
using diode-connected devices as in [11], the threshold voltage
can easily calculate the required linear charge transferability by
of the NMOSs in the earlier stages is made smaller than those in
charging up the output voltage to a specified level within a given
the later stages. In our process, a smaller threshold voltage can
output ramp-up time [9]. The linear ramp-up current can be cal-
be achieved by reducing the width-to-length ratio of the device
culated as
[10]. However, small width-to-length ratio limits the amount of
charge flow through the switches. Thus, the width-to-length ratio
(5)
is gradually increased from the earlier stages to the later stages.
where is the output current to a capacitor of the charge pump,
C. Advantages of the Proposed Charge Pump
is the load capacitance, is the output voltage, and
The proposed charge pump demonstrates the following ad- is the output ramp-up time. In the proposed charge
vantages over the previous design, while working under low pump design, the output load capacitor is chosen to be around
voltage supply: 50.7 pF, which is the same as the output load capacitors in the
First, under low voltage supply, body biasing and back- LCP and the TBCP.
ward control can turn on/off the MOSFETs more effec- The proposed charge pump, the linear charge pump (LCP),
tively than TBCP. Higher gate-source voltage and lower and the two-branch charge pump (TBCP) are designed using
threshold voltage largely reduce the conduction loss due the same subthreshold and body-bias oscillator described in
to . Section III. Fig. 8 shows the simulated signals, clk and clkb,
Second, the last stage of the two branches is modified of the ring oscillator under a supply of 300 mV. The clock
to more effectively turn on/off under low voltage supply, frequency is around 450 kHz.
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA. Downloaded on November 03,2023 at 08:57:17 UTC from IEEE Xplore. Restrictions apply.
 PENG et al.: CMOS STARTUP CHARGE PUMP WITH BODY BIAS AND BACKWARD CONTROL 1625

Fig. 8. Simulated clkb and clk waveforms from the proposed ring oscillator
under 300 mV power supply (clock frequency kHz).

The 0.18 m standard CMOS device model is used to verify

the design of all three charge pumps. Fig. 9(a), (b), (c), and (d)
show the output voltage versus. time of the proposed charge
pump (this work), the two-branch charge pump (TBCP), and
the linear charge pump (LCP) with the same capacitive load
under power supplies of 320 mV, 360 mV, 400 mV, and 440 mV.
As shown in Fig. 9, the simulated output voltage of the pro-
posed charge pump is much higher than those of the other charge
pumps. The ramp-up time of the proposed charge pump is also
the fastest among the three. So, from (5), the proposed charge
pump obviously has the highest ramp-up current, i.e., charge
transferability. Table I shows the calculated ramp-up current of
each charge pump based on simulation results under a supply of
400 mV and with of 50.7 pF.

B. Silicon Verification
Three test chips have been fabricated in a 0.18 m standard
CMOS process to verify the proposed charge pump circuit. The
photographs of the three test chips are shown in Fig. 10. The test
chips include the proposed six-stage charge pump with pumping
capacitors of 24 pF each, the six-stage linear charge pump with
pumping capacitors of 48 pF each, and the six-stage two-branch
charge pump with pumping capacitors of 24 pF each.
Fig. 11 shows the measured output voltages of the three
charge pumps with capacitor load. The measurement results in
Fig. 11 are somewhat lower than the simulated results in Fig. 9,
likely because of the parasitic resistance and capacitance of the
testing environment, such as probes, cables and instruments.
The TBCP and the LCP do not function properly when the
voltage power supply VDD is below 0.4 V. After the voltage Fig. 9. Simulated output voltages with a 50.7 pF capacitor load of the proposed
power supply VDD exceeds 0.55 V, the TBCP performs better charge pump, two-branch charge pump, and linear charge pump with different
power supply voltages (VDD).
than the proposed charge pump. Because VDD becomes larger
than the threshold voltage, the large MOSFETs in the TBCP
TABLE I
no longer operate in the subthreshold region and can turn SIMULATION RESULTS OF CHARGE PUMPS’ OUTPUT RAMP-UP CURRENT AT
on/off normally. Meanwhile, for the proposed charge pump, 400 MV SUPPLY VOLTAGE
as mentioned in Section IV.B, the NMOSs in the earlier stages
are made smaller than those in the later stages. Thus, they
limit the charge flow through the switches. Moreover, as VDD
increases, the body-biased PMOSs in the proposed charge
pump will introduce more body leakage current through the
forward biased pn junction (source to bulk).
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA. Downloaded on November 03,2023 at 08:57:17 UTC from IEEE Xplore. Restrictions apply.
 1626 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 6, JUNE 2014

Fig. 10. Photographs of different charge pump circuits: (a) 6-stage two-branch
charge pump; (b) 6-stage linear charge pump; (c) 6-stage proposed charge pump
(this work).

Fig. 13. Measured ramp-up time of the different charge pumps output voltage
with 50.7 pF capacitor load under VDD 0.4 V, where the stages are six: (a) linear
charge pump; (b) two-branch charge pump; (c) this work.

TABLE II
MEASUREMENT RESULT OF THE THREE CHARGE PUMPS’ OUTPUT RAMP-UP
Fig. 11. Measured output voltages with capacitor load of different charge CURRENT AT 400 MV SUPPLY VOLTAGE
pumps versus different power supply voltages, where the stages are six.

Nonetheless, the proposed charge pump has the best perfor-

mance under a supply voltage between the 320 mV and 500 mV,
and its output voltage is close to the ideal value (7 VDD). As a
result, the proposed charge pump performs the best when being
used to start up a step-up converter which harvests from a low en-
ergy source of 300 mV to 500 mV [2], [3]. Fig. 12 shows detailed
Fig. 12. Proposed charge pump’s measurement of pump efficiency information of the proposed charge pump’s measured pumping
. efficiency under different voltage supplies.
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA. Downloaded on November 03,2023 at 08:57:17 UTC from IEEE Xplore. Restrictions apply.
 PENG et al.: CMOS STARTUP CHARGE PUMP WITH BODY BIAS AND BACKWARD CONTROL
TABLE III
PERFORMANCE SUMMARY
Unlike traditional charge pumps, the available output current
level from a startup charge pump is very limited [4]. It is neither
practical nor necessary to measure the output currents from the
three charge pumps. From (5), the ramp-up time is an important
factor in determining charge transferability, i.e., a startup charge
pump in which output voltage rises to a higher voltage more
quickly to a start up a step-up converter has better charge trans-
ferability. As shown in Fig. 11, since the LCP and the TBCP
have no functionality under 0.4 V, it is difficult to compare them
to the proposed charge pump under a power supply below 0.4 V.
Thus, the output ramp-up times of these charge pumps are mea-
sured when the power supply is 0.4 V for fair comparison.
Fig. 13(a), (b), and (c) illustrate the measured output ramp-up
time of the linear charge pump (LCP), the two-branch charge
pump (TBCP), and the proposed charge pump (this work)
50.7 pF capacitor load under a supply of 0.4 V. The measure-
ment equipment includes a Tektronix oscilloscope (TDS3000B)
and American metal probes (Model 72A-C3/05) touching the
pads of these test chips. The oscilloscope and the probes added
about 30 pF extra capacitance to the charge pump’s load. Also,
some additional parasitic capacitance (such as cable) was not
accounted for. For this reason, the simulated ramp-up time
is much shorter than the measured value. However, using
mathematical scaling method, it is still valid to compare the
ramp-up current of these charge pumps. Table II shows the
calculated values of the ramp-up current of the three charge
pumps based on (5), assuming and including all of
the test environment’s capacitors. Although the measurement
results are lower than the simulation results, the performance
of the proposed charge pump is still the best among the three.
Table III summarizes the performance of the proposed
charge pump and compares it with state-of-the-art designs. The
charge pumps in [4] and [19] could operate at a much lower
voltage supply. However, they were fabricated in a 65 nm
CMOS process, which offered devices with lower threshold
voltage. The charge pump in [7] also has a lower minimum
operating voltage, but it only generates a pulse signal with very
limited charge transferability. [17] does not provide process
information, but its MOSFETs can effectively turn on/off under
330 mV supply without any difficulty. Considering the overall
performance, the proposed charge pump achieves the lowest
operating voltage, the largest capacitance driving capability
and the best pumping efficiency.
VI. CONCLUSION
A new CMOS charge pump module with integrated
two-phase clock generator has been designed to provide
startup function for energy harvesting step-up converters.
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA. Downloaded on November 03,2023 at 08:57:17 UTC from IEEE Xplore. Restrictions apply.
1627
Using subthreshold operation and body bias technique, the
charge pump and its clock generator can operate at as low
as 320 mV power supply. Using internal boosted voltages,
the backward control scheme increases the clock amplitude,
and together with a compensated two-branch structure, it can
completely turn on and off the CTSs under a low voltage
supply. Thus, the reverse charge sharing phenomenon and
switching loss are mitigated sharply. Meanwhile, a modified
output structure increases the last pumping stage’s drivability
by avoiding the diode connection, which further improves the
pumping efficiency. The experimental results have shown that
output voltage rises 10 times faster compared to previous de-
signs with the same total capacitance at 400 mV power supply,
which implies a much better output charge transferability. In
conclusion, the proposed charge pump circuit can be effectively
used to start up a step-up converter in energy harvesting appli-
cations, where the available voltage can be as low as 320 mV,
which is below the threshold voltage of a standard 0.18 m
CMOS process. Compared with other charge pumps designed
in similar processes, the proposed charge pump has the highest
charge transferability, the largest capacitance drivability and
the highest pumping efficiency (89%).
ACKNOWLEDGMENT
The authors would like to thank TowerJazz Semiconductor
for chip fabrication. The authors also wish to acknowledge
the assistance and support of the NSF CDADIC. This project
was partially supported by an NSF CAREER Award (ECCS-
(ECCS-0845849), KFRI (Korean Food Research Institute) uu-
food project and the Korean Government (NRF-2011-220-
(NRF-2011-220-D00084).
REFERENCES
[1] C. Alippi and C. Galperti, “An adaptive system for optimal solar energy
harvesting in wireless sensor network nodes,” IEEE Trans. Circuits
Syst.—I, vol. 55, no. 6, pp. 1742–1750, Jul. 2008.
[2] C. Donovan, A. Dewan, H. Peng, D. Heo, and H. Beyenal, “Power
management system for a 2.5 W remote sensor powered by a sediment
microbial fuel cell,” J. Power Source, pp. 1171–1177, 2011.
[3] C. Donovan, A. Dewan, D. Heo, and H. Beyenal, “Batteryless, wire-
less sensor powered by a sediment microbial fuel cell,” Environmental
Science and Technology, vol. 42, no. 22, pp. 8591–8596, 2008.
[4] P. H. Chen et al., “Startup techniques for 95 mV step-up converter
by capacitor pass-on scheme and -tuned oscillator with fixed
charge programming,” IEEE J. Solid-State Circuits, vol. 47, no. 5, pp.
1252–1260, May 2012.
[5] E. J. Carlson et al., “A 20 mV input boost converter with efficient dig-
ital control for thermoelectric energy harvesting,” IEEE J. Solid-State
Circuits, vol. 45, no. 4, pp. 741–750, Apr. 2010.
[6] Y. O. Ramadass and A. P. Chandrakasan, “A battery-less thermoelec-
tric energy harvesting interface circuit with 35 mV startup voltage,”
IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 333–341, Jan. 2011.
 1628 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 6, JUNE 2014
[7] J. Holleman et al., “A compact pulse-based charge pump in 0.13 m
CMOS,” in Proc. IEEE Custom Int. Circuits Conf., 2007, pp. 381–384.
[8] A. Worapishet and J. B. Hughes, “Performance enhancement of
switched-current techniques using subthreshold MOS operation,”
IEEE Trans. Circuits Syst.—I, vol. 55, no. 11, pp. 3582–3592, Dec.
2008.
[9] F. Pan and T. Samaddar, Charge Pump Circuit Design. New York:
McGraw-Hill, 2006.
[10] Jazz Semiconductor Design Application Manual. Newport Beach,
CA: Jazz Semiconductor Products Inc., 2012.
[11] J.-T. Wu and K.-L. Chang, “MOS charge pump for low voltage oper-
ation,” IEEE J. Solid-State Circuits, vol. 33, no. 4, pp. 592–597, Apr.
1998.
[12] L. Su and D.-S. Ma, “Design and optimization of integrated
low-voltage low-power monolithic CMOS charge pumps,” in Proc.
Int. Power Electron., Electrical Drives, Automation Motion, 2008, pp.
43–48.
[13] F. Su and W.-H. Ki, “Gate control strategies for high efficiency charge
pumps,” in Proc. Int. Symp. Circuits Syst., 2005, pp. 1907–1910.
[14] M.-D. Ker, S.-L. Chen, and C.-S. Tsai, “Design of charge pump cir-
cuit with consideration of gate-oxide reliability in low-voltage CMOS
process,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1100–1107,
May 2006.
[15] B. Razavi, Design of Analog CMOS Integrated Circuits. New York:
McGraw-Hill, 2001.
[16] P.-E. Allen and D.-R. Holbreg, CMOS Analog Circuit Design, 2nd
ed. Oxford: Oxford Univ. Press, 2002.
[17] K. Kadirvel et al., “A 300 nA energy-harvesting charger with battery
management for solar and thermoelectric energy harvesign,” in Proc.
ISSCC, 2012, pp. 106–107.
[18] S. Matsumoto, T. Shodai, and Y. Kanai, “A novel strategy of a con-
trol IC for boost converter with ultra low voltage input and maximum
power point tracking for a single solar cell application,” in Proc. Int
Symp. Power Semiconductor Devices ICs, June 2009, pp. 180–183.
[19] P. Chen et al., “0.18-V input charge pump with forward body biasing in
startup circuit using 65 nm CMOS,” in Proc. IEEE Custom Int. Circuits
Conf., Sept. 2010, pp. 239–242.
[20] Y. M. Sun and X. B. Wu, “Subthreshold voltage startup module for
step-up DC-DC converter,” Electron. Lett., vol. 46, pp. 373–374, 2010.
Huan Peng received the B.S. and M.S. degrees from
Huazhong University of Science and Technology
(HUST), Hubei, China, in 2005 and 2007, respec-
tively, both in electrical engineering. He is currently
working toward the Ph.D. degree in electrical en-
gineering at Washington State University, Pullman,
WA, USA.
In late 2004, he joined the laboratory of the Sci-
ence and Technology Dept., HUST, China as an Un-
dergraduate Research Assistant. From 2005 to 2008,
he was an Analog IC designer for Asian Microelec-
tronics Co., LTD, Wuhan, China, where he was responsible for the transistor
level design for DCDC converters, power management for low power circuits,
and analog IC design. His research interests are low power high efficiency power
management integrated circuits, energy harvesting circuits and analog/mixed
signal ICs.
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA. Downloaded on November 03,2023 at 08:57:17 UTC from IEEE Xplore. Restrictions apply.
Nghia Tang received the B.S. in electrical engi-
neering, magna cum laude, from Washington State
University (WSU), Pullman, WA, USA, in 2009,
where he is currently working toward the Ph.D. de-
gree in electrical engineering. His doctoral research
primarily focuses on analog circuits, especially
power management ICs.
He is currently involved in the design of envelope
tracking bias modulators for power amplifiers, high
speed regulators for multi-core processors, and low
voltage power management systems for energy har-
vesting applications.
Mr. Tang was a recipient of the Royal D. Sloan scholarship from the WSU
electrical engineering department during his undergraduate study.
Youngoo Yang (S’99–M’02) was born in Hamyang,
Korea, in 1969. He received the Ph.D. degree in elec-
trical and electronic engineering from the Pohang
University of Science and Technology (Postech),
Pohang, Korea, in 2002.
From 2002 to 2005, he was with Skyworks
Solutions, Inc., Newbury Park, CA, USA, where
he designed power amplifiers for various cellular
handsets. Since March 2005, he has been with the
School of Electronic and Electrical Engineering,
Sungkyunkwan University, Suwon, Korea, where he
is currently an Associate Professor and a Director of the RFID/USN Integrated
Circuit Research Center. His research interests include power amplifier design,
RF transmitters, RFIC design, integrated circuit design for RFID/USN systems,
and modeling of high power amplifiers or devices.
Deukhyoun Heo (S’97–M’00–SM’13) received
the B.S.E.E. degree in electrical engineering from
Kyoungpuk National University, Daegu, Korea, in
1989, the M.S.E.E. degree in electrical engineering
from Pohang University of Science and Technology
(POSTECH), Pohang, Korea, in 1997, and the Ph.D.
degree in electrical and computer engineering from
the Georgia Institute of Technology, Atlanta, GA,
USA, in 2000.
In 2000, he joined the National Semiconductor
Corporation, where he was a Senior Design Engineer
involved in the development of silicon RFICs for cellular applications. Since the
fall of 2003, he has been an Associate Professor with the Electrical Engineering
and Computer Science Department, Washington State University, Pullman,
WA, USA. His research interests include RF/microwave/opto transceiver
design based on CMOS, SiGe BiCMOS, and GaAs technologies for wireless
and wireline data communications, battery-less wireless sensors and intelligent
power management systems for sustainable energy sources, adaptive beam
former for phased-array communications, low-power high date-rate wireless
links for biomedical applications, and multilayer module development for
system-in-package solutions. He has served as an associate editor for the IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II: EXPRESS
BRIEFS (2007–2009) and has served as an Associate Editor for the IEEE
TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES.
Dr. Heo has been a member of the Technical Program Committee of IEEE
Microwave Theory and Techniques Society (IEEE MTTS-S) International Mi-
crowave Symposium (IMS) and the International Symposium of Circuit and
Systems (ISCAS). He received the 2009 National Science Foundation (NSF)
CAREER Award.