Department of Computer Science and Engineering

National Institute of Technology Calicut

Kozhikode - 673 601, Kerala, India
CS2001D-LOGIC DESIGN
Tentative Course Details – Monsoon Semester 2023
Lecture:
Lecture Slot: A1, A2
Lecture Hours: Monday 09.00 am – 09.50 pm, 02.00 pm – 02.50 pm
Wednesday 12.00 pm – 12.50 pm, 01.00 pm – 01.50 pm
Thursday 11.00 am – 11.50 am, 04.00 pm – 04.50 pm
Friday 10.00 am – 10.50 am, 03.00 pm – 03.50 pm

Lecture Hall: ELHC-401, 203

Instructors:
Name: T M Srinivasa Email: srini_2007@nitc.ac.in
Nirmal Kumar Boran nirmalkboran@nitc.ac.in

Course Outcomes:
CO1: Learn and understand various number systems and their applications in digital design.
CO2: Design and implement logic functions utilizing logic gates and programmable logic.
CO3: Learn and understand HDLs used to implement digital systems.

Syllabus

Module 1
Number systems and codes, Boolean algebra: postulates and theorems, constants, variables and functions,
switching algebra, Boolean functions, logical operations, Karnaugh map: prime cubes, the minimum sum
of products and product of sums, Introduction of HDLs and their syntax.
Module 2
The Quine-McCuskey algorithm, prime implicant chart, cyclic prime implicant chart, Patrick’s method,
Combinational Logic: introduction, analysis, and design of combinational logic circuits, parallel adders,
and look-ahead adders, comparators, decoders and encoders, code conversion, multiplexers and de-
multiplexers, parity generators and checkers.

Module 3
Programmable Logic Devices, ROMs, PALs, PLAs, PLA folding, design for testability. Introduction to
sequential circuits, memory elements, latches.

Module 4
Flip-flops, analysis of sequential circuits, state tables, state diagrams, design of sequential circuits,
excitation tables, Mealy and Moore models, registers, shift registers, and counters.

References:
1. T. L. Floyd and R. P. Jain, Digital Fundamentals, 8/e, Pearson Education, 2006.
2. C. H. Roth, Jr., and L. L. Kinney, Fundamentals of Logic Design, 6/e, Cengage Learning, 2009.
3. M. M. Mano and M. D. Ciletti, Digital Design, 4/e, Pearson Education, 2008.
4. B. J. LaMeres, Introduction to Logic Circuits & Logic Design with Verilog, 1/e, Springer, 2017.

Grading & Evaluation policy

Weightage for different evaluations:

1. Mid Exam: 30%

2. Assignment/Quiz/Surprise test: 30%

4. Final Exam: 40% (All Modules)

Grading Policies:

• Grading will be Relative. Even though the grading will be relative, the probable mapping of
marks to grades is as follows: 90-100: S, 80-89 A, 70-79: B, 60-69: C, 50-59: D, 40-49: E, 0-39:F

• Absence for Exams/Quizzes/Assignments/Surprise tests/Programming tests without prior written

permission from the respective Instructor/Faculty would be equivalent to zero marks in the
corresponding exam/Quiz/Assignment/Surprise test/Programming test.

• There will be no makeup exams except in case of genuine reasons. In such exceptional cases, the
student must discuss the matter with the instructor and get written permission from FA and HOD
at least one day before the exam date.

• All issues regarding the valuation of exams and quizzes must be resolved within the stipulated
schedule.

Standard of Conduct:

• Each student is expected to adhere to high standards of ethical conduct, especially those related to
cheating and plagiarism.

• Any work submitted MUST BE on individual effort.

• Any academic dishonesty will result in zero marks in the corresponding exam or quiz and will be
reported to the department council for record-keeping and permission to assign an F grade in the
course.

• 80% attendance is mandatory for each student for the course, and there will be no compromise.
• Use of mobile phones is strictly prohibited during class hours.
• More details on Academic Integrity:
https://minerva.nitc.ac.in/sites/default/files/attachments/news/Academic-
IntegrityNew%20%281%29.pdf