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Kiichiro TANIGUCHI,
Terukazu SATO, Takashi NABESHIMA, and Kimihiro NISHIJIMA
Faculty of Engineering
Oita University
700, Dannoharu,
Oita, 870-1192 Japan
E-mail: v08e2020@mail.cc.oita-u.ac.jp
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PEDS2009
window voltage when a clock signal is not applied. is automatically fixed so as the output voltage becomes
nearly Vr. The transfer function of PWM controller is
S1 L rL io expressed by the following expression.
ΔV1 ( s ) 1 + sT (3)
iL =
rC ΔV A ( s ) VOH
Vi S2 Vo RL
During the comparator output voltage vl is high level, the
C
integrated voltage vn of the negative comparator input rises
vG up until it reaches vH. vl is then changed to low level and vn
R1 C1
begins to descend. If the clock signal is applied to the positive
comparator input before vn reaches vL, the comparator output
vn is forced to high level.
v1
U As dynamic performance of the PWM controller is mainly
determined by the time constant TC= R1C1, it is necessary to
vp
make a value of TC large in order to obtain good transient
performance for external disturbances. However the large
U : Comparator Ra Rb Vr time constant TC at the high switching frequency results small
amplitude of triangular voltage vn and it may easily lead
Fig. 1. Circuit diagram of the buck converter controlled by conventional
undesirable irregular switching due to the incoming switching
hysteretic PWM controller noise. To solve this problem with small time constant, this
vl means with large amplitude of triangular voltage, the output
error voltage is amplified and then fed to inverse input of the
V OH comparator. In this case, the gain of error amplifier over the
switching frequency is not needed to be high. Because the
frequency component of the output transient voltage is much
0 lower than that of the switching noise. Therefore the
vp
operational amplifier employed to the error amplifier is not
necessary to have high GBW.
VH
VL III. ANALYSIS OF THE CONTROL CIRCUIT
0 In the previous study [5], the transfer functions of the
vn hysteretic PWM controller a ramp signal as a perturbation of
the input signal. Fig. 4 shows key waveforms of hysteretic
VH comparator.
VL
io
0
Fig. 2. Operating waveforms of hysteretic comparator DC − DC Converter RL
level output voltage VOH, low level output voltage VOL, and Ri
resisters Ra Rb as follows expression (1)(2). vn Cf Rf
v1
Ra Rb (1) U1
V = H v + A V OH
Ra + Rb Ra + Rb vp
Ra Rb (2)
VL = vA + VOL U2
Ra + Rb Ra + Rb U1 : Comparator vA
Ra Rb
Vr
The output voltage of the comparator positive input is VH U 2 : OP.amp
when synchronizing with the fixed frequency that set by Clock
outside clock signal of the small duty. In this way, switching
cycle is determined. On the other hand, when the clock signal Fig. 3. Circuit diagram of buck converter controlled by proposed hysteretic
is applied to the positive comparator input, its output is PWM controller
forced to high level even before vn reaches VL. Then vn rises
up until it reaches VH. Hence the clock signal determines the
timing of the turn on of the main switch S1 and the duty ratio
1195
PEDS2009
1196
PEDS2009
20
and the line characteristics of output voltage. As seen form
figure, no steady-state error was observed on the output 10
90
Tc=12.9u
Tc=27.1u
Phase[degree]
Tc=52.8u
45
0
100 1000 10000 100000
Frequency[Hz]
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PEDS2009
40
Tc=12.9u
30
Tc=27.1u
V:50mV/div.
Tc=52.8u H:20μs/div.
Gain[dB]
20
20A/div.
10
1.2V Tc=27μs
Vo
0
50mV Without synchronization
-10
100 1000 10000 100000
Frequency[Hz]
90 1.2V Tc=27μs
Vo
Tc=12.9u
Tc=27.1u 50mV synchronization
Phase[degree]
Tc=52.8u
45 10A
Io
0
100 1000 10000 100000
0A
Frequency[Hz]
20 1.4
1.35
Output voltage Vo[V]
10 1.3
Gain[dB]
1.25
0 1.2
1.15
-10 1.1
1.05
-20 1
100 1000 10000 100000 1000000 10000000 0 2 4 6 8 10
Frequency[Hz] Load current Io[A]
90 1.4
45 1.35
Output voltage Vo[V]
Phase[degree]
0 1.3
-45 1.25
-90 1.2
-135 1.15
1.1
-180
1.05
-225
1
-270 3 4 5 6 7
100 1000 10000 100000 1000000 10000000
Frequency[Hz] Input voltage Vi[V]
1198
PEDS2009
V. CONCLUSION
A new robust PWM control method with inherent
derivative characteristics at constant switching frequency is
proposed and analyzed. As a result, it was verified that the
converter controlled by the proposed PWM method provides
excellent transient performances and the stable switching
action. The use of small time constant with large gain
improve settling time and remove the irregular switching
action under the same control bandwidth.
REFERENCES
[1] R. Redl, and N. O. Socal ‘’Near-Optimum Dynamic Regulation of DC-
DC Converters Using Feed-Forward of Output Current and Input
Voltage with Current-Mde Control,’’ IEEE Trans. On Power
Electronics, Vol.PE-1, No.3, 1986, pp. 181-192.
[2] M. T. Zang, M. M Jovanovic and F. C. Lee,’’Analysis and Evaluation
of Interleaving Techniques in Forward Converters,’’IEEE Trans. On
Power Electronics, Vol.13, No.14, 1998, pp. 690-698.
[3] W. Huang, ’’A New Control for Multi-Phase Buck Converter with Fast
Transient Response,’’ Proc. Of Applied Power Electronics Conference,
2001, pp.273-279.
[4] R. Miftakhutdnov, ‘’Analysis and Optimization of Synchronous Buck
Converter at High Slew-Rate Load Current Transients,’’Proc. Of
Power Electronics Specialalists Conference, 2000, pp. 714-720.
[5] T. Nabeshima T. Sato, S. Yoshida, S. Chiba and K. Onda, ‘’Analysis
and Design Considerations of a buck Converter with a hysteretic PWM
controller,’’in Proceedings of Power Electronics Specialists
Conference, pp. 1711-1716.
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