Registration Number : 22BCE3969

Name : Jai Sharma

Vellore Institute of Technology

School of Electronics Engineering
Department of Communication Engineering

Task No. 5 Reg. No. : 22BCE3969

Student Name : Jai Sharma

Class ID : VL2023240104530

L1+L2
Course Code : BECE 102P Slot & Semester :
Fall Semester
(2023-24)

Digital Systems
Course Name: Theory Slot No. : 1
Design Lab

Task Title : Design and Verilog modelling of various sequential

elements

Date of Exp. : 30-10-2023 Date of Submission : 10-11-2023

Faculty Name: Dr. HENRIDASS
Registration Number : 22BCE3969
Name : Jai Sharma

QUESTION 1
● Aim: Design and simulate a simple 8-bit microprocessor’s ALU unit which
performs arithmetic and logical operations (shown in below table) on two
8-bit inputs [7:0] A and [7:0] B. Write the Verilog HDL code in behavioural
modelling.
● Verilog Code & Testbench:
Registration Number : 22BCE3969
Name : Jai Sharma

● Outputs:
Registration Number : 22BCE3969
Name : Jai Sharma

QUESTION 2
● Aim: Design an automated vending machine, which dispatches a chocolate
after deposition of 15 rupees. The machine has only one coin slot to receive
coins from customers’ one coin at a time. In addition, the machine receives
only 10 (D) or 5 (N) rupee coins and it doesn’t give any change if the total
deposited amount exceeds 15 rupees. Simulate and verify the designed FSM
using Verilog HDL.
● Verilog Code:
Registration Number : 22BCE3969
Name : Jai Sharma

● Testbench:
Registration Number : 22BCE3969
Name : Jai Sharma

● Outputs:
Registration Number : 22BCE3969
Name : Jai Sharma

QUESTION 3
● Aim: Design a Moore non-overlapping sequence detector to detect a
sequence of 10101. Implement the same using D Flip-flop.
● Solution:
Registration Number : 22BCE3969
Name : Jai Sharma
Registration Number : 22BCE3969
Name : Jai Sharma

● Verilog Code & Testbench:

Registration Number : 22BCE3969
Name : Jai Sharma

● Outputs:

● Result:
○ 8-bit ALU Design: The Verilog HDL code for the 8-bit ALU was
successfully implemented and simulated. The ALU performs the specified
arithmetic and logical operations on two 8-bit inputs A and B, as outlined in
the provided table. The behavioural modelling ensures accurate
functionality, and simulation results demonstrate proper operation for
various input combinations.
○ Automated Vending Machine Design: The Verilog HDL code for the
automated vending machine has been successfully developed and
simulated. The finite state machine (FSM) accurately models the behaviour
of the vending machine, ensuring that it dispenses a chocolate when the
deposited amount reaches or exceeds 15 rupees. The FSM responds
appropriately to the insertion of 10 (D) or 5 (N) rupee coins, and it correctly
restricts any change if the deposited amount surpasses 15 rupees.
○ Moore Sequence Detector Design: The Moore non-overlapping sequence
detector for the pattern "10101" has been effectively designed using D
Flip-Flops. The Verilog HDL code captures the sequential logic required for
detecting the specified sequence. The simulation results validate the correct
Registration Number : 22BCE3969
Name : Jai Sharma

functioning of the sequence detector, confirming its ability to recognize the

non-overlapping occurrences of the pattern "10101" in the input sequence.
● Inference:
Hence we were able to write Verilog HDL code for ALU Design, Automated
Vending Machine and Moore Sequence Detector.