Elements of Computing Systems-1

Combinational Logic (Part 4)

Dr. Jyothish Lal G, Assistant Professor (Sr. Gr)

Department of AI / Center for Computational Engineering and Networking (CEN)
Amrita School of AI, Coimbatore
Acknowledgment: Prof. Noam Nisan, Prof. Shimon Schocken
 Parallel Subtractor
• A-B can be performed by taking the 2’s complement of B and adding to A
• 2’s complement→ 1’s complement +1
• Let Xi=Bi’

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 Multiplexer (MUX)
• A digital multiplexer is a combinational circuit that selects binary
information from one of many inputs and direct it to single output line

• The selection of a particular line is controlled by a set of selection lines

• In general, there are n data lines and m selection lines
n=2m
• Usually, we denote it as 2m to 1 multiplexer
• Also known as data selector

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Implementation of 2-to-1 MUX

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 Gate level logic
S0 D1 D0

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Chip logic Diagram HDL Description I0=D0,
I1=D1

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2-to-1 MUX using NAND gates

So ’
D0

So f
D1

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Implementation of 4-to-1 MUX
Truth table (Compact form)

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 Gate level logic
S1 S0 D0 D1 D2 D3

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 HDL Description

Chip logic Diagram

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 4-to-1 MUX using 2-to-1 MUX
If S0 =0

If S0 =1 ✓

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 HDL code

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8-to-1 MUX using smaller MUX-es

✓
✓

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 HACK exercises
• Implement 2-to-1 MUX
• Implement 4-to-1 MUX
• Implement 8-to-1 MUX
• Implement 4-to-1 MUX using 2-to-1 MUX
• Implement 8-to-1 MUX using smaller MUX-es

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 Thank You

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