Memory Test

Ganesh C. Patil

Tuesday, November 7, 2023

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Density and Defect Trends
 1970 -- DRAM Invention (Intel) 1024 bits
 1993 -- 1st 256 MBit DRAM papers
 1997 -- 1st 256 MBit DRAM samples
 Kilburn -- Ferranti Atlas computer
¢ ¢
(Manchester U.) -- Invented Virtual Memory
 1997 -- Cache DRAM -- SRAM cache + DRAM now
on 1 chip

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Memory Cells Per Chip

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 Test Time in Seconds
(Memory Size n Bits)
Size Number of Test Algorithm Operations

n n n
2
n X log2n

1 Mb 0.06 1.26 18.3 hr

4 Mb 0.25 5.54 293.2 hr
16 Mb 1.01 24.16 4691.3 hr
64 Mb 4.03 104.7 75060.0 hr
256 Mb 16.11 451.0 1200959.9 hr
1 Gb 64.43 1932.8 19215358.4 hr
2 Gb 128.9 3994.4 76861433.7 hr

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Notation
 0 -- A cell is in logical state 0
 1 -- A cell is in logical state 1
 X -- A cell is in logical state X
 A -- A memory address
 ABF -- AND Bridging Fault
 AF -- Address Decoder Fault
 B -- Memory # bits in a word
 BF -- Bridging Fault
 C -- A Memory Cell
 CF -- Coupling Fault

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 Notation (Continued)
 CFdyn -- Dynamic Coupling Fault
 CFid -- Idempotent Coupling Fault
 CFin -- Inversion Coupling Fault
 coupling cell – cell whose change causes another cell
to change
 coupled cell – cell forced to change by a coupling cell
 DRF -- RAM Data Retention Fault
 k -- Size of a neighborhood
 M -- memory cells, words, or address set
 n -- # of Memory bits
 N -- Number of address bits: n = 2N
 NPSF -- Neighborhood Pattern Sensitive Fault

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Notation (Continued)
 OBF -- OR Bridging Fault
 SAF -- Stuck-at Fault
 SCF -- State Coupling Fault
 SOAF -- Stuck-Open Address Decoder
Fault
 TF -- Transition Fault

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Faults
 System -- Mixed electronic, electromechanical,
chemical, and photonic system (MEMS
technology)
 Failure -- Incorrect or interrupted system
behavior
 Error -- Manifestation of fault in system
 Fault -- Physical difference between good &
bad system behavior

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Fault Types
 Fault types:
 Permanent -- System is broken and stays
broken the same way indefinitely
 Transient -- Fault temporarily affects the
system behavior, and then the system reverts
to the good machine -- time dependency,
caused by environmental condition
 Intermittent -- Sometimes causes a failure,
sometimes does not

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Failure Mechanisms
 Permanent faults:
 Missing/Added Electrical Connection
 Broken Component (IC mask defect or
silicon-to-metal connection)
 Burnt-out Chip Wire
 Corroded connection between chip &
package
 Chip logic error (Pentium division bug)

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Failure Mechanisms (Continued)
 Transient Faults:
 Cosmic Ray
 An a particle (ionized Helium atom)
 Air pollution (causes wire short/open)
 Humidity (temporary short)
 Temperature (temporary logic error)
 Pressure (temporary wire open/short)
 Vibration (temporary wire open)
 Power Supply Fluctuation (logic error)
 Electromagnetic Interference (coupling)
 Static Electrical Discharge (change state)
 Ground Loop (misinterpreted logic value)
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Failure Mechanisms (Continued)
 Intermittent Faults:
 Loose Connections
 Aging Components (changed logic delays)
 Hazards and Races in critical timing paths (bad
design)
 Resistor, Capacitor, Inductor variances (timing
faults)
 Physical Irregularities (narrow wire -- high
resistance)
 Electrical Noise (memory state changes)

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Physical Failure Mechanisms
 Corrosion
 Electromigration
 Bonding Deterioration -- Au package wires
interdiffuse with Al chip pads
 Ionic Contamination -- Na+ diffuses through
package and into FET gate oxide
 Alloying -- Al migrates from metal layers into Si
substrate
 Radiation and Cosmic Rays -- 8 MeV, collides
with Si lattice, generates n - p pairs, causes soft
memory error
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Memory Test Levels

Chip, Array,
& Board

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March Test Notation
 r -- Read a memory location
 w -- Write a memory location
 r0 -- Read a 0 from a memory location
 r1 -- Read a 1 from a memory location
 w0 -- Write a 0 to a memory location
 w1 -- Write a 1 to a memory location
 -- Write a 1 to a cell containing 0
 -- Write a 0 to a cell containing 1

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March Test Notation (Continued)
 -- Complement the cell contents

 -- Increasing memory addressing

 -- Decreasing memory addressing

 -- Either increasing or decreasing

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 More March Test Notation
A
 -- Any write operation
 < ... > -- Denotes a particular fault, ...
 <I / F > -- I is the fault sensitizing condition,
F is the faulty cell value
 <I1, ..., In-1 ; In / F> -- Denotes a fault
covering n cells
 I1, ..., In-1 are fault sensitization conditions in
cells 1 through n - 1 for cell n
 In gives sensitization condition for cell n
 If In is empty, write In / F as F
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MATS+ March Test
M0: { March element (w0) }
for cell := 0 to n - 1 (or any other order) do
write 0 to A [cell];
M1: { March element (r0, w1) }
for cell := 0 to n - 1 do
read A [cell]; { Expected value = 0}
write 1 to A [cell];
M2: {March element (r1, w0) }
for cell := n – 1 down to 0 do
read A [cell]; { Expected value = 1 }
write 0 to A [cell];

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Fault Modeling
 Behavioral Model -- State machine
modeling all memory content
combinations -- Intractable
 Functional Model -- Used
 Logic Gate Model -- Not used
Inadequately models transistors &
capacitors
 Electrical Model -- Very expensive
 Geometrical Model -- Layout Model

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Functional Model

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Simplified Functional Model

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 Reduced Functional Model (van de
Goor)
 n Memory bits, B bits/word, n/B addresses
 Access happens when Address Latch contents change
 Low-order address bits operate column decoder, high-
order operate row decoder
 read -- Precharge bit lines, then activate row
 write -- Keep driving bit lines during evaluation
 Refresh -- Read all bits in 1 row and simultaneously
refresh them

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22
Subset Functional Faults

Functional fault
a Cell stuck
b Driver stuck
c Read/write line stuck
d Chip-select line stuck
e Data line stuck
f Open circuit in data line
g Short circuit between data lines
h Crosstalk between data lines

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 Subset Functional Faults
(Continued)
Functional fault
i Address line stuck
j Open circuit in address line
k Shorts between address lines
l Open circuit in decoder
m Wrong address access
n Multiple simultaneous address access
o Cell can be set to 0 but not to 1 (or vice versa)
p Pattern sensitive cell interaction

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Reduced Functional Faults

Fault
SAF Stuck-at fault
TF Transition fault
CF Coupling fault
NPSF Neighborhood Pattern Sensitive fault

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Reduced Functional Faults
Fault Functional fault
SAF a Cell stuck
SAF b Driver stuck
SAF c Read/write line stuck
SAF d Chip-select line stuck
SAF e Data line stuck
SAF f Open circuit in data line
CF g Short circuit between data lines
CF h Crosstalk between data lines
AF i Address line stuck
AF j Open circuit in address line
AF k Shorts between address lines
AF l Open circuit in decoder
AF m Wrong address access
AF n Multiple simultaneous address access
TF o Cell can be set to 0 (1) but not to 1 (0)
NPSF p Pattern sensitive cell interaction

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Fault Modeling Example 1

SA0
SAF
AF+SAF

SCF<0;0> SA0 SCF<1;1>

SA0 TF< /0>
TF< /1>

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Fault Modeling Example 2
SA1 gg SA1+SCF

AF
AF

SCF
SA0

AF
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Delay Test

Ganesh C. Patil

Tuesday, November 7, 2023

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Delay Test Definition
 A circuit that passes delay test must produce
correct outputs when inputs are applied and
outputs observed with specified timing.
 For a combinational or synchronous
sequential circuit, delay test verifies the limits
of delay in combinational logic.
 Delay test problem for asynchronous circuits
is complex and not well understood.

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 Digital Circuit Timing
Input Output Transient
Signal Observation region
changes instant

Inputs
Comb.
logic

Outputs
Synchronized
With clock
time
Clock period
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Circuit Delays
 Switching or inertial delay is the interval between input change
and output change of a gate:
 Depends on input capacitance, device (transistor)
characteristics and output capacitance of gate.
 Also depends on input rise or fall times and states of other
inputs (second-order effects).
 Approximation: fixed rise and fall delays (or min-max
delay range, or single fixed delay) for gate output.
 Propagation or interconnect delay is the time a transition takes
to travel between gates:
 Depends on transmission line effects (distributed R, L, C
parameters, length and loading) of routing paths.
 Approximation: modeled as lumped delays for gate inputs.

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Event Propagation Delays
Single lumped inertial delay modeled for each gate
PI transitions assumed to occur without time skew
Path P1

1 3
0 1

2 4 6
P2 1

0 2 3
P3

0 2 5

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Circuit Outputs
 Each path can potentially produce one signal
transition at the output.
 The location of an output transition in time is
determined by the delay of the path.

Clock period
Final value

Initial value

Fast transitions Slow transitions

time
Initial value Final value

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 Singly-Testable Paths (Non-Robust Test)
 The delay of a target path is tested if the test propagates a
transition via path to a path destination.
 Delay test is a combinational vector-pair, V1,V2, that:
 Produces a transition at path input.
 Produces static sensitization -- All off-path inputs assume
non-controlling states in V2.
don’t
care
V1 V2 Off-path inputs
V1 V2

Target
path
Static sensitization guarantees a test when the target path is the only
faulty path. The test is, therefore, called non-robust. It is a test with
minimal restriction. A path with no such test is a false path.

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Non-robust Test Example

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Non-robust Test Example

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Robust Test
 A robust test guarantees the detection of a delay
fault of the target path, irrespective of delay faults
on other paths.
 A robust test is a combinational vector-pair, V1,
V2, that satisfies following conditions:
 Produce real events (different steady-state
values for V1 and V2) on all on-path signals.
 All on-path signals must have controlling
events arriving via the target path.
 A robust test is also a non-robust test.
 Concept of robust test is general – robust tests for
other fault models can be defined.

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Robust Test Conditions
 Real events on target path.
 Controlling events via target path.

V1 V2 V1 V2
V1 V2
V1 V2 U0
U1
U0
U1
U1/R1 U0/F0 U0/F0
U1/R1

V1 V2 V1 V2
S1 S0
S1 S0
U0/F0 U0/F0 U1/R1 U1/R1

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A Five-Valued Algebra
 Signal States: S0, U0 (F0), S1, U1 (R1), XX.
 On-path signals: F0 and R1.
 Off-path signals: F0=U0 and R1=U1.

Input 1 Input 1
AND S0 U0 S1 U1 XX OR S0 U0 S1 U1 XX

S0 S0 S0 S0 S0 S0 S0 S0 U0 S1 U1 XX
Input 2

Input 2
U0 S0 U0 U0 U0 U0 U0 U0 U0 S1 U1 XX
S1 S0 U0 S1 U1 XX S1 S1 S1 S1 S1 S1
U1 S0 U0 U1 U1 XX U1 U1 U1 S1 U1 U1
XX S0 U0 XX XX XX XX XX XX S1 U1 XX

Input
NOT S0 U0 S1 U1 XX

S1 U1 S0 U0 XX
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 Robust Test Generation
Test for ↓ P3 – falling transition through path P3: Steps A through E
E. Set input of AND gate to
S0 to justify S0 at output
XX S0 S0
C. F0 interpreted as U0; U0 D. Change off-path input
propagates through U0 to S0 to Propagate R1
AND gate through OR gate

A. Place F0 at R1
path origin Path P3
F0

XX F0 R1
U0 Robust Test:
B. Propagate F0 through OR gate; S0, F0, U0
also propagates as R1 through
NOT gate

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Non-Robust Test Generation
Fault ↑ P2 – rising transition through path P2
C. Set input of AND gate to
propagate R1 to output D. R1 non-robustly propagates
XX U1 through OR gate since off-
R1 path input is not S0
R1

Path P2 U1
A. Place R1 at
path origin
R1
R1 U1 U0
XX
U0
B. Propagate R1 through OR gate;
interpreted as U1 on off-path signal; Non-robust test:
propagates as U0 through NOT gate U1, R1, U0

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 Other Delay Fault Models
 Segment-delay fault – A segment of an I/O path is assumed to
have large delay such that all paths containing the segment
become faulty.
 Transition fault – A segment-delay fault with segment of unit
length (single gate):
 Two faults per gate; slow-to-rise and slow-to-fall.
 Tests are similar to stuck-at fault tests. For example, a line is
initialized to 0 and then tested for s-a-0 fault to detect slow-to-
rise transition fault.
 Models spot (or gross) delay defects.
 Line-delay fault – A transition fault tested through the longest
delay path. Two faults per line or gate. Tests are dependent on
modeled delays of gates.
 Gate-delay fault – A gate is assumed to have a delay increase of
certain amount (called fault size) while all other gates retain
some nominal delays. Gate-delay faults only of certain sizes
may be detectable.

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Thank you !!!

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