IDDQ Testing

Ganesh C. Patil

Tuesday, November 7, 2023

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Motivation
 Early 1990’s – Fabrication Line had 50 to 1000
defects per million (dpm) chips
 IBM wants to get 3.4 defects per million (dpm) chips
 Conventional way to reduce defects:
 Increasing test fault coverage
 Increasing burn-in coverage
 Increase Electro-Static Damage awareness
 New way to reduce defects:
 IDDQ Testing – also useful for Failure Effect
Analysis

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Basic Principle of IDDQ Testing

 Measure IDDQ current through Vss bus

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Faults Detected by IDDQ Tests

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Stuck-at Faults Detected by IDDQ Tests
 Bridging faults with stuck-at fault behavior
 Levi – Bridging of a logic node to VDD or VSS –
few of these
 Transistor gate oxide short
 Floating MOSFET gate defects – do not
fully turn off transistor

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NAND Open Circuit Defect – Floating gate

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Floating Gate Defects
 Small break in logic gate inputs (100 – 200
Angstroms) lets wires couple by electron
tunneling
 Delay fault and IDDQ fault
 Large open results in stuck-at fault – not
detectable by IDDQ test
 If Vtn < Vfn < VDD - | Vtp | then detectable by
IDDQ test

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Multiple IDDQ Fault Example

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Capacitive Coupling of Floating Gates
 Cpb – capacitance from poly to
bulk
 Cmp – overlapped metal wire to
poly
 Floating gate voltage depends
on capacitances and node
voltages
 If nFET and pFET get enough
gate voltage to turn them on,
then IDDQ test detects this defect

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 Leakage Faults
 Gate oxide shorts cause leaks between gate &
source or gate & drain
 Mao and Gulati leakage fault model:
 Leakage path flags: fGS, fGD, fSD, fBS, fBD, fBG
G = gate, S = source, D = drain, B = bulk

 Assume that short does not change logic values

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Weak Faults
 nFET passes logic 1 as 5 V – Vtn
 pFET passes logic 0 as 0 V + |Vtp|
 Weak fault – one device in C-switch does not
turn on
 Causes logic value degradation in C-switch

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Transistor Stuck-Closed Faults
 Due to gate oxide
short (GOS)
 k = distance of short
from drain
 Rs = short resistance
 IDDQ2 current results
show 3 or 4 orders of
magnitude elevation

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Gate Oxide Short

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Leakage Fault Table
 k = # component I/O pins
 n = # component transistors
 m = 2k (# of input / output combinations)
 m x n matrix M represents the table
 Each logic state – 1 matrix row
 Entry mi j = octal leakage fault information
 Flags fBG fBD fBS fSD fGD fGS
 Sub-entry mi j = 1 if leakage fault detected

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Example Leakage Fault Table

Flags fBG fBD fBS fSD fGD fGS

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Instrumentation Problems
 Need to measure < 1 mA current at
clock > 10 kHz
 Off-chip IDDQ measurements degraded
 Pulse width of CMOS IC transient current
 Impedance loading of tester probe
 Current leakages in tester
 High noise of tester load board
 Much slower rate of current
measurement than voltage measurement

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Limitations of IDDQ Testing
 Sub-micron technologies have increased
leakage currents
 Transistor sub-threshold conduction
 Harder to find IDDQ threshold separating good &
bad chips
 IDDQ tests work:
 When average defect-induced current greater
than average good IC current
 Small variation in IDDQ over test sequence &
between chips

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Delta IDDQ Testing -- Thibeault
 Use derivative of IDDQ at test vector as
current signature
D IDDQ (i) = IDDQ (i) – IDDQ (i – 1)
 Leads to a narrower histogram
 Eliminates variation between chips and
between wafers
 P – probability of false test decisions

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IDDQ Built-in Current Testing – Maly
and Nigh
 Build current sensor into ground bus of
device-under-test
 Voltage drop device & comparator
 Compares virtual ground VGND with Vref at end
of each clock – VGND > Vref only in bad circuits
 Activates circuit breaker when bad device
found

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Conceptual BIC Sensor

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CMOS BIC Sensor

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Setting Optimal # Transistors in Block
 Must partition chip into functional units, each with
its own BIC
 Too large a unit – combined leakage currents
erroneously trigger BIC sensor
 Idefmin – smallest defect current
 Inoisemax – maximum noise-related peak supply
current
 Minimum area sensor design at Idefmin and IDDQ
intersection
 Nmax – maximum # transistors in 1 BIC unit

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Graph for Choosing Nmax

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Thank you !!!

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